1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #ifdef FTRACE 10 #define CONFIG_TRACE 11 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) 12 #define CONFIG_TRACE_EARLY_SIZE (16 << 20) 13 #define CONFIG_TRACE_EARLY 14 #define CONFIG_TRACE_EARLY_ADDR 0x00100000 15 #endif 16 17 #ifndef CONFIG_SPL_BUILD 18 #define CONFIG_IO_TRACE 19 #endif 20 21 #ifndef CONFIG_TIMER 22 #define CONFIG_SYS_TIMER_RATE 1000000 23 #endif 24 25 #define CONFIG_HOST_MAX_DEVICES 4 26 27 /* 28 * Size of malloc() pool, before and after relocation 29 */ 30 #define CONFIG_MALLOC_F_ADDR 0x0010000 31 #define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ 32 33 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 34 35 /* turn on command-line edit/c/auto */ 36 37 /* SPI - enable all SPI flash types for testing purposes */ 38 39 #define CONFIG_I2C_EDID 40 41 /* Memory things - we don't really want a memory test */ 42 #define CONFIG_SYS_LOAD_ADDR 0x00000000 43 #define CONFIG_SYS_FDT_LOAD_ADDR 0x100 44 45 #define CONFIG_PHYSMEM 46 47 /* Size of our emulated memory */ 48 #define SB_CONCAT(x, y) x ## y 49 #define SB_TO_UL(s) SB_CONCAT(s, UL) 50 #define CONFIG_SYS_SDRAM_BASE 0 51 #define CONFIG_SYS_SDRAM_SIZE \ 52 (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) 53 #define CONFIG_SYS_MONITOR_BASE 0 54 55 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 56 115200} 57 58 #define BOOT_TARGET_DEVICES(func) \ 59 func(HOST, host, 1) \ 60 func(HOST, host, 0) 61 62 #ifdef __ASSEMBLY__ 63 #define BOOTENV 64 #else 65 #include <config_distro_bootcmd.h> 66 #endif 67 68 #define CONFIG_KEEP_SERVERADDR 69 #define CONFIG_UDP_CHECKSUM 70 #define CONFIG_TIMESTAMP 71 #define CONFIG_BOOTP_SERVERIP 72 73 #ifndef SANDBOX_NO_SDL 74 #define CONFIG_SANDBOX_SDL 75 #endif 76 77 /* LCD and keyboard require SDL support */ 78 #ifdef CONFIG_SANDBOX_SDL 79 #define LCD_BPP LCD_COLOR16 80 #define CONFIG_LCD_BMP_RLE8 81 82 #define CONFIG_KEYBOARD 83 84 #define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \ 85 "stdout=serial,vidconsole\0" \ 86 "stderr=serial,vidconsole\0" 87 #else 88 #define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \ 89 "stdout=serial,vidconsole\0" \ 90 "stderr=serial,vidconsole\0" 91 #endif 92 93 #define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ 94 "eth2addr=00:00:11:22:33:48\0" \ 95 "eth3addr=00:00:11:22:33:45\0" \ 96 "eth4addr=00:00:11:22:33:48\0" \ 97 "eth5addr=00:00:11:22:33:46\0" \ 98 "eth6addr=00:00:11:22:33:47\0" \ 99 "ipaddr=1.2.3.4\0" 100 101 #define MEM_LAYOUT_ENV_SETTINGS \ 102 "bootm_size=0x10000000\0" \ 103 "kernel_addr_r=0x1000000\0" \ 104 "fdt_addr_r=0xc00000\0" \ 105 "ramdisk_addr_r=0x2000000\0" \ 106 "scriptaddr=0x1000\0" \ 107 "pxefile_addr_r=0x2000\0" 108 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 SANDBOX_SERIAL_SETTINGS \ 111 SANDBOX_ETH_SETTINGS \ 112 BOOTENV \ 113 MEM_LAYOUT_ENV_SETTINGS 114 115 #ifndef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_IDE_MAXBUS 1 117 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 118 #define CONFIG_SYS_IDE_MAXDEVICE 2 119 #define CONFIG_SYS_ATA_BASE_ADDR 0x100 120 #define CONFIG_SYS_ATA_DATA_OFFSET 0 121 #define CONFIG_SYS_ATA_REG_OFFSET 1 122 #define CONFIG_SYS_ATA_ALT_OFFSET 2 123 #define CONFIG_SYS_ATA_STRIDE 4 124 #endif 125 126 #define CONFIG_SCSI_AHCI_PLAT 127 #define CONFIG_SYS_SCSI_MAX_DEVICE 2 128 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 8 129 #define CONFIG_SYS_SCSI_MAX_LUN 4 130 131 #define CONFIG_SYS_SATA_MAX_DEVICE 2 132 133 #endif 134