1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/system.h>
12 #include <asm/cache.h>
13 #include <linux/compiler.h>
14 #include <asm/armv7_mpu.h>
15
16 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #ifdef CONFIG_SYS_ARM_MMU
arm_init_before_mmu(void)21 __weak void arm_init_before_mmu(void)
22 {
23 }
24
set_section_phys(int section,phys_addr_t phys,enum dcache_option option)25 static void set_section_phys(int section, phys_addr_t phys,
26 enum dcache_option option)
27 {
28 #ifdef CONFIG_ARMV7_LPAE
29 u64 *page_table = (u64 *)gd->arch.tlb_addr;
30 /* Need to set the access flag to not fault */
31 u64 value = TTB_SECT_AP | TTB_SECT_AF;
32 #else
33 u32 *page_table = (u32 *)gd->arch.tlb_addr;
34 u32 value = TTB_SECT_AP;
35 #endif
36
37 /* Add the page offset */
38 value |= phys;
39
40 /* Add caching bits */
41 value |= option;
42
43 /* Set PTE */
44 page_table[section] = value;
45 }
46
set_section_dcache(int section,enum dcache_option option)47 void set_section_dcache(int section, enum dcache_option option)
48 {
49 set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
50 }
51
mmu_page_table_flush(unsigned long start,unsigned long stop)52 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
53 {
54 debug("%s: Warning: not implemented\n", __func__);
55 }
56
mmu_set_region_dcache_behaviour_phys(phys_addr_t start,phys_addr_t phys,size_t size,enum dcache_option option)57 void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
58 size_t size, enum dcache_option option)
59 {
60 #ifdef CONFIG_ARMV7_LPAE
61 u64 *page_table = (u64 *)gd->arch.tlb_addr;
62 #else
63 u32 *page_table = (u32 *)gd->arch.tlb_addr;
64 #endif
65 unsigned long startpt, stoppt;
66 unsigned long upto, end;
67
68 /* div by 2 before start + size to avoid phys_addr_t overflow */
69 end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
70 >> (MMU_SECTION_SHIFT - 1);
71 start = start >> MMU_SECTION_SHIFT;
72
73 #ifdef CONFIG_ARMV7_LPAE
74 debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
75 option);
76 #else
77 debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
78 option);
79 #endif
80 for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
81 set_section_phys(upto, phys, option);
82
83 /*
84 * Make sure range is cache line aligned
85 * Only CPU maintains page tables, hence it is safe to always
86 * flush complete cache lines...
87 */
88
89 startpt = (unsigned long)&page_table[start];
90 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
91 stoppt = (unsigned long)&page_table[end];
92 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
93 mmu_page_table_flush(startpt, stoppt);
94 }
95
mmu_set_region_dcache_behaviour(phys_addr_t start,size_t size,enum dcache_option option)96 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
97 enum dcache_option option)
98 {
99 mmu_set_region_dcache_behaviour_phys(start, start, size, option);
100 }
101
dram_bank_mmu_setup(int bank)102 __weak void dram_bank_mmu_setup(int bank)
103 {
104 struct bd_info *bd = gd->bd;
105 int i;
106
107 /* bd->bi_dram is available only after relocation */
108 if ((gd->flags & GD_FLG_RELOC) == 0)
109 return;
110
111 debug("%s: bank: %d\n", __func__, bank);
112 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
113 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
114 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
115 i++)
116 set_section_dcache(i, DCACHE_DEFAULT_OPTION);
117 }
118
119 /* to activate the MMU we need to set up virtual memory: use 1M areas */
mmu_setup(void)120 static inline void mmu_setup(void)
121 {
122 int i;
123 u32 reg;
124
125 arm_init_before_mmu();
126 /* Set up an identity-mapping for all 4GB, rw for everyone */
127 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
128 set_section_dcache(i, DCACHE_OFF);
129
130 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
131 dram_bank_mmu_setup(i);
132 }
133
134 #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
135 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
136 for (i = 0; i < 4; i++) {
137 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
138 u64 tpt = gd->arch.tlb_addr + (4096 * i);
139 page_table[i] = tpt | TTB_PAGETABLE;
140 }
141
142 reg = TTBCR_EAE;
143 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
144 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
145 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
146 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
147 #else
148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
149 #endif
150
151 if (is_hyp()) {
152 /* Set HTCR to enable LPAE */
153 asm volatile("mcr p15, 4, %0, c2, c0, 2"
154 : : "r" (reg) : "memory");
155 /* Set HTTBR0 */
156 asm volatile("mcrr p15, 4, %0, %1, c2"
157 :
158 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
159 : "memory");
160 /* Set HMAIR */
161 asm volatile("mcr p15, 4, %0, c10, c2, 0"
162 : : "r" (MEMORY_ATTRIBUTES) : "memory");
163 } else {
164 /* Set TTBCR to enable LPAE */
165 asm volatile("mcr p15, 0, %0, c2, c0, 2"
166 : : "r" (reg) : "memory");
167 /* Set 64-bit TTBR0 */
168 asm volatile("mcrr p15, 0, %0, %1, c2"
169 :
170 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
171 : "memory");
172 /* Set MAIR */
173 asm volatile("mcr p15, 0, %0, c10, c2, 0"
174 : : "r" (MEMORY_ATTRIBUTES) : "memory");
175 }
176 #elif defined(CONFIG_CPU_V7A)
177 if (is_hyp()) {
178 /* Set HTCR to disable LPAE */
179 asm volatile("mcr p15, 4, %0, c2, c0, 2"
180 : : "r" (0) : "memory");
181 } else {
182 /* Set TTBCR to disable LPAE */
183 asm volatile("mcr p15, 0, %0, c2, c0, 2"
184 : : "r" (0) : "memory");
185 }
186 /* Set TTBR0 */
187 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
188 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
189 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
190 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
191 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
192 #else
193 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
194 #endif
195 asm volatile("mcr p15, 0, %0, c2, c0, 0"
196 : : "r" (reg) : "memory");
197 #else
198 /* Copy the page table address to cp15 */
199 asm volatile("mcr p15, 0, %0, c2, c0, 0"
200 : : "r" (gd->arch.tlb_addr) : "memory");
201 #endif
202 /*
203 * initial value of Domain Access Control Register (DACR)
204 * Set the access control to client (1U) for each of the 16 domains
205 */
206 asm volatile("mcr p15, 0, %0, c3, c0, 0"
207 : : "r" (0x55555555));
208
209 /* and enable the mmu */
210 reg = get_cr(); /* get control reg. */
211 set_cr(reg | CR_M);
212 }
213
mmu_enabled(void)214 static int mmu_enabled(void)
215 {
216 return get_cr() & CR_M;
217 }
218 #endif /* CONFIG_SYS_ARM_MMU */
219
220 /* cache_bit must be either CR_I or CR_C */
cache_enable(uint32_t cache_bit)221 static void cache_enable(uint32_t cache_bit)
222 {
223 uint32_t reg;
224
225 /* The data cache is not active unless the mmu/mpu is enabled too */
226 #ifdef CONFIG_SYS_ARM_MMU
227 if ((cache_bit == CR_C) && !mmu_enabled())
228 mmu_setup();
229 #elif defined(CONFIG_SYS_ARM_MPU)
230 if ((cache_bit == CR_C) && !mpu_enabled()) {
231 printf("Consider enabling MPU before enabling caches\n");
232 return;
233 }
234 #endif
235 reg = get_cr(); /* get control reg. */
236 set_cr(reg | cache_bit);
237 }
238
239 /* cache_bit must be either CR_I or CR_C */
cache_disable(uint32_t cache_bit)240 static void cache_disable(uint32_t cache_bit)
241 {
242 uint32_t reg;
243
244 reg = get_cr();
245
246 if (cache_bit == CR_C) {
247 /* if cache isn;t enabled no need to disable */
248 if ((reg & CR_C) != CR_C)
249 return;
250 #ifdef CONFIG_SYS_ARM_MMU
251 /* if disabling data cache, disable mmu too */
252 cache_bit |= CR_M;
253 #endif
254 }
255 reg = get_cr();
256
257 #ifdef CONFIG_SYS_ARM_MMU
258 if (cache_bit == (CR_C | CR_M))
259 #elif defined(CONFIG_SYS_ARM_MPU)
260 if (cache_bit == CR_C)
261 #endif
262 flush_dcache_all();
263 set_cr(reg & ~cache_bit);
264 }
265 #endif
266
267 #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable(void)268 void icache_enable(void)
269 {
270 return;
271 }
272
icache_disable(void)273 void icache_disable(void)
274 {
275 return;
276 }
277
icache_status(void)278 int icache_status(void)
279 {
280 return 0; /* always off */
281 }
282 #else
icache_enable(void)283 void icache_enable(void)
284 {
285 cache_enable(CR_I);
286 }
287
icache_disable(void)288 void icache_disable(void)
289 {
290 cache_disable(CR_I);
291 }
292
icache_status(void)293 int icache_status(void)
294 {
295 return (get_cr() & CR_I) != 0;
296 }
297 #endif
298
299 #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable(void)300 void dcache_enable(void)
301 {
302 return;
303 }
304
dcache_disable(void)305 void dcache_disable(void)
306 {
307 return;
308 }
309
dcache_status(void)310 int dcache_status(void)
311 {
312 return 0; /* always off */
313 }
314 #else
dcache_enable(void)315 void dcache_enable(void)
316 {
317 cache_enable(CR_C);
318 }
319
dcache_disable(void)320 void dcache_disable(void)
321 {
322 cache_disable(CR_C);
323 }
324
dcache_status(void)325 int dcache_status(void)
326 {
327 return (get_cr() & CR_C) != 0;
328 }
329 #endif
330