1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
4 * Author: Tor Krill <tor@excito.com>
5 *
6 * This is a driver for Silicon Image sil3114 sata chip modelled on
7 * the ata_piix driver
8 */
9
10 #include <common.h>
11 #include <blk.h>
12 #include <log.h>
13 #include <part.h>
14 #include <pci.h>
15 #include <command.h>
16 #include <config.h>
17 #include <asm/byteorder.h>
18 #include <asm/io.h>
19 #include <ide.h>
20 #include <sata.h>
21 #include <libata.h>
22 #include <linux/delay.h>
23 #include "sata_sil3114.h"
24
25 /* Convert sectorsize to wordsize */
26 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
27
28 /* Forwards */
29 u8 sil3114_spin_up (int num);
30 u8 sil3114_spin_down (int num);
31 static int sata_bus_softreset (int num);
32 static void sata_identify (int num, int dev);
33 static u8 check_power_mode (int num);
34 static void sata_port (struct sata_ioports *ioport);
35 static void set_Feature_cmd (int num, int dev);
36 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
37 unsigned int max, u8 usealtstatus);
38 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
39 static void msleep (int count);
40
41 static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
42
43 static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
44
output_data(struct sata_ioports * ioaddr,u16 * sect_buf,int words)45 static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
46 {
47 while (words--) {
48 __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
49 }
50 }
51
input_data(struct sata_ioports * ioaddr,u16 * sect_buf,int words)52 static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
53 {
54 while (words--) {
55 *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
56 }
57 return 0;
58 }
59
sata_bus_softreset(int num)60 static int sata_bus_softreset (int num)
61 {
62 u8 status = 0;
63
64 port[num].dev_mask = 1;
65
66 port[num].ctl_reg = 0x08; /*Default value of control reg */
67 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
68 udelay(10);
69 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
70 udelay(10);
71 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
72
73 /* spec mandates ">= 2ms" before checking status.
74 * We wait 150ms, because that was the magic delay used for
75 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
76 * between when the ATA command register is written, and then
77 * status is checked. Because waiting for "a while" before
78 * checking status is fine, post SRST, we perform this magic
79 * delay here as well.
80 */
81 msleep (150);
82 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
83 while ((status & ATA_BUSY)) {
84 msleep (100);
85 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
86 }
87
88 if (status & ATA_BUSY) {
89 printf ("ata%u is slow to respond,plz be patient\n", num);
90 }
91
92 while ((status & ATA_BUSY)) {
93 msleep (100);
94 status = sata_chk_status (&port[num].ioaddr, 0);
95 }
96
97 if (status & ATA_BUSY) {
98 printf ("ata%u failed to respond : ", num);
99 printf ("bus reset failed\n");
100 port[num].dev_mask = 0;
101 return 1;
102 }
103 return 0;
104 }
105
sata_identify(int num,int dev)106 static void sata_identify (int num, int dev)
107 {
108 u8 cmd = 0, status = 0, devno = num;
109 u16 iobuf[ATA_SECTOR_WORDS];
110 u64 n_sectors = 0;
111
112 memset (iobuf, 0, sizeof (iobuf));
113
114 if (!(port[num].dev_mask & 0x01)) {
115 printf ("dev%d is not present on port#%d\n", dev, num);
116 return;
117 }
118
119 debug ("port=%d dev=%d\n", num, dev);
120
121 status = 0;
122 cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
123 writeb (cmd, port[num].ioaddr.command_addr);
124 readb (port[num].ioaddr.altstatus_addr);
125 udelay(10);
126
127 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
128 if (status & ATA_ERR) {
129 printf ("\ndevice not responding\n");
130 port[num].dev_mask &= ~0x01;
131 return;
132 }
133
134 input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
135
136 ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
137
138 debug ("Specific config: %x\n", iobuf[2]);
139
140 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
141 if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
142 debug ("ata%u: no dma/lba\n", num);
143 }
144 #ifdef DEBUG
145 ata_dump_id (iobuf);
146 #endif
147 n_sectors = ata_id_n_sectors (iobuf);
148
149 if (n_sectors == 0) {
150 port[num].dev_mask &= ~0x01;
151 return;
152 }
153 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
154 ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
155 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
156 ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
157 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
158 ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
159
160 /* TODO - atm we asume harddisk ie not removable */
161 sata_dev_desc[devno].removable = 0;
162
163 sata_dev_desc[devno].lba = (u32) n_sectors;
164 debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
165
166 #ifdef CONFIG_LBA48
167 if (iobuf[83] & (1 << 10)) {
168 sata_dev_desc[devno].lba48 = 1;
169 } else {
170 sata_dev_desc[devno].lba48 = 0;
171 }
172 #endif
173
174 /* assuming HD */
175 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
176 sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
177 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
178 }
179
set_Feature_cmd(int num,int dev)180 static void set_Feature_cmd (int num, int dev)
181 {
182 u8 status = 0;
183
184 if (!(port[num].dev_mask & 0x01)) {
185 debug ("dev%d is not present on port#%d\n", dev, num);
186 return;
187 }
188
189 writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
190 writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
191 writeb (0, port[num].ioaddr.lbal_addr);
192 writeb (0, port[num].ioaddr.lbam_addr);
193 writeb (0, port[num].ioaddr.lbah_addr);
194
195 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
196 writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
197
198 udelay(50);
199 msleep (150);
200
201 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
202 if ((status & (ATA_BUSY | ATA_ERR))) {
203 printf ("Error : status 0x%02x\n", status);
204 port[num].dev_mask &= ~0x01;
205 }
206 }
207
sil3114_spin_down(int num)208 u8 sil3114_spin_down (int num)
209 {
210 u8 status = 0;
211
212 debug ("Spin down disk\n");
213
214 if (!(port[num].dev_mask & 0x01)) {
215 debug ("Device ata%d is not present\n", num);
216 return 1;
217 }
218
219 if ((status = check_power_mode (num)) == 0x00) {
220 debug ("Already in standby\n");
221 return 0;
222 }
223
224 if (status == 0x01) {
225 printf ("Failed to check power mode on ata%d\n", num);
226 return 1;
227 }
228
229 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
230 printf ("Device ata%d not ready\n", num);
231 return 1;
232 }
233
234 writeb (0x00, port[num].ioaddr.feature_addr);
235
236 writeb (0x00, port[num].ioaddr.nsect_addr);
237 writeb (0x00, port[num].ioaddr.lbal_addr);
238 writeb (0x00, port[num].ioaddr.lbam_addr);
239 writeb (0x00, port[num].ioaddr.lbah_addr);
240
241 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
242 writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
243
244 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
245 if ((status & (ATA_BUSY | ATA_ERR))) {
246 printf ("Error waiting for disk spin down: status 0x%02x\n",
247 status);
248 port[num].dev_mask &= ~0x01;
249 return 1;
250 }
251 return 0;
252 }
253
sil3114_spin_up(int num)254 u8 sil3114_spin_up (int num)
255 {
256 u8 status = 0;
257
258 debug ("Spin up disk\n");
259
260 if (!(port[num].dev_mask & 0x01)) {
261 debug ("Device ata%d is not present\n", num);
262 return 1;
263 }
264
265 if ((status = check_power_mode (num)) != 0x00) {
266 if (status == 0x01) {
267 printf ("Failed to check power mode on ata%d\n", num);
268 return 1;
269 } else {
270 /* should be up and running already */
271 return 0;
272 }
273 }
274
275 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
276 printf ("Device ata%d not ready\n", num);
277 return 1;
278 }
279
280 debug ("Stautus of device check: %d\n", status);
281
282 writeb (0x00, port[num].ioaddr.feature_addr);
283
284 writeb (0x00, port[num].ioaddr.nsect_addr);
285 writeb (0x00, port[num].ioaddr.lbal_addr);
286 writeb (0x00, port[num].ioaddr.lbam_addr);
287 writeb (0x00, port[num].ioaddr.lbah_addr);
288
289 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
290 writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
291
292 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
293 if ((status & (ATA_BUSY | ATA_ERR))) {
294 printf ("Error waiting for disk spin up: status 0x%02x\n",
295 status);
296 port[num].dev_mask &= ~0x01;
297 return 1;
298 }
299
300 /* Wait for disk to enter Active state */
301 do {
302 msleep (10);
303 status = check_power_mode (num);
304 } while ((status == 0x00) || (status == 0x80));
305
306 if (status == 0x01) {
307 printf ("Falied waiting for disk to spin up\n");
308 return 1;
309 }
310
311 return 0;
312 }
313
314 /* Return value is not the usual here
315 * 0x00 - Device stand by
316 * 0x01 - Operation failed
317 * 0x80 - Device idle
318 * 0xff - Device active
319 */
check_power_mode(int num)320 static u8 check_power_mode (int num)
321 {
322 u8 status = 0;
323 u8 res = 0;
324 if (!(port[num].dev_mask & 0x01)) {
325 debug ("Device ata%d is not present\n", num);
326 return 1;
327 }
328
329 if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
330 printf ("Device ata%d not ready\n", num);
331 return 1;
332 }
333
334 writeb (0, port[num].ioaddr.feature_addr);
335 writeb (0, port[num].ioaddr.nsect_addr);
336 writeb (0, port[num].ioaddr.lbal_addr);
337 writeb (0, port[num].ioaddr.lbam_addr);
338 writeb (0, port[num].ioaddr.lbah_addr);
339
340 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
341 writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
342
343 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
344 if ((status & (ATA_BUSY | ATA_ERR))) {
345 printf
346 ("Error waiting for check power mode complete : status 0x%02x\n",
347 status);
348 port[num].dev_mask &= ~0x01;
349 return 1;
350 }
351 res = readb (port[num].ioaddr.nsect_addr);
352 debug ("Check powermode: %d\n", res);
353 return res;
354
355 }
356
sata_port(struct sata_ioports * ioport)357 static void sata_port (struct sata_ioports *ioport)
358 {
359 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
360 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
361 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
362 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
363 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
364 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
365 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
366 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
367 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
368 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
369 }
370
wait_for_irq(int num,unsigned int max)371 static u8 wait_for_irq (int num, unsigned int max)
372 {
373
374 u32 port = iobase[5];
375 switch (num) {
376 case 0:
377 port += VND_TF_CNST_CH0;
378 break;
379 case 1:
380 port += VND_TF_CNST_CH1;
381 break;
382 case 2:
383 port += VND_TF_CNST_CH2;
384 break;
385 case 3:
386 port += VND_TF_CNST_CH3;
387 break;
388 default:
389 return 1;
390 }
391
392 do {
393 if (readl (port) & VND_TF_CNST_INTST) {
394 break;
395 }
396 udelay(1000);
397 max--;
398 } while ((max > 0));
399
400 return (max == 0);
401 }
402
sata_busy_wait(struct sata_ioports * ioaddr,int bits,unsigned int max,u8 usealtstatus)403 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
404 unsigned int max, u8 usealtstatus)
405 {
406 u8 status;
407
408 do {
409 if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
410 break;
411 }
412 udelay(1000);
413 max--;
414 } while ((status & bits) && (max > 0));
415
416 return status;
417 }
418
sata_chk_status(struct sata_ioports * ioaddr,u8 usealtstatus)419 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
420 {
421 if (!usealtstatus) {
422 return readb (ioaddr->status_addr);
423 } else {
424 return readb (ioaddr->altstatus_addr);
425 }
426 }
427
msleep(int count)428 static void msleep (int count)
429 {
430 int i;
431
432 for (i = 0; i < count; i++)
433 udelay(1000);
434 }
435
436 /* Read up to 255 sectors
437 *
438 * Returns sectors read
439 */
do_one_read(int device,ulong block,u8 blkcnt,u16 * buff,uchar lba48)440 static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
441 uchar lba48)
442 {
443
444 u8 sr = 0;
445 u8 status;
446 u64 blknr = (u64) block;
447
448 if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
449 printf ("Device ata%d not ready\n", device);
450 return 0;
451 }
452
453 /* Set up transfer */
454 #ifdef CONFIG_LBA48
455 if (lba48) {
456 /* write high bits */
457 writeb (0, port[device].ioaddr.nsect_addr);
458 writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
459 writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
460 writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
461 }
462 #endif
463 writeb (blkcnt, port[device].ioaddr.nsect_addr);
464 writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
465 writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
466 writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
467
468 #ifdef CONFIG_LBA48
469 if (lba48) {
470 writeb (ATA_LBA, port[device].ioaddr.device_addr);
471 writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
472 } else
473 #endif
474 {
475 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
476 port[device].ioaddr.device_addr);
477 writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
478 }
479
480 status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
481
482 if (status & ATA_BUSY) {
483 u8 err = 0;
484
485 printf ("Device %d not responding status %d\n", device, status);
486 err = readb (port[device].ioaddr.error_addr);
487 printf ("Error reg = 0x%x\n", err);
488
489 return (sr);
490 }
491 while (blkcnt--) {
492
493 if (wait_for_irq (device, 500)) {
494 printf ("ata%u irq failed\n", device);
495 return sr;
496 }
497
498 status = sata_chk_status (&port[device].ioaddr, 0);
499 if (status & ATA_ERR) {
500 printf ("ata%u error %d\n", device,
501 readb (port[device].ioaddr.error_addr));
502 return sr;
503 }
504 /* Read one sector */
505 input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
506 buff += ATA_SECTOR_WORDS;
507 sr++;
508
509 }
510 return sr;
511 }
512
sata_read(int device,ulong block,lbaint_t blkcnt,void * buff)513 ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
514 {
515 ulong n = 0, sread;
516 u16 *buffer = (u16 *) buff;
517 u8 status = 0;
518 u64 blknr = (u64) block;
519 unsigned char lba48 = 0;
520
521 #ifdef CONFIG_LBA48
522 if (blknr > 0xfffffff) {
523 if (!sata_dev_desc[device].lba48) {
524 printf ("Drive doesn't support 48-bit addressing\n");
525 return 0;
526 }
527 /* more than 28 bits used, use 48bit mode */
528 lba48 = 1;
529 }
530 #endif
531
532 while (blkcnt > 0) {
533
534 if (blkcnt > 255) {
535 sread = 255;
536 } else {
537 sread = blkcnt;
538 }
539
540 status = do_one_read (device, blknr, sread, buffer, lba48);
541 if (status != sread) {
542 printf ("Read failed\n");
543 return n;
544 }
545
546 blkcnt -= sread;
547 blknr += sread;
548 n += sread;
549 buffer += sread * ATA_SECTOR_WORDS;
550 }
551 return n;
552 }
553
sata_write(int device,ulong block,lbaint_t blkcnt,const void * buff)554 ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
555 {
556 ulong n = 0;
557 u16 *buffer = (u16 *) buff;
558 unsigned char status = 0, num = 0;
559 u64 blknr = (u64) block;
560 #ifdef CONFIG_LBA48
561 unsigned char lba48 = 0;
562
563 if (blknr > 0xfffffff) {
564 if (!sata_dev_desc[device].lba48) {
565 printf ("Drive doesn't support 48-bit addressing\n");
566 return 0;
567 }
568 /* more than 28 bits used, use 48bit mode */
569 lba48 = 1;
570 }
571 #endif
572 /*Port Number */
573 num = device;
574
575 while (blkcnt-- > 0) {
576 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
577 if (status & ATA_BUSY) {
578 printf ("ata%u failed to respond\n", port[num].port_no);
579 return n;
580 }
581 #ifdef CONFIG_LBA48
582 if (lba48) {
583 /* write high bits */
584 writeb (0, port[num].ioaddr.nsect_addr);
585 writeb ((blknr >> 24) & 0xFF,
586 port[num].ioaddr.lbal_addr);
587 writeb ((blknr >> 32) & 0xFF,
588 port[num].ioaddr.lbam_addr);
589 writeb ((blknr >> 40) & 0xFF,
590 port[num].ioaddr.lbah_addr);
591 }
592 #endif
593 writeb (1, port[num].ioaddr.nsect_addr);
594 writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
595 writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
596 writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
597 #ifdef CONFIG_LBA48
598 if (lba48) {
599 writeb (ATA_LBA, port[num].ioaddr.device_addr);
600 writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
601 } else
602 #endif
603 {
604 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
605 port[num].ioaddr.device_addr);
606 writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
607 }
608
609 msleep (50);
610 /*may take up to 4 sec */
611 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
612 if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
613 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
614 device, (ulong) blknr, status);
615 return (n);
616 }
617
618 output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
619 readb (port[num].ioaddr.altstatus_addr);
620 udelay(50);
621
622 ++n;
623 ++blknr;
624 buffer += ATA_SECTOR_WORDS;
625 }
626 return n;
627 }
628
629 /* Driver implementation */
sil_get_device_cache_line(pci_dev_t pdev)630 static u8 sil_get_device_cache_line (pci_dev_t pdev)
631 {
632 u8 cache_line = 0;
633 pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
634 return cache_line;
635 }
636
init_sata(int dev)637 int init_sata (int dev)
638 {
639 static u8 init_done = 0;
640 static int res = 1;
641 pci_dev_t devno;
642 u8 cls = 0;
643 u16 cmd = 0;
644 u32 sconf = 0;
645
646 if (init_done) {
647 return res;
648 }
649
650 init_done = 1;
651
652 if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
653 res = 1;
654 return res;
655 }
656
657 /* Read out all BARs, even though we only use MMIO from BAR5 */
658 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
659 pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
660 pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
661 pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
662 pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
663 pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
664
665 if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
666 (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
667 (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
668 printf ("Error no base addr for SATA controller\n");
669 res = 1;
670 return res;
671 }
672
673 /* mask off unused bits */
674 iobase[0] &= 0xfffffffc;
675 iobase[1] &= 0xfffffff8;
676 iobase[2] &= 0xfffffffc;
677 iobase[3] &= 0xfffffff8;
678 iobase[4] &= 0xfffffff0;
679 iobase[5] &= 0xfffffc00;
680
681 /* from sata_sil in Linux kernel */
682 cls = sil_get_device_cache_line (devno);
683 if (cls) {
684 cls >>= 3;
685 cls++; /* cls = (line_size/8)+1 */
686 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
687 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
688 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
689 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
690 } else {
691 printf ("Cache line not set. Driver may not function\n");
692 }
693
694 /* Enable operation */
695 pci_read_config_word (devno, PCI_COMMAND, &cmd);
696 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
697 pci_write_config_word (devno, PCI_COMMAND, cmd);
698
699 /* Disable interrupt usage */
700 pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
701 sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
702 pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
703
704 res = 0;
705 return res;
706 }
707
reset_sata(int dev)708 int reset_sata(int dev)
709 {
710 return 0;
711 }
712
713 /* Check if device is connected to port */
sata_bus_probe(int portno)714 int sata_bus_probe (int portno)
715 {
716 u32 port = iobase[5];
717 u32 val;
718 switch (portno) {
719 case 0:
720 port += VND_SSTATUS_CH0;
721 break;
722 case 1:
723 port += VND_SSTATUS_CH1;
724 break;
725 case 2:
726 port += VND_SSTATUS_CH2;
727 break;
728 case 3:
729 port += VND_SSTATUS_CH3;
730 break;
731 default:
732 return 0;
733 }
734 val = readl (port);
735 if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
736 return 1;
737 } else {
738 return 0;
739 }
740 }
741
sata_phy_reset(int portno)742 int sata_phy_reset (int portno)
743 {
744 u32 port = iobase[5];
745 u32 val;
746 switch (portno) {
747 case 0:
748 port += VND_SCONTROL_CH0;
749 break;
750 case 1:
751 port += VND_SCONTROL_CH1;
752 break;
753 case 2:
754 port += VND_SCONTROL_CH2;
755 break;
756 case 3:
757 port += VND_SCONTROL_CH3;
758 break;
759 default:
760 return 0;
761 }
762 val = readl (port);
763 writel (val | SATA_SC_DET_RST, port);
764 msleep (150);
765 writel (val & ~SATA_SC_DET_RST, port);
766 return 0;
767 }
768
scan_sata(int dev)769 int scan_sata (int dev)
770 {
771 /* A bit brain dead, but the code has a legacy */
772 switch (dev) {
773 case 0:
774 port[0].port_no = 0;
775 port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
776 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
777 (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
778 port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
779 break;
780 #if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
781 case 1:
782 port[1].port_no = 0;
783 port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
784 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
785 (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
786 port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
787 break;
788 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
789 case 2:
790 port[2].port_no = 0;
791 port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
792 port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
793 (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
794 port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
795 break;
796 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
797 case 3:
798 port[3].port_no = 0;
799 port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
800 port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
801 (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
802 port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
803 break;
804 #endif
805 default:
806 printf ("Tried to scan unknown port: ata%d\n", dev);
807 return 1;
808 }
809
810 /* Initialize other registers */
811 sata_port (&port[dev].ioaddr);
812
813 /* Check for attached device */
814 if (!sata_bus_probe (dev)) {
815 port[dev].port_state = 0;
816 debug ("SATA#%d port is not present\n", dev);
817 } else {
818 debug ("SATA#%d port is present\n", dev);
819 if (sata_bus_softreset (dev)) {
820 /* soft reset failed, try a hard one */
821 sata_phy_reset (dev);
822 if (sata_bus_softreset (dev)) {
823 port[dev].port_state = 0;
824 } else {
825 port[dev].port_state = 1;
826 }
827 } else {
828 port[dev].port_state = 1;
829 }
830 }
831 if (port[dev].port_state == 1) {
832 /* Probe device and set xfer mode */
833 sata_identify (dev, 0);
834 set_Feature_cmd (dev, 0);
835 }
836
837 return 0;
838 }
839