1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2020, Cortina Access Inc. 4 */ 5 6/dts-v1/; 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <1>; 11 12 mmc0: mmc@f4400000 { 13 compatible = "cortina,ca-mmc"; 14 reg = <0x0 0xf4400000 0x1000>; 15 bus-width = <4>; 16 sd_dll_ctrl = <0xf43200e8>; 17 io_drv_ctrl = <0xf432004c>; 18 }; 19 20 gpio0: gpio-controller@0xf4329280 { 21 compatible = "cortina,ca-gpio"; 22 reg = <0x0 0xf4329280 0x24>; 23 gpio-controller; 24 #gpio-cells = <2>; 25 status = "okay"; 26 }; 27 gpio1: gpio-controller@0xf43292a4 { 28 compatible = "cortina,ca-gpio"; 29 reg = <0x0 0xf43292a4 0x24>; 30 gpio-controller; 31 #gpio-cells = <2>; 32 status = "disabled"; 33 }; 34 35 watchdog: watchdog@0xf432901c { 36 compatible = "cortina,ca-wdt"; 37 reg = <0x0 0xf432901c 0x34>, 38 <0x0 0xf4320020 0x04>; 39 status = "okay"; 40 }; 41 42 uart0: serial@0xf4329148 { 43 u-boot,dm-pre-reloc; 44 compatible = "cortina,ca-uart"; 45 reg = <0x0 0xf4329148 0x30>; 46 status = "okay"; 47 }; 48 49 i2c: i2c@f4329120 { 50 compatible = "cortina,ca-i2c"; 51 reg = <0x0 0xf4329120 0x28>; 52 clock-frequency = <400000>; 53 }; 54 55 nand: nand-controller@f4324000 { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 compatible = "cortina,ca-nand"; 59 reg = <0 0xf4324000 0x3b0>, /* NAND controller */ 60 <0 0xf7001000 0xb4>, /* DMA_GLOBAL */ 61 <0 0xf7001a00 0x80>; /* DMA channel0 for FLASH */ 62 status = "okay"; 63 nand-ecc-mode = "hw"; 64 nand-ecc-strength = <16>; 65 nand-ecc-step-size = <1024>; /* Must be 1024 */ 66 nand_flash_base_addr = <0xe0000000>; 67 }; 68 69 sflash: sflash-controller@f4324000 { 70 #address-cells = <2>; 71 #size-cells = <1>; 72 compatible = "cortina,ca-sflash"; 73 reg = <0x0 0xf4324000 0x50>; 74 reg-names = "sflash-regs"; 75 flash@0 { 76 compatible = "jedec,spi-nor"; 77 spi-rx-bus-width = <1>; 78 spi-max-frequency = <108000000>; 79 }; 80 }; 81 82 leds: led-controller@f43200f0 { 83 compatible = "cortina,ca-leds"; 84 reg = <0x0 0xf43200f0 0x40>; 85 86 cortina,blink-rate1 = <256>; 87 cortina,blink-rate2 = <512>; 88 89 led@0 { 90 pin = <0>; 91 active-low; 92 blink-sel =<0>; 93 port = <0>; 94 off-event = <0>; 95 label = "led0"; 96 }; 97 98 led@1 { 99 pin = <1>; 100 active-low; 101 blink-sel =<1>; 102 label = "led1"; 103 }; 104 105 led@2 { 106 pin = <2>; 107 active-low; 108 label = "led2"; 109 }; 110 111 }; 112 113 eth: ethnet@0xf4300000 { 114 compatible = "eth_cortina"; 115 reg = <0x0 0xf4320000 0x34>, 116 <0x0 0xf43290d8 0x04>, 117 <0x0 0xf4304000 0x04>; 118 119 /* port0: phy address 1 - GMAC0: port 0 120 * port1: phy address 2 - GMAC1: port 1 121 * port2: phy address 3 - GMAC2: port 2 122 * port3: phy address 4 - GMAC3: port 3 123 * port4: phy address 5 - RGMII: port 4 124 */ 125 valid-port-map = <0x1f>; 126 valid-port-num = <5>; 127 valid-ports = <0x1 0x0>, 128 <0x2 0x1>, 129 <0x3 0x2>, 130 <0x4 0x3>, 131 <0x5 0x4>; 132 def-active-port = <0x3>; 133 inter-gphy-num = <6>; 134 inter-gphy-val = <0xf43380fc 0xbcd>, 135 <0xf43380dc 0xeeee>, 136 <0xf43380d8 0xeeee>, 137 <0xf43380fc 0xbce>, 138 <0xf43380c0 0x7777>, 139 <0xf43380c4 0x7777>; 140 init-rgmii = <1>; 141 ni-xram-base = <0xF4500000>; 142 }; 143}; 144