1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 simplefb_cvbs: framebuffer-cvbs { 26 compatible = "amlogic,simple-framebuffer", 27 "simple-framebuffer"; 28 amlogic,pipeline = "vpu-cvbs"; 29 clocks = <&clkc CLKID_HDMI>, 30 <&clkc CLKID_HTX_PCLK>, 31 <&clkc CLKID_VPU_INTR>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "amlogic,simple-framebuffer", 37 "simple-framebuffer"; 38 amlogic,pipeline = "vpu-hdmi"; 39 clocks = <&clkc CLKID_HDMI>, 40 <&clkc CLKID_HTX_PCLK>, 41 <&clkc CLKID_VPU_INTR>; 42 status = "disabled"; 43 }; 44 }; 45 46 efuse: efuse { 47 compatible = "amlogic,meson-gxbb-efuse"; 48 clocks = <&clkc CLKID_EFUSE>; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 read-only; 52 secure-monitor = <&sm>; 53 }; 54 55 gpu_opp_table: gpu-opp-table { 56 compatible = "operating-points-v2"; 57 58 opp-124999998 { 59 opp-hz = /bits/ 64 <124999998>; 60 opp-microvolt = <800000>; 61 }; 62 opp-249999996 { 63 opp-hz = /bits/ 64 <249999996>; 64 opp-microvolt = <800000>; 65 }; 66 opp-285714281 { 67 opp-hz = /bits/ 64 <285714281>; 68 opp-microvolt = <800000>; 69 }; 70 opp-399999994 { 71 opp-hz = /bits/ 64 <399999994>; 72 opp-microvolt = <800000>; 73 }; 74 opp-499999992 { 75 opp-hz = /bits/ 64 <499999992>; 76 opp-microvolt = <800000>; 77 }; 78 opp-666666656 { 79 opp-hz = /bits/ 64 <666666656>; 80 opp-microvolt = <800000>; 81 }; 82 opp-799999987 { 83 opp-hz = /bits/ 64 <799999987>; 84 opp-microvolt = <800000>; 85 }; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0"; 90 method = "smc"; 91 }; 92 93 reserved-memory { 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 99 secmon_reserved: secmon@5000000 { 100 reg = <0x0 0x05000000 0x0 0x300000>; 101 no-map; 102 }; 103 104 linux,cma { 105 compatible = "shared-dma-pool"; 106 reusable; 107 size = <0x0 0x10000000>; 108 alignment = <0x0 0x400000>; 109 linux,cma-default; 110 }; 111 }; 112 113 sm: secure-monitor { 114 compatible = "amlogic,meson-gxbb-sm"; 115 }; 116 117 soc { 118 compatible = "simple-bus"; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges; 122 123 pcie: pcie@fc000000 { 124 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 125 reg = <0x0 0xfc000000 0x0 0x400000 126 0x0 0xff648000 0x0 0x2000 127 0x0 0xfc400000 0x0 0x200000>; 128 reg-names = "elbi", "cfg", "config"; 129 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 130 #interrupt-cells = <1>; 131 interrupt-map-mask = <0 0 0 0>; 132 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 133 bus-range = <0x0 0xff>; 134 #address-cells = <3>; 135 #size-cells = <2>; 136 device_type = "pci"; 137 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 138 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 139 140 clocks = <&clkc CLKID_PCIE_PHY 141 &clkc CLKID_PCIE_COMB 142 &clkc CLKID_PCIE_PLL>; 143 clock-names = "general", 144 "pclk", 145 "port"; 146 resets = <&reset RESET_PCIE_CTRL_A>, 147 <&reset RESET_PCIE_APB>; 148 reset-names = "port", 149 "apb"; 150 num-lanes = <1>; 151 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 152 phy-names = "pcie"; 153 status = "disabled"; 154 }; 155 156 thermal-zones { 157 cpu_thermal: cpu-thermal { 158 polling-delay = <1000>; 159 polling-delay-passive = <100>; 160 thermal-sensors = <&cpu_temp>; 161 162 trips { 163 cpu_passive: cpu-passive { 164 temperature = <85000>; /* millicelsius */ 165 hysteresis = <2000>; /* millicelsius */ 166 type = "passive"; 167 }; 168 169 cpu_hot: cpu-hot { 170 temperature = <95000>; /* millicelsius */ 171 hysteresis = <2000>; /* millicelsius */ 172 type = "hot"; 173 }; 174 175 cpu_critical: cpu-critical { 176 temperature = <110000>; /* millicelsius */ 177 hysteresis = <2000>; /* millicelsius */ 178 type = "critical"; 179 }; 180 }; 181 }; 182 183 ddr_thermal: ddr-thermal { 184 polling-delay = <1000>; 185 polling-delay-passive = <100>; 186 thermal-sensors = <&ddr_temp>; 187 188 trips { 189 ddr_passive: ddr-passive { 190 temperature = <85000>; /* millicelsius */ 191 hysteresis = <2000>; /* millicelsius */ 192 type = "passive"; 193 }; 194 195 ddr_critical: ddr-critical { 196 temperature = <110000>; /* millicelsius */ 197 hysteresis = <2000>; /* millicelsius */ 198 type = "critical"; 199 }; 200 }; 201 202 cooling-maps { 203 map { 204 trip = <&ddr_passive>; 205 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 206 }; 207 }; 208 }; 209 }; 210 211 ethmac: ethernet@ff3f0000 { 212 compatible = "amlogic,meson-axg-dwmac", 213 "snps,dwmac-3.70a", 214 "snps,dwmac"; 215 reg = <0x0 0xff3f0000 0x0 0x10000>, 216 <0x0 0xff634540 0x0 0x8>; 217 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 218 interrupt-names = "macirq"; 219 clocks = <&clkc CLKID_ETH>, 220 <&clkc CLKID_FCLK_DIV2>, 221 <&clkc CLKID_MPLL2>, 222 <&clkc CLKID_FCLK_DIV2>; 223 clock-names = "stmmaceth", "clkin0", "clkin1", 224 "timing-adjustment"; 225 rx-fifo-depth = <4096>; 226 tx-fifo-depth = <2048>; 227 status = "disabled"; 228 229 mdio0: mdio { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "snps,dwmac-mdio"; 233 }; 234 }; 235 236 apb: bus@ff600000 { 237 compatible = "simple-bus"; 238 reg = <0x0 0xff600000 0x0 0x200000>; 239 #address-cells = <2>; 240 #size-cells = <2>; 241 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 242 243 hdmi_tx: hdmi-tx@0 { 244 compatible = "amlogic,meson-g12a-dw-hdmi"; 245 reg = <0x0 0x0 0x0 0x10000>; 246 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 247 resets = <&reset RESET_HDMITX_CAPB3>, 248 <&reset RESET_HDMITX_PHY>, 249 <&reset RESET_HDMITX>; 250 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 251 clocks = <&clkc CLKID_HDMI>, 252 <&clkc CLKID_HTX_PCLK>, 253 <&clkc CLKID_VPU_INTR>; 254 clock-names = "isfr", "iahb", "venci"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 260 /* VPU VENC Input */ 261 hdmi_tx_venc_port: port@0 { 262 reg = <0>; 263 264 hdmi_tx_in: endpoint { 265 remote-endpoint = <&hdmi_tx_out>; 266 }; 267 }; 268 269 /* TMDS Output */ 270 hdmi_tx_tmds_port: port@1 { 271 reg = <1>; 272 }; 273 }; 274 275 apb_efuse: bus@30000 { 276 compatible = "simple-bus"; 277 reg = <0x0 0x30000 0x0 0x2000>; 278 #address-cells = <2>; 279 #size-cells = <2>; 280 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 281 282 hwrng: rng@218 { 283 compatible = "amlogic,meson-rng"; 284 reg = <0x0 0x218 0x0 0x4>; 285 }; 286 }; 287 288 acodec: audio-controller@32000 { 289 compatible = "amlogic,t9015"; 290 reg = <0x0 0x32000 0x0 0x14>; 291 #sound-dai-cells = <0>; 292 sound-name-prefix = "ACODEC"; 293 clocks = <&clkc CLKID_AUDIO_CODEC>; 294 clock-names = "pclk"; 295 resets = <&reset RESET_AUDIO_CODEC>; 296 status = "disabled"; 297 }; 298 299 periphs: bus@34400 { 300 compatible = "simple-bus"; 301 reg = <0x0 0x34400 0x0 0x400>; 302 #address-cells = <2>; 303 #size-cells = <2>; 304 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 305 306 periphs_pinctrl: pinctrl@40 { 307 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 308 #address-cells = <2>; 309 #size-cells = <2>; 310 ranges; 311 312 gpio: bank@40 { 313 reg = <0x0 0x40 0x0 0x4c>, 314 <0x0 0xe8 0x0 0x18>, 315 <0x0 0x120 0x0 0x18>, 316 <0x0 0x2c0 0x0 0x40>, 317 <0x0 0x340 0x0 0x1c>; 318 reg-names = "gpio", 319 "pull", 320 "pull-enable", 321 "mux", 322 "ds"; 323 gpio-controller; 324 #gpio-cells = <2>; 325 gpio-ranges = <&periphs_pinctrl 0 0 86>; 326 }; 327 328 cec_ao_a_h_pins: cec_ao_a_h { 329 mux { 330 groups = "cec_ao_a_h"; 331 function = "cec_ao_a_h"; 332 bias-disable; 333 }; 334 }; 335 336 cec_ao_b_h_pins: cec_ao_b_h { 337 mux { 338 groups = "cec_ao_b_h"; 339 function = "cec_ao_b_h"; 340 bias-disable; 341 }; 342 }; 343 344 emmc_ctrl_pins: emmc-ctrl { 345 mux-0 { 346 groups = "emmc_cmd"; 347 function = "emmc"; 348 bias-pull-up; 349 drive-strength-microamp = <4000>; 350 }; 351 352 mux-1 { 353 groups = "emmc_clk"; 354 function = "emmc"; 355 bias-disable; 356 drive-strength-microamp = <4000>; 357 }; 358 }; 359 360 emmc_data_4b_pins: emmc-data-4b { 361 mux-0 { 362 groups = "emmc_nand_d0", 363 "emmc_nand_d1", 364 "emmc_nand_d2", 365 "emmc_nand_d3"; 366 function = "emmc"; 367 bias-pull-up; 368 drive-strength-microamp = <4000>; 369 }; 370 }; 371 372 emmc_data_8b_pins: emmc-data-8b { 373 mux-0 { 374 groups = "emmc_nand_d0", 375 "emmc_nand_d1", 376 "emmc_nand_d2", 377 "emmc_nand_d3", 378 "emmc_nand_d4", 379 "emmc_nand_d5", 380 "emmc_nand_d6", 381 "emmc_nand_d7"; 382 function = "emmc"; 383 bias-pull-up; 384 drive-strength-microamp = <4000>; 385 }; 386 }; 387 388 emmc_ds_pins: emmc-ds { 389 mux { 390 groups = "emmc_nand_ds"; 391 function = "emmc"; 392 bias-pull-down; 393 drive-strength-microamp = <4000>; 394 }; 395 }; 396 397 emmc_clk_gate_pins: emmc_clk_gate { 398 mux { 399 groups = "BOOT_8"; 400 function = "gpio_periphs"; 401 bias-pull-down; 402 drive-strength-microamp = <4000>; 403 }; 404 }; 405 406 hdmitx_ddc_pins: hdmitx_ddc { 407 mux { 408 groups = "hdmitx_sda", 409 "hdmitx_sck"; 410 function = "hdmitx"; 411 bias-disable; 412 drive-strength-microamp = <4000>; 413 }; 414 }; 415 416 hdmitx_hpd_pins: hdmitx_hpd { 417 mux { 418 groups = "hdmitx_hpd_in"; 419 function = "hdmitx"; 420 bias-disable; 421 }; 422 }; 423 424 425 i2c0_sda_c_pins: i2c0-sda-c { 426 mux { 427 groups = "i2c0_sda_c"; 428 function = "i2c0"; 429 bias-disable; 430 drive-strength-microamp = <3000>; 431 432 }; 433 }; 434 435 i2c0_sck_c_pins: i2c0-sck-c { 436 mux { 437 groups = "i2c0_sck_c"; 438 function = "i2c0"; 439 bias-disable; 440 drive-strength-microamp = <3000>; 441 }; 442 }; 443 444 i2c0_sda_z0_pins: i2c0-sda-z0 { 445 mux { 446 groups = "i2c0_sda_z0"; 447 function = "i2c0"; 448 bias-disable; 449 drive-strength-microamp = <3000>; 450 }; 451 }; 452 453 i2c0_sck_z1_pins: i2c0-sck-z1 { 454 mux { 455 groups = "i2c0_sck_z1"; 456 function = "i2c0"; 457 bias-disable; 458 drive-strength-microamp = <3000>; 459 }; 460 }; 461 462 i2c0_sda_z7_pins: i2c0-sda-z7 { 463 mux { 464 groups = "i2c0_sda_z7"; 465 function = "i2c0"; 466 bias-disable; 467 drive-strength-microamp = <3000>; 468 }; 469 }; 470 471 i2c0_sda_z8_pins: i2c0-sda-z8 { 472 mux { 473 groups = "i2c0_sda_z8"; 474 function = "i2c0"; 475 bias-disable; 476 drive-strength-microamp = <3000>; 477 }; 478 }; 479 480 i2c1_sda_x_pins: i2c1-sda-x { 481 mux { 482 groups = "i2c1_sda_x"; 483 function = "i2c1"; 484 bias-disable; 485 drive-strength-microamp = <3000>; 486 }; 487 }; 488 489 i2c1_sck_x_pins: i2c1-sck-x { 490 mux { 491 groups = "i2c1_sck_x"; 492 function = "i2c1"; 493 bias-disable; 494 drive-strength-microamp = <3000>; 495 }; 496 }; 497 498 i2c1_sda_h2_pins: i2c1-sda-h2 { 499 mux { 500 groups = "i2c1_sda_h2"; 501 function = "i2c1"; 502 bias-disable; 503 drive-strength-microamp = <3000>; 504 }; 505 }; 506 507 i2c1_sck_h3_pins: i2c1-sck-h3 { 508 mux { 509 groups = "i2c1_sck_h3"; 510 function = "i2c1"; 511 bias-disable; 512 drive-strength-microamp = <3000>; 513 }; 514 }; 515 516 i2c1_sda_h6_pins: i2c1-sda-h6 { 517 mux { 518 groups = "i2c1_sda_h6"; 519 function = "i2c1"; 520 bias-disable; 521 drive-strength-microamp = <3000>; 522 }; 523 }; 524 525 i2c1_sck_h7_pins: i2c1-sck-h7 { 526 mux { 527 groups = "i2c1_sck_h7"; 528 function = "i2c1"; 529 bias-disable; 530 drive-strength-microamp = <3000>; 531 }; 532 }; 533 534 i2c2_sda_x_pins: i2c2-sda-x { 535 mux { 536 groups = "i2c2_sda_x"; 537 function = "i2c2"; 538 bias-disable; 539 drive-strength-microamp = <3000>; 540 }; 541 }; 542 543 i2c2_sck_x_pins: i2c2-sck-x { 544 mux { 545 groups = "i2c2_sck_x"; 546 function = "i2c2"; 547 bias-disable; 548 drive-strength-microamp = <3000>; 549 }; 550 }; 551 552 i2c2_sda_z_pins: i2c2-sda-z { 553 mux { 554 groups = "i2c2_sda_z"; 555 function = "i2c2"; 556 bias-disable; 557 drive-strength-microamp = <3000>; 558 }; 559 }; 560 561 i2c2_sck_z_pins: i2c2-sck-z { 562 mux { 563 groups = "i2c2_sck_z"; 564 function = "i2c2"; 565 bias-disable; 566 drive-strength-microamp = <3000>; 567 }; 568 }; 569 570 i2c3_sda_h_pins: i2c3-sda-h { 571 mux { 572 groups = "i2c3_sda_h"; 573 function = "i2c3"; 574 bias-disable; 575 drive-strength-microamp = <3000>; 576 }; 577 }; 578 579 i2c3_sck_h_pins: i2c3-sck-h { 580 mux { 581 groups = "i2c3_sck_h"; 582 function = "i2c3"; 583 bias-disable; 584 drive-strength-microamp = <3000>; 585 }; 586 }; 587 588 i2c3_sda_a_pins: i2c3-sda-a { 589 mux { 590 groups = "i2c3_sda_a"; 591 function = "i2c3"; 592 bias-disable; 593 drive-strength-microamp = <3000>; 594 }; 595 }; 596 597 i2c3_sck_a_pins: i2c3-sck-a { 598 mux { 599 groups = "i2c3_sck_a"; 600 function = "i2c3"; 601 bias-disable; 602 drive-strength-microamp = <3000>; 603 }; 604 }; 605 606 mclk0_a_pins: mclk0-a { 607 mux { 608 groups = "mclk0_a"; 609 function = "mclk0"; 610 bias-disable; 611 drive-strength-microamp = <3000>; 612 }; 613 }; 614 615 mclk1_a_pins: mclk1-a { 616 mux { 617 groups = "mclk1_a"; 618 function = "mclk1"; 619 bias-disable; 620 drive-strength-microamp = <3000>; 621 }; 622 }; 623 624 mclk1_x_pins: mclk1-x { 625 mux { 626 groups = "mclk1_x"; 627 function = "mclk1"; 628 bias-disable; 629 drive-strength-microamp = <3000>; 630 }; 631 }; 632 633 mclk1_z_pins: mclk1-z { 634 mux { 635 groups = "mclk1_z"; 636 function = "mclk1"; 637 bias-disable; 638 drive-strength-microamp = <3000>; 639 }; 640 }; 641 642 nor_pins: nor { 643 mux { 644 groups = "nor_d", 645 "nor_q", 646 "nor_c", 647 "nor_cs"; 648 function = "nor"; 649 bias-disable; 650 }; 651 }; 652 653 pdm_din0_a_pins: pdm-din0-a { 654 mux { 655 groups = "pdm_din0_a"; 656 function = "pdm"; 657 bias-disable; 658 }; 659 }; 660 661 pdm_din0_c_pins: pdm-din0-c { 662 mux { 663 groups = "pdm_din0_c"; 664 function = "pdm"; 665 bias-disable; 666 }; 667 }; 668 669 pdm_din0_x_pins: pdm-din0-x { 670 mux { 671 groups = "pdm_din0_x"; 672 function = "pdm"; 673 bias-disable; 674 }; 675 }; 676 677 pdm_din0_z_pins: pdm-din0-z { 678 mux { 679 groups = "pdm_din0_z"; 680 function = "pdm"; 681 bias-disable; 682 }; 683 }; 684 685 pdm_din1_a_pins: pdm-din1-a { 686 mux { 687 groups = "pdm_din1_a"; 688 function = "pdm"; 689 bias-disable; 690 }; 691 }; 692 693 pdm_din1_c_pins: pdm-din1-c { 694 mux { 695 groups = "pdm_din1_c"; 696 function = "pdm"; 697 bias-disable; 698 }; 699 }; 700 701 pdm_din1_x_pins: pdm-din1-x { 702 mux { 703 groups = "pdm_din1_x"; 704 function = "pdm"; 705 bias-disable; 706 }; 707 }; 708 709 pdm_din1_z_pins: pdm-din1-z { 710 mux { 711 groups = "pdm_din1_z"; 712 function = "pdm"; 713 bias-disable; 714 }; 715 }; 716 717 pdm_din2_a_pins: pdm-din2-a { 718 mux { 719 groups = "pdm_din2_a"; 720 function = "pdm"; 721 bias-disable; 722 }; 723 }; 724 725 pdm_din2_c_pins: pdm-din2-c { 726 mux { 727 groups = "pdm_din2_c"; 728 function = "pdm"; 729 bias-disable; 730 }; 731 }; 732 733 pdm_din2_x_pins: pdm-din2-x { 734 mux { 735 groups = "pdm_din2_x"; 736 function = "pdm"; 737 bias-disable; 738 }; 739 }; 740 741 pdm_din2_z_pins: pdm-din2-z { 742 mux { 743 groups = "pdm_din2_z"; 744 function = "pdm"; 745 bias-disable; 746 }; 747 }; 748 749 pdm_din3_a_pins: pdm-din3-a { 750 mux { 751 groups = "pdm_din3_a"; 752 function = "pdm"; 753 bias-disable; 754 }; 755 }; 756 757 pdm_din3_c_pins: pdm-din3-c { 758 mux { 759 groups = "pdm_din3_c"; 760 function = "pdm"; 761 bias-disable; 762 }; 763 }; 764 765 pdm_din3_x_pins: pdm-din3-x { 766 mux { 767 groups = "pdm_din3_x"; 768 function = "pdm"; 769 bias-disable; 770 }; 771 }; 772 773 pdm_din3_z_pins: pdm-din3-z { 774 mux { 775 groups = "pdm_din3_z"; 776 function = "pdm"; 777 bias-disable; 778 }; 779 }; 780 781 pdm_dclk_a_pins: pdm-dclk-a { 782 mux { 783 groups = "pdm_dclk_a"; 784 function = "pdm"; 785 bias-disable; 786 drive-strength-microamp = <500>; 787 }; 788 }; 789 790 pdm_dclk_c_pins: pdm-dclk-c { 791 mux { 792 groups = "pdm_dclk_c"; 793 function = "pdm"; 794 bias-disable; 795 drive-strength-microamp = <500>; 796 }; 797 }; 798 799 pdm_dclk_x_pins: pdm-dclk-x { 800 mux { 801 groups = "pdm_dclk_x"; 802 function = "pdm"; 803 bias-disable; 804 drive-strength-microamp = <500>; 805 }; 806 }; 807 808 pdm_dclk_z_pins: pdm-dclk-z { 809 mux { 810 groups = "pdm_dclk_z"; 811 function = "pdm"; 812 bias-disable; 813 drive-strength-microamp = <500>; 814 }; 815 }; 816 817 pwm_a_pins: pwm-a { 818 mux { 819 groups = "pwm_a"; 820 function = "pwm_a"; 821 bias-disable; 822 }; 823 }; 824 825 pwm_b_x7_pins: pwm-b-x7 { 826 mux { 827 groups = "pwm_b_x7"; 828 function = "pwm_b"; 829 bias-disable; 830 }; 831 }; 832 833 pwm_b_x19_pins: pwm-b-x19 { 834 mux { 835 groups = "pwm_b_x19"; 836 function = "pwm_b"; 837 bias-disable; 838 }; 839 }; 840 841 pwm_c_c_pins: pwm-c-c { 842 mux { 843 groups = "pwm_c_c"; 844 function = "pwm_c"; 845 bias-disable; 846 }; 847 }; 848 849 pwm_c_x5_pins: pwm-c-x5 { 850 mux { 851 groups = "pwm_c_x5"; 852 function = "pwm_c"; 853 bias-disable; 854 }; 855 }; 856 857 pwm_c_x8_pins: pwm-c-x8 { 858 mux { 859 groups = "pwm_c_x8"; 860 function = "pwm_c"; 861 bias-disable; 862 }; 863 }; 864 865 pwm_d_x3_pins: pwm-d-x3 { 866 mux { 867 groups = "pwm_d_x3"; 868 function = "pwm_d"; 869 bias-disable; 870 }; 871 }; 872 873 pwm_d_x6_pins: pwm-d-x6 { 874 mux { 875 groups = "pwm_d_x6"; 876 function = "pwm_d"; 877 bias-disable; 878 }; 879 }; 880 881 pwm_e_pins: pwm-e { 882 mux { 883 groups = "pwm_e"; 884 function = "pwm_e"; 885 bias-disable; 886 }; 887 }; 888 889 pwm_f_x_pins: pwm-f-x { 890 mux { 891 groups = "pwm_f_x"; 892 function = "pwm_f"; 893 bias-disable; 894 }; 895 }; 896 897 pwm_f_h_pins: pwm-f-h { 898 mux { 899 groups = "pwm_f_h"; 900 function = "pwm_f"; 901 bias-disable; 902 }; 903 }; 904 905 sdcard_c_pins: sdcard_c { 906 mux-0 { 907 groups = "sdcard_d0_c", 908 "sdcard_d1_c", 909 "sdcard_d2_c", 910 "sdcard_d3_c", 911 "sdcard_cmd_c"; 912 function = "sdcard"; 913 bias-pull-up; 914 drive-strength-microamp = <4000>; 915 }; 916 917 mux-1 { 918 groups = "sdcard_clk_c"; 919 function = "sdcard"; 920 bias-disable; 921 drive-strength-microamp = <4000>; 922 }; 923 }; 924 925 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 926 mux { 927 groups = "GPIOC_4"; 928 function = "gpio_periphs"; 929 bias-pull-down; 930 drive-strength-microamp = <4000>; 931 }; 932 }; 933 934 sdcard_z_pins: sdcard_z { 935 mux-0 { 936 groups = "sdcard_d0_z", 937 "sdcard_d1_z", 938 "sdcard_d2_z", 939 "sdcard_d3_z", 940 "sdcard_cmd_z"; 941 function = "sdcard"; 942 bias-pull-up; 943 drive-strength-microamp = <4000>; 944 }; 945 946 mux-1 { 947 groups = "sdcard_clk_z"; 948 function = "sdcard"; 949 bias-disable; 950 drive-strength-microamp = <4000>; 951 }; 952 }; 953 954 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 955 mux { 956 groups = "GPIOZ_6"; 957 function = "gpio_periphs"; 958 bias-pull-down; 959 drive-strength-microamp = <4000>; 960 }; 961 }; 962 963 sdio_pins: sdio { 964 mux { 965 groups = "sdio_d0", 966 "sdio_d1", 967 "sdio_d2", 968 "sdio_d3", 969 "sdio_clk", 970 "sdio_cmd"; 971 function = "sdio"; 972 bias-disable; 973 drive-strength-microamp = <4000>; 974 }; 975 }; 976 977 sdio_clk_gate_pins: sdio_clk_gate { 978 mux { 979 groups = "GPIOX_4"; 980 function = "gpio_periphs"; 981 bias-pull-down; 982 drive-strength-microamp = <4000>; 983 }; 984 }; 985 986 spdif_in_a10_pins: spdif-in-a10 { 987 mux { 988 groups = "spdif_in_a10"; 989 function = "spdif_in"; 990 bias-disable; 991 }; 992 }; 993 994 spdif_in_a12_pins: spdif-in-a12 { 995 mux { 996 groups = "spdif_in_a12"; 997 function = "spdif_in"; 998 bias-disable; 999 }; 1000 }; 1001 1002 spdif_in_h_pins: spdif-in-h { 1003 mux { 1004 groups = "spdif_in_h"; 1005 function = "spdif_in"; 1006 bias-disable; 1007 }; 1008 }; 1009 1010 spdif_out_h_pins: spdif-out-h { 1011 mux { 1012 groups = "spdif_out_h"; 1013 function = "spdif_out"; 1014 drive-strength-microamp = <500>; 1015 bias-disable; 1016 }; 1017 }; 1018 1019 spdif_out_a11_pins: spdif-out-a11 { 1020 mux { 1021 groups = "spdif_out_a11"; 1022 function = "spdif_out"; 1023 drive-strength-microamp = <500>; 1024 bias-disable; 1025 }; 1026 }; 1027 1028 spdif_out_a13_pins: spdif-out-a13 { 1029 mux { 1030 groups = "spdif_out_a13"; 1031 function = "spdif_out"; 1032 drive-strength-microamp = <500>; 1033 bias-disable; 1034 }; 1035 }; 1036 1037 spicc0_x_pins: spicc0-x { 1038 mux { 1039 groups = "spi0_mosi_x", 1040 "spi0_miso_x", 1041 "spi0_clk_x"; 1042 function = "spi0"; 1043 drive-strength-microamp = <4000>; 1044 bias-disable; 1045 }; 1046 }; 1047 1048 spicc0_ss0_x_pins: spicc0-ss0-x { 1049 mux { 1050 groups = "spi0_ss0_x"; 1051 function = "spi0"; 1052 drive-strength-microamp = <4000>; 1053 bias-disable; 1054 }; 1055 }; 1056 1057 spicc0_c_pins: spicc0-c { 1058 mux { 1059 groups = "spi0_mosi_c", 1060 "spi0_miso_c", 1061 "spi0_ss0_c", 1062 "spi0_clk_c"; 1063 function = "spi0"; 1064 drive-strength-microamp = <4000>; 1065 bias-disable; 1066 }; 1067 }; 1068 1069 spicc1_pins: spicc1 { 1070 mux { 1071 groups = "spi1_mosi", 1072 "spi1_miso", 1073 "spi1_clk"; 1074 function = "spi1"; 1075 drive-strength-microamp = <4000>; 1076 }; 1077 }; 1078 1079 spicc1_ss0_pins: spicc1-ss0 { 1080 mux { 1081 groups = "spi1_ss0"; 1082 function = "spi1"; 1083 drive-strength-microamp = <4000>; 1084 bias-disable; 1085 }; 1086 }; 1087 1088 tdm_a_din0_pins: tdm-a-din0 { 1089 mux { 1090 groups = "tdm_a_din0"; 1091 function = "tdm_a"; 1092 bias-disable; 1093 }; 1094 }; 1095 1096 1097 tdm_a_din1_pins: tdm-a-din1 { 1098 mux { 1099 groups = "tdm_a_din1"; 1100 function = "tdm_a"; 1101 bias-disable; 1102 }; 1103 }; 1104 1105 tdm_a_dout0_pins: tdm-a-dout0 { 1106 mux { 1107 groups = "tdm_a_dout0"; 1108 function = "tdm_a"; 1109 bias-disable; 1110 drive-strength-microamp = <3000>; 1111 }; 1112 }; 1113 1114 tdm_a_dout1_pins: tdm-a-dout1 { 1115 mux { 1116 groups = "tdm_a_dout1"; 1117 function = "tdm_a"; 1118 bias-disable; 1119 drive-strength-microamp = <3000>; 1120 }; 1121 }; 1122 1123 tdm_a_fs_pins: tdm-a-fs { 1124 mux { 1125 groups = "tdm_a_fs"; 1126 function = "tdm_a"; 1127 bias-disable; 1128 drive-strength-microamp = <3000>; 1129 }; 1130 }; 1131 1132 tdm_a_sclk_pins: tdm-a-sclk { 1133 mux { 1134 groups = "tdm_a_sclk"; 1135 function = "tdm_a"; 1136 bias-disable; 1137 drive-strength-microamp = <3000>; 1138 }; 1139 }; 1140 1141 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1142 mux { 1143 groups = "tdm_a_slv_fs"; 1144 function = "tdm_a"; 1145 bias-disable; 1146 }; 1147 }; 1148 1149 1150 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1151 mux { 1152 groups = "tdm_a_slv_sclk"; 1153 function = "tdm_a"; 1154 bias-disable; 1155 }; 1156 }; 1157 1158 tdm_b_din0_pins: tdm-b-din0 { 1159 mux { 1160 groups = "tdm_b_din0"; 1161 function = "tdm_b"; 1162 bias-disable; 1163 }; 1164 }; 1165 1166 tdm_b_din1_pins: tdm-b-din1 { 1167 mux { 1168 groups = "tdm_b_din1"; 1169 function = "tdm_b"; 1170 bias-disable; 1171 }; 1172 }; 1173 1174 tdm_b_din2_pins: tdm-b-din2 { 1175 mux { 1176 groups = "tdm_b_din2"; 1177 function = "tdm_b"; 1178 bias-disable; 1179 }; 1180 }; 1181 1182 tdm_b_din3_a_pins: tdm-b-din3-a { 1183 mux { 1184 groups = "tdm_b_din3_a"; 1185 function = "tdm_b"; 1186 bias-disable; 1187 }; 1188 }; 1189 1190 tdm_b_din3_h_pins: tdm-b-din3-h { 1191 mux { 1192 groups = "tdm_b_din3_h"; 1193 function = "tdm_b"; 1194 bias-disable; 1195 }; 1196 }; 1197 1198 tdm_b_dout0_pins: tdm-b-dout0 { 1199 mux { 1200 groups = "tdm_b_dout0"; 1201 function = "tdm_b"; 1202 bias-disable; 1203 drive-strength-microamp = <3000>; 1204 }; 1205 }; 1206 1207 tdm_b_dout1_pins: tdm-b-dout1 { 1208 mux { 1209 groups = "tdm_b_dout1"; 1210 function = "tdm_b"; 1211 bias-disable; 1212 drive-strength-microamp = <3000>; 1213 }; 1214 }; 1215 1216 tdm_b_dout2_pins: tdm-b-dout2 { 1217 mux { 1218 groups = "tdm_b_dout2"; 1219 function = "tdm_b"; 1220 bias-disable; 1221 drive-strength-microamp = <3000>; 1222 }; 1223 }; 1224 1225 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1226 mux { 1227 groups = "tdm_b_dout3_a"; 1228 function = "tdm_b"; 1229 bias-disable; 1230 drive-strength-microamp = <3000>; 1231 }; 1232 }; 1233 1234 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1235 mux { 1236 groups = "tdm_b_dout3_h"; 1237 function = "tdm_b"; 1238 bias-disable; 1239 drive-strength-microamp = <3000>; 1240 }; 1241 }; 1242 1243 tdm_b_fs_pins: tdm-b-fs { 1244 mux { 1245 groups = "tdm_b_fs"; 1246 function = "tdm_b"; 1247 bias-disable; 1248 drive-strength-microamp = <3000>; 1249 }; 1250 }; 1251 1252 tdm_b_sclk_pins: tdm-b-sclk { 1253 mux { 1254 groups = "tdm_b_sclk"; 1255 function = "tdm_b"; 1256 bias-disable; 1257 drive-strength-microamp = <3000>; 1258 }; 1259 }; 1260 1261 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1262 mux { 1263 groups = "tdm_b_slv_fs"; 1264 function = "tdm_b"; 1265 bias-disable; 1266 }; 1267 }; 1268 1269 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1270 mux { 1271 groups = "tdm_b_slv_sclk"; 1272 function = "tdm_b"; 1273 bias-disable; 1274 }; 1275 }; 1276 1277 tdm_c_din0_a_pins: tdm-c-din0-a { 1278 mux { 1279 groups = "tdm_c_din0_a"; 1280 function = "tdm_c"; 1281 bias-disable; 1282 }; 1283 }; 1284 1285 tdm_c_din0_z_pins: tdm-c-din0-z { 1286 mux { 1287 groups = "tdm_c_din0_z"; 1288 function = "tdm_c"; 1289 bias-disable; 1290 }; 1291 }; 1292 1293 tdm_c_din1_a_pins: tdm-c-din1-a { 1294 mux { 1295 groups = "tdm_c_din1_a"; 1296 function = "tdm_c"; 1297 bias-disable; 1298 }; 1299 }; 1300 1301 tdm_c_din1_z_pins: tdm-c-din1-z { 1302 mux { 1303 groups = "tdm_c_din1_z"; 1304 function = "tdm_c"; 1305 bias-disable; 1306 }; 1307 }; 1308 1309 tdm_c_din2_a_pins: tdm-c-din2-a { 1310 mux { 1311 groups = "tdm_c_din2_a"; 1312 function = "tdm_c"; 1313 bias-disable; 1314 }; 1315 }; 1316 1317 eth_leds_pins: eth-leds { 1318 mux { 1319 groups = "eth_link_led", 1320 "eth_act_led"; 1321 function = "eth"; 1322 bias-disable; 1323 }; 1324 }; 1325 1326 eth_pins: eth { 1327 mux { 1328 groups = "eth_mdio", 1329 "eth_mdc", 1330 "eth_rgmii_rx_clk", 1331 "eth_rx_dv", 1332 "eth_rxd0", 1333 "eth_rxd1", 1334 "eth_txen", 1335 "eth_txd0", 1336 "eth_txd1"; 1337 function = "eth"; 1338 drive-strength-microamp = <4000>; 1339 bias-disable; 1340 }; 1341 }; 1342 1343 eth_rgmii_pins: eth-rgmii { 1344 mux { 1345 groups = "eth_rxd2_rgmii", 1346 "eth_rxd3_rgmii", 1347 "eth_rgmii_tx_clk", 1348 "eth_txd2_rgmii", 1349 "eth_txd3_rgmii"; 1350 function = "eth"; 1351 drive-strength-microamp = <4000>; 1352 bias-disable; 1353 }; 1354 }; 1355 1356 tdm_c_din2_z_pins: tdm-c-din2-z { 1357 mux { 1358 groups = "tdm_c_din2_z"; 1359 function = "tdm_c"; 1360 bias-disable; 1361 }; 1362 }; 1363 1364 tdm_c_din3_a_pins: tdm-c-din3-a { 1365 mux { 1366 groups = "tdm_c_din3_a"; 1367 function = "tdm_c"; 1368 bias-disable; 1369 }; 1370 }; 1371 1372 tdm_c_din3_z_pins: tdm-c-din3-z { 1373 mux { 1374 groups = "tdm_c_din3_z"; 1375 function = "tdm_c"; 1376 bias-disable; 1377 }; 1378 }; 1379 1380 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1381 mux { 1382 groups = "tdm_c_dout0_a"; 1383 function = "tdm_c"; 1384 bias-disable; 1385 drive-strength-microamp = <3000>; 1386 }; 1387 }; 1388 1389 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1390 mux { 1391 groups = "tdm_c_dout0_z"; 1392 function = "tdm_c"; 1393 bias-disable; 1394 drive-strength-microamp = <3000>; 1395 }; 1396 }; 1397 1398 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1399 mux { 1400 groups = "tdm_c_dout1_a"; 1401 function = "tdm_c"; 1402 bias-disable; 1403 drive-strength-microamp = <3000>; 1404 }; 1405 }; 1406 1407 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1408 mux { 1409 groups = "tdm_c_dout1_z"; 1410 function = "tdm_c"; 1411 bias-disable; 1412 drive-strength-microamp = <3000>; 1413 }; 1414 }; 1415 1416 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1417 mux { 1418 groups = "tdm_c_dout2_a"; 1419 function = "tdm_c"; 1420 bias-disable; 1421 drive-strength-microamp = <3000>; 1422 }; 1423 }; 1424 1425 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1426 mux { 1427 groups = "tdm_c_dout2_z"; 1428 function = "tdm_c"; 1429 bias-disable; 1430 drive-strength-microamp = <3000>; 1431 }; 1432 }; 1433 1434 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1435 mux { 1436 groups = "tdm_c_dout3_a"; 1437 function = "tdm_c"; 1438 bias-disable; 1439 drive-strength-microamp = <3000>; 1440 }; 1441 }; 1442 1443 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1444 mux { 1445 groups = "tdm_c_dout3_z"; 1446 function = "tdm_c"; 1447 bias-disable; 1448 drive-strength-microamp = <3000>; 1449 }; 1450 }; 1451 1452 tdm_c_fs_a_pins: tdm-c-fs-a { 1453 mux { 1454 groups = "tdm_c_fs_a"; 1455 function = "tdm_c"; 1456 bias-disable; 1457 drive-strength-microamp = <3000>; 1458 }; 1459 }; 1460 1461 tdm_c_fs_z_pins: tdm-c-fs-z { 1462 mux { 1463 groups = "tdm_c_fs_z"; 1464 function = "tdm_c"; 1465 bias-disable; 1466 drive-strength-microamp = <3000>; 1467 }; 1468 }; 1469 1470 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1471 mux { 1472 groups = "tdm_c_sclk_a"; 1473 function = "tdm_c"; 1474 bias-disable; 1475 drive-strength-microamp = <3000>; 1476 }; 1477 }; 1478 1479 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1480 mux { 1481 groups = "tdm_c_sclk_z"; 1482 function = "tdm_c"; 1483 bias-disable; 1484 drive-strength-microamp = <3000>; 1485 }; 1486 }; 1487 1488 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1489 mux { 1490 groups = "tdm_c_slv_fs_a"; 1491 function = "tdm_c"; 1492 bias-disable; 1493 }; 1494 }; 1495 1496 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1497 mux { 1498 groups = "tdm_c_slv_fs_z"; 1499 function = "tdm_c"; 1500 bias-disable; 1501 }; 1502 }; 1503 1504 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1505 mux { 1506 groups = "tdm_c_slv_sclk_a"; 1507 function = "tdm_c"; 1508 bias-disable; 1509 }; 1510 }; 1511 1512 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1513 mux { 1514 groups = "tdm_c_slv_sclk_z"; 1515 function = "tdm_c"; 1516 bias-disable; 1517 }; 1518 }; 1519 1520 uart_a_pins: uart-a { 1521 mux { 1522 groups = "uart_a_tx", 1523 "uart_a_rx"; 1524 function = "uart_a"; 1525 bias-disable; 1526 }; 1527 }; 1528 1529 uart_a_cts_rts_pins: uart-a-cts-rts { 1530 mux { 1531 groups = "uart_a_cts", 1532 "uart_a_rts"; 1533 function = "uart_a"; 1534 bias-disable; 1535 }; 1536 }; 1537 1538 uart_b_pins: uart-b { 1539 mux { 1540 groups = "uart_b_tx", 1541 "uart_b_rx"; 1542 function = "uart_b"; 1543 bias-disable; 1544 }; 1545 }; 1546 1547 uart_c_pins: uart-c { 1548 mux { 1549 groups = "uart_c_tx", 1550 "uart_c_rx"; 1551 function = "uart_c"; 1552 bias-disable; 1553 }; 1554 }; 1555 1556 uart_c_cts_rts_pins: uart-c-cts-rts { 1557 mux { 1558 groups = "uart_c_cts", 1559 "uart_c_rts"; 1560 function = "uart_c"; 1561 bias-disable; 1562 }; 1563 }; 1564 }; 1565 }; 1566 1567 cpu_temp: temperature-sensor@34800 { 1568 compatible = "amlogic,g12a-cpu-thermal", 1569 "amlogic,g12a-thermal"; 1570 reg = <0x0 0x34800 0x0 0x50>; 1571 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1572 clocks = <&clkc CLKID_TS>; 1573 #thermal-sensor-cells = <0>; 1574 amlogic,ao-secure = <&sec_AO>; 1575 }; 1576 1577 ddr_temp: temperature-sensor@34c00 { 1578 compatible = "amlogic,g12a-ddr-thermal", 1579 "amlogic,g12a-thermal"; 1580 reg = <0x0 0x34c00 0x0 0x50>; 1581 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1582 clocks = <&clkc CLKID_TS>; 1583 #thermal-sensor-cells = <0>; 1584 amlogic,ao-secure = <&sec_AO>; 1585 }; 1586 1587 usb2_phy0: phy@36000 { 1588 compatible = "amlogic,g12a-usb2-phy"; 1589 reg = <0x0 0x36000 0x0 0x2000>; 1590 clocks = <&xtal>; 1591 clock-names = "xtal"; 1592 resets = <&reset RESET_USB_PHY20>; 1593 reset-names = "phy"; 1594 #phy-cells = <0>; 1595 }; 1596 1597 dmc: bus@38000 { 1598 compatible = "simple-bus"; 1599 reg = <0x0 0x38000 0x0 0x400>; 1600 #address-cells = <2>; 1601 #size-cells = <2>; 1602 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1603 1604 canvas: video-lut@48 { 1605 compatible = "amlogic,canvas"; 1606 reg = <0x0 0x48 0x0 0x14>; 1607 }; 1608 }; 1609 1610 usb2_phy1: phy@3a000 { 1611 compatible = "amlogic,g12a-usb2-phy"; 1612 reg = <0x0 0x3a000 0x0 0x2000>; 1613 clocks = <&xtal>; 1614 clock-names = "xtal"; 1615 resets = <&reset RESET_USB_PHY21>; 1616 reset-names = "phy"; 1617 #phy-cells = <0>; 1618 }; 1619 1620 hiu: bus@3c000 { 1621 compatible = "simple-bus"; 1622 reg = <0x0 0x3c000 0x0 0x1400>; 1623 #address-cells = <2>; 1624 #size-cells = <2>; 1625 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1626 1627 hhi: system-controller@0 { 1628 compatible = "amlogic,meson-gx-hhi-sysctrl", 1629 "simple-mfd", "syscon"; 1630 reg = <0 0 0 0x400>; 1631 1632 clkc: clock-controller { 1633 compatible = "amlogic,g12a-clkc"; 1634 #clock-cells = <1>; 1635 clocks = <&xtal>; 1636 clock-names = "xtal"; 1637 }; 1638 1639 pwrc: power-controller { 1640 compatible = "amlogic,meson-g12a-pwrc"; 1641 #power-domain-cells = <1>; 1642 amlogic,ao-sysctrl = <&rti>; 1643 resets = <&reset RESET_VIU>, 1644 <&reset RESET_VENC>, 1645 <&reset RESET_VCBUS>, 1646 <&reset RESET_BT656>, 1647 <&reset RESET_RDMA>, 1648 <&reset RESET_VENCI>, 1649 <&reset RESET_VENCP>, 1650 <&reset RESET_VDAC>, 1651 <&reset RESET_VDI6>, 1652 <&reset RESET_VENCL>, 1653 <&reset RESET_VID_LOCK>; 1654 reset-names = "viu", "venc", "vcbus", "bt656", 1655 "rdma", "venci", "vencp", "vdac", 1656 "vdi6", "vencl", "vid_lock"; 1657 clocks = <&clkc CLKID_VPU>, 1658 <&clkc CLKID_VAPB>; 1659 clock-names = "vpu", "vapb"; 1660 /* 1661 * VPU clocking is provided by two identical clock paths 1662 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1663 * free mux to safely change frequency while running. 1664 * Same for VAPB but with a final gate after the glitch free mux. 1665 */ 1666 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1667 <&clkc CLKID_VPU_0>, 1668 <&clkc CLKID_VPU>, /* Glitch free mux */ 1669 <&clkc CLKID_VAPB_0_SEL>, 1670 <&clkc CLKID_VAPB_0>, 1671 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1672 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1673 <0>, /* Do Nothing */ 1674 <&clkc CLKID_VPU_0>, 1675 <&clkc CLKID_FCLK_DIV4>, 1676 <0>, /* Do Nothing */ 1677 <&clkc CLKID_VAPB_0>; 1678 assigned-clock-rates = <0>, /* Do Nothing */ 1679 <666666666>, 1680 <0>, /* Do Nothing */ 1681 <0>, /* Do Nothing */ 1682 <250000000>, 1683 <0>; /* Do Nothing */ 1684 }; 1685 }; 1686 }; 1687 1688 usb3_pcie_phy: phy@46000 { 1689 compatible = "amlogic,g12a-usb3-pcie-phy"; 1690 reg = <0x0 0x46000 0x0 0x2000>; 1691 clocks = <&clkc CLKID_PCIE_PLL>; 1692 clock-names = "ref_clk"; 1693 resets = <&reset RESET_PCIE_PHY>; 1694 reset-names = "phy"; 1695 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1696 assigned-clock-rates = <100000000>; 1697 #phy-cells = <1>; 1698 }; 1699 1700 eth_phy: mdio-multiplexer@4c000 { 1701 compatible = "amlogic,g12a-mdio-mux"; 1702 reg = <0x0 0x4c000 0x0 0xa4>; 1703 clocks = <&clkc CLKID_ETH_PHY>, 1704 <&xtal>, 1705 <&clkc CLKID_MPLL_50M>; 1706 clock-names = "pclk", "clkin0", "clkin1"; 1707 mdio-parent-bus = <&mdio0>; 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 1711 ext_mdio: mdio@0 { 1712 reg = <0>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 }; 1716 1717 int_mdio: mdio@1 { 1718 reg = <1>; 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 1722 internal_ephy: ethernet_phy@8 { 1723 compatible = "ethernet-phy-id0180.3301", 1724 "ethernet-phy-ieee802.3-c22"; 1725 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1726 reg = <8>; 1727 max-speed = <100>; 1728 }; 1729 }; 1730 }; 1731 }; 1732 1733 aobus: bus@ff800000 { 1734 compatible = "simple-bus"; 1735 reg = <0x0 0xff800000 0x0 0x100000>; 1736 #address-cells = <2>; 1737 #size-cells = <2>; 1738 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1739 1740 rti: sys-ctrl@0 { 1741 compatible = "amlogic,meson-gx-ao-sysctrl", 1742 "simple-mfd", "syscon"; 1743 reg = <0x0 0x0 0x0 0x100>; 1744 #address-cells = <2>; 1745 #size-cells = <2>; 1746 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1747 1748 clkc_AO: clock-controller { 1749 compatible = "amlogic,meson-g12a-aoclkc"; 1750 #clock-cells = <1>; 1751 #reset-cells = <1>; 1752 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1753 clock-names = "xtal", "mpeg-clk"; 1754 }; 1755 1756 ao_pinctrl: pinctrl@14 { 1757 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1758 #address-cells = <2>; 1759 #size-cells = <2>; 1760 ranges; 1761 1762 gpio_ao: bank@14 { 1763 reg = <0x0 0x14 0x0 0x8>, 1764 <0x0 0x1c 0x0 0x8>, 1765 <0x0 0x24 0x0 0x14>; 1766 reg-names = "mux", 1767 "ds", 1768 "gpio"; 1769 gpio-controller; 1770 #gpio-cells = <2>; 1771 gpio-ranges = <&ao_pinctrl 0 0 15>; 1772 }; 1773 1774 i2c_ao_sck_pins: i2c_ao_sck_pins { 1775 mux { 1776 groups = "i2c_ao_sck"; 1777 function = "i2c_ao"; 1778 bias-disable; 1779 drive-strength-microamp = <3000>; 1780 }; 1781 }; 1782 1783 i2c_ao_sda_pins: i2c_ao_sda { 1784 mux { 1785 groups = "i2c_ao_sda"; 1786 function = "i2c_ao"; 1787 bias-disable; 1788 drive-strength-microamp = <3000>; 1789 }; 1790 }; 1791 1792 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1793 mux { 1794 groups = "i2c_ao_sck_e"; 1795 function = "i2c_ao"; 1796 bias-disable; 1797 drive-strength-microamp = <3000>; 1798 }; 1799 }; 1800 1801 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1802 mux { 1803 groups = "i2c_ao_sda_e"; 1804 function = "i2c_ao"; 1805 bias-disable; 1806 drive-strength-microamp = <3000>; 1807 }; 1808 }; 1809 1810 mclk0_ao_pins: mclk0-ao { 1811 mux { 1812 groups = "mclk0_ao"; 1813 function = "mclk0_ao"; 1814 bias-disable; 1815 drive-strength-microamp = <3000>; 1816 }; 1817 }; 1818 1819 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1820 mux { 1821 groups = "tdm_ao_b_din0"; 1822 function = "tdm_ao_b"; 1823 bias-disable; 1824 }; 1825 }; 1826 1827 spdif_ao_out_pins: spdif-ao-out { 1828 mux { 1829 groups = "spdif_ao_out"; 1830 function = "spdif_ao_out"; 1831 drive-strength-microamp = <500>; 1832 bias-disable; 1833 }; 1834 }; 1835 1836 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1837 mux { 1838 groups = "tdm_ao_b_din1"; 1839 function = "tdm_ao_b"; 1840 bias-disable; 1841 }; 1842 }; 1843 1844 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1845 mux { 1846 groups = "tdm_ao_b_din2"; 1847 function = "tdm_ao_b"; 1848 bias-disable; 1849 }; 1850 }; 1851 1852 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1853 mux { 1854 groups = "tdm_ao_b_dout0"; 1855 function = "tdm_ao_b"; 1856 bias-disable; 1857 drive-strength-microamp = <3000>; 1858 }; 1859 }; 1860 1861 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1862 mux { 1863 groups = "tdm_ao_b_dout1"; 1864 function = "tdm_ao_b"; 1865 bias-disable; 1866 drive-strength-microamp = <3000>; 1867 }; 1868 }; 1869 1870 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1871 mux { 1872 groups = "tdm_ao_b_dout2"; 1873 function = "tdm_ao_b"; 1874 bias-disable; 1875 drive-strength-microamp = <3000>; 1876 }; 1877 }; 1878 1879 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1880 mux { 1881 groups = "tdm_ao_b_fs"; 1882 function = "tdm_ao_b"; 1883 bias-disable; 1884 drive-strength-microamp = <3000>; 1885 }; 1886 }; 1887 1888 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1889 mux { 1890 groups = "tdm_ao_b_sclk"; 1891 function = "tdm_ao_b"; 1892 bias-disable; 1893 drive-strength-microamp = <3000>; 1894 }; 1895 }; 1896 1897 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1898 mux { 1899 groups = "tdm_ao_b_slv_fs"; 1900 function = "tdm_ao_b"; 1901 bias-disable; 1902 }; 1903 }; 1904 1905 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1906 mux { 1907 groups = "tdm_ao_b_slv_sclk"; 1908 function = "tdm_ao_b"; 1909 bias-disable; 1910 }; 1911 }; 1912 1913 uart_ao_a_pins: uart-a-ao { 1914 mux { 1915 groups = "uart_ao_a_tx", 1916 "uart_ao_a_rx"; 1917 function = "uart_ao_a"; 1918 bias-disable; 1919 }; 1920 }; 1921 1922 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1923 mux { 1924 groups = "uart_ao_a_cts", 1925 "uart_ao_a_rts"; 1926 function = "uart_ao_a"; 1927 bias-disable; 1928 }; 1929 }; 1930 1931 pwm_a_e_pins: pwm-a-e { 1932 mux { 1933 groups = "pwm_a_e"; 1934 function = "pwm_a_e"; 1935 bias-disable; 1936 }; 1937 }; 1938 1939 pwm_ao_a_pins: pwm-ao-a { 1940 mux { 1941 groups = "pwm_ao_a"; 1942 function = "pwm_ao_a"; 1943 bias-disable; 1944 }; 1945 }; 1946 1947 pwm_ao_b_pins: pwm-ao-b { 1948 mux { 1949 groups = "pwm_ao_b"; 1950 function = "pwm_ao_b"; 1951 bias-disable; 1952 }; 1953 }; 1954 1955 pwm_ao_c_4_pins: pwm-ao-c-4 { 1956 mux { 1957 groups = "pwm_ao_c_4"; 1958 function = "pwm_ao_c"; 1959 bias-disable; 1960 }; 1961 }; 1962 1963 pwm_ao_c_6_pins: pwm-ao-c-6 { 1964 mux { 1965 groups = "pwm_ao_c_6"; 1966 function = "pwm_ao_c"; 1967 bias-disable; 1968 }; 1969 }; 1970 1971 pwm_ao_d_5_pins: pwm-ao-d-5 { 1972 mux { 1973 groups = "pwm_ao_d_5"; 1974 function = "pwm_ao_d"; 1975 bias-disable; 1976 }; 1977 }; 1978 1979 pwm_ao_d_10_pins: pwm-ao-d-10 { 1980 mux { 1981 groups = "pwm_ao_d_10"; 1982 function = "pwm_ao_d"; 1983 bias-disable; 1984 }; 1985 }; 1986 1987 pwm_ao_d_e_pins: pwm-ao-d-e { 1988 mux { 1989 groups = "pwm_ao_d_e"; 1990 function = "pwm_ao_d"; 1991 }; 1992 }; 1993 1994 remote_input_ao_pins: remote-input-ao { 1995 mux { 1996 groups = "remote_ao_input"; 1997 function = "remote_ao_input"; 1998 bias-disable; 1999 }; 2000 }; 2001 }; 2002 }; 2003 2004 vrtc: rtc@0a8 { 2005 compatible = "amlogic,meson-vrtc"; 2006 reg = <0x0 0x000a8 0x0 0x4>; 2007 }; 2008 2009 cec_AO: cec@100 { 2010 compatible = "amlogic,meson-gx-ao-cec"; 2011 reg = <0x0 0x00100 0x0 0x14>; 2012 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2013 clocks = <&clkc_AO CLKID_AO_CEC>; 2014 clock-names = "core"; 2015 status = "disabled"; 2016 }; 2017 2018 sec_AO: ao-secure@140 { 2019 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2020 reg = <0x0 0x140 0x0 0x140>; 2021 amlogic,has-chip-id; 2022 }; 2023 2024 cecb_AO: cec@280 { 2025 compatible = "amlogic,meson-g12a-ao-cec"; 2026 reg = <0x0 0x00280 0x0 0x1c>; 2027 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2028 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2029 clock-names = "oscin"; 2030 status = "disabled"; 2031 }; 2032 2033 pwm_AO_cd: pwm@2000 { 2034 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2035 reg = <0x0 0x2000 0x0 0x20>; 2036 #pwm-cells = <3>; 2037 status = "disabled"; 2038 }; 2039 2040 uart_AO: serial@3000 { 2041 compatible = "amlogic,meson-gx-uart", 2042 "amlogic,meson-ao-uart"; 2043 reg = <0x0 0x3000 0x0 0x18>; 2044 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2045 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2046 clock-names = "xtal", "pclk", "baud"; 2047 status = "disabled"; 2048 }; 2049 2050 uart_AO_B: serial@4000 { 2051 compatible = "amlogic,meson-gx-uart", 2052 "amlogic,meson-ao-uart"; 2053 reg = <0x0 0x4000 0x0 0x18>; 2054 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2055 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2056 clock-names = "xtal", "pclk", "baud"; 2057 status = "disabled"; 2058 }; 2059 2060 i2c_AO: i2c@5000 { 2061 compatible = "amlogic,meson-axg-i2c"; 2062 status = "disabled"; 2063 reg = <0x0 0x05000 0x0 0x20>; 2064 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2065 #address-cells = <1>; 2066 #size-cells = <0>; 2067 clocks = <&clkc CLKID_I2C>; 2068 }; 2069 2070 pwm_AO_ab: pwm@7000 { 2071 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2072 reg = <0x0 0x7000 0x0 0x20>; 2073 #pwm-cells = <3>; 2074 status = "disabled"; 2075 }; 2076 2077 ir: ir@8000 { 2078 compatible = "amlogic,meson-gxbb-ir"; 2079 reg = <0x0 0x8000 0x0 0x20>; 2080 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2081 status = "disabled"; 2082 }; 2083 2084 saradc: adc@9000 { 2085 compatible = "amlogic,meson-g12a-saradc", 2086 "amlogic,meson-saradc"; 2087 reg = <0x0 0x9000 0x0 0x48>; 2088 #io-channel-cells = <1>; 2089 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2090 clocks = <&xtal>, 2091 <&clkc_AO CLKID_AO_SAR_ADC>, 2092 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2093 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2094 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2095 status = "disabled"; 2096 }; 2097 }; 2098 2099 vdec: video-decoder@ff620000 { 2100 compatible = "amlogic,g12a-vdec"; 2101 reg = <0x0 0xff620000 0x0 0x10000>, 2102 <0x0 0xffd0e180 0x0 0xe4>; 2103 reg-names = "dos", "esparser"; 2104 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2105 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2106 interrupt-names = "vdec", "esparser"; 2107 2108 amlogic,ao-sysctrl = <&rti>; 2109 amlogic,canvas = <&canvas>; 2110 2111 clocks = <&clkc CLKID_PARSER>, 2112 <&clkc CLKID_DOS>, 2113 <&clkc CLKID_VDEC_1>, 2114 <&clkc CLKID_VDEC_HEVC>, 2115 <&clkc CLKID_VDEC_HEVCF>; 2116 clock-names = "dos_parser", "dos", "vdec_1", 2117 "vdec_hevc", "vdec_hevcf"; 2118 resets = <&reset RESET_PARSER>; 2119 reset-names = "esparser"; 2120 }; 2121 2122 vpu: vpu@ff900000 { 2123 compatible = "amlogic,meson-g12a-vpu"; 2124 reg = <0x0 0xff900000 0x0 0x100000>, 2125 <0x0 0xff63c000 0x0 0x1000>; 2126 reg-names = "vpu", "hhi"; 2127 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 amlogic,canvas = <&canvas>; 2131 2132 /* CVBS VDAC output port */ 2133 cvbs_vdac_port: port@0 { 2134 reg = <0>; 2135 }; 2136 2137 /* HDMI-TX output port */ 2138 hdmi_tx_port: port@1 { 2139 reg = <1>; 2140 2141 hdmi_tx_out: endpoint { 2142 remote-endpoint = <&hdmi_tx_in>; 2143 }; 2144 }; 2145 }; 2146 2147 gic: interrupt-controller@ffc01000 { 2148 compatible = "arm,gic-400"; 2149 reg = <0x0 0xffc01000 0 0x1000>, 2150 <0x0 0xffc02000 0 0x2000>, 2151 <0x0 0xffc04000 0 0x2000>, 2152 <0x0 0xffc06000 0 0x2000>; 2153 interrupt-controller; 2154 interrupts = <GIC_PPI 9 2155 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2156 #interrupt-cells = <3>; 2157 #address-cells = <0>; 2158 }; 2159 2160 cbus: bus@ffd00000 { 2161 compatible = "simple-bus"; 2162 reg = <0x0 0xffd00000 0x0 0x100000>; 2163 #address-cells = <2>; 2164 #size-cells = <2>; 2165 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2166 2167 reset: reset-controller@1004 { 2168 compatible = "amlogic,meson-axg-reset"; 2169 reg = <0x0 0x1004 0x0 0x9c>; 2170 #reset-cells = <1>; 2171 }; 2172 2173 gpio_intc: interrupt-controller@f080 { 2174 compatible = "amlogic,meson-g12a-gpio-intc", 2175 "amlogic,meson-gpio-intc"; 2176 reg = <0x0 0xf080 0x0 0x10>; 2177 interrupt-controller; 2178 #interrupt-cells = <2>; 2179 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2180 }; 2181 2182 spicc0: spi@13000 { 2183 compatible = "amlogic,meson-g12a-spicc"; 2184 reg = <0x0 0x13000 0x0 0x44>; 2185 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2186 clocks = <&clkc CLKID_SPICC0>, 2187 <&clkc CLKID_SPICC0_SCLK>; 2188 clock-names = "core", "pclk"; 2189 #address-cells = <1>; 2190 #size-cells = <0>; 2191 status = "disabled"; 2192 }; 2193 2194 spicc1: spi@15000 { 2195 compatible = "amlogic,meson-g12a-spicc"; 2196 reg = <0x0 0x15000 0x0 0x44>; 2197 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2198 clocks = <&clkc CLKID_SPICC1>, 2199 <&clkc CLKID_SPICC1_SCLK>; 2200 clock-names = "core", "pclk"; 2201 #address-cells = <1>; 2202 #size-cells = <0>; 2203 status = "disabled"; 2204 }; 2205 2206 spifc: spi@14000 { 2207 compatible = "amlogic,meson-gxbb-spifc"; 2208 status = "disabled"; 2209 reg = <0x0 0x14000 0x0 0x80>; 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 clocks = <&clkc CLKID_CLK81>; 2213 }; 2214 2215 pwm_ef: pwm@19000 { 2216 compatible = "amlogic,meson-g12a-ee-pwm"; 2217 reg = <0x0 0x19000 0x0 0x20>; 2218 #pwm-cells = <3>; 2219 status = "disabled"; 2220 }; 2221 2222 pwm_cd: pwm@1a000 { 2223 compatible = "amlogic,meson-g12a-ee-pwm"; 2224 reg = <0x0 0x1a000 0x0 0x20>; 2225 #pwm-cells = <3>; 2226 status = "disabled"; 2227 }; 2228 2229 pwm_ab: pwm@1b000 { 2230 compatible = "amlogic,meson-g12a-ee-pwm"; 2231 reg = <0x0 0x1b000 0x0 0x20>; 2232 #pwm-cells = <3>; 2233 status = "disabled"; 2234 }; 2235 2236 i2c3: i2c@1c000 { 2237 compatible = "amlogic,meson-axg-i2c"; 2238 status = "disabled"; 2239 reg = <0x0 0x1c000 0x0 0x20>; 2240 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2241 #address-cells = <1>; 2242 #size-cells = <0>; 2243 clocks = <&clkc CLKID_I2C>; 2244 }; 2245 2246 i2c2: i2c@1d000 { 2247 compatible = "amlogic,meson-axg-i2c"; 2248 status = "disabled"; 2249 reg = <0x0 0x1d000 0x0 0x20>; 2250 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2251 #address-cells = <1>; 2252 #size-cells = <0>; 2253 clocks = <&clkc CLKID_I2C>; 2254 }; 2255 2256 i2c1: i2c@1e000 { 2257 compatible = "amlogic,meson-axg-i2c"; 2258 status = "disabled"; 2259 reg = <0x0 0x1e000 0x0 0x20>; 2260 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 clocks = <&clkc CLKID_I2C>; 2264 }; 2265 2266 i2c0: i2c@1f000 { 2267 compatible = "amlogic,meson-axg-i2c"; 2268 status = "disabled"; 2269 reg = <0x0 0x1f000 0x0 0x20>; 2270 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2271 #address-cells = <1>; 2272 #size-cells = <0>; 2273 clocks = <&clkc CLKID_I2C>; 2274 }; 2275 2276 clk_msr: clock-measure@18000 { 2277 compatible = "amlogic,meson-g12a-clk-measure"; 2278 reg = <0x0 0x18000 0x0 0x10>; 2279 }; 2280 2281 uart_C: serial@22000 { 2282 compatible = "amlogic,meson-gx-uart"; 2283 reg = <0x0 0x22000 0x0 0x18>; 2284 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2285 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2286 clock-names = "xtal", "pclk", "baud"; 2287 status = "disabled"; 2288 }; 2289 2290 uart_B: serial@23000 { 2291 compatible = "amlogic,meson-gx-uart"; 2292 reg = <0x0 0x23000 0x0 0x18>; 2293 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2294 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2295 clock-names = "xtal", "pclk", "baud"; 2296 status = "disabled"; 2297 }; 2298 2299 uart_A: serial@24000 { 2300 compatible = "amlogic,meson-gx-uart"; 2301 reg = <0x0 0x24000 0x0 0x18>; 2302 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2303 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2304 clock-names = "xtal", "pclk", "baud"; 2305 status = "disabled"; 2306 }; 2307 }; 2308 2309 sd_emmc_a: sd@ffe03000 { 2310 compatible = "amlogic,meson-axg-mmc"; 2311 reg = <0x0 0xffe03000 0x0 0x800>; 2312 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2313 status = "disabled"; 2314 clocks = <&clkc CLKID_SD_EMMC_A>, 2315 <&clkc CLKID_SD_EMMC_A_CLK0>, 2316 <&clkc CLKID_FCLK_DIV2>; 2317 clock-names = "core", "clkin0", "clkin1"; 2318 resets = <&reset RESET_SD_EMMC_A>; 2319 }; 2320 2321 sd_emmc_b: sd@ffe05000 { 2322 compatible = "amlogic,meson-axg-mmc"; 2323 reg = <0x0 0xffe05000 0x0 0x800>; 2324 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2325 status = "disabled"; 2326 clocks = <&clkc CLKID_SD_EMMC_B>, 2327 <&clkc CLKID_SD_EMMC_B_CLK0>, 2328 <&clkc CLKID_FCLK_DIV2>; 2329 clock-names = "core", "clkin0", "clkin1"; 2330 resets = <&reset RESET_SD_EMMC_B>; 2331 }; 2332 2333 sd_emmc_c: mmc@ffe07000 { 2334 compatible = "amlogic,meson-axg-mmc"; 2335 reg = <0x0 0xffe07000 0x0 0x800>; 2336 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2337 status = "disabled"; 2338 clocks = <&clkc CLKID_SD_EMMC_C>, 2339 <&clkc CLKID_SD_EMMC_C_CLK0>, 2340 <&clkc CLKID_FCLK_DIV2>; 2341 clock-names = "core", "clkin0", "clkin1"; 2342 resets = <&reset RESET_SD_EMMC_C>; 2343 }; 2344 2345 usb: usb@ffe09000 { 2346 status = "disabled"; 2347 compatible = "amlogic,meson-g12a-usb-ctrl"; 2348 reg = <0x0 0xffe09000 0x0 0xa0>; 2349 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2350 #address-cells = <2>; 2351 #size-cells = <2>; 2352 ranges; 2353 2354 clocks = <&clkc CLKID_USB>; 2355 resets = <&reset RESET_USB>; 2356 2357 dr_mode = "otg"; 2358 2359 phys = <&usb2_phy0>, <&usb2_phy1>, 2360 <&usb3_pcie_phy PHY_TYPE_USB3>; 2361 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2362 2363 dwc2: usb@ff400000 { 2364 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2365 reg = <0x0 0xff400000 0x0 0x40000>; 2366 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2367 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2368 clock-names = "otg"; 2369 phys = <&usb2_phy1>; 2370 phy-names = "usb2-phy"; 2371 dr_mode = "peripheral"; 2372 g-rx-fifo-size = <192>; 2373 g-np-tx-fifo-size = <128>; 2374 g-tx-fifo-size = <128 128 16 16 16>; 2375 }; 2376 2377 dwc3: usb@ff500000 { 2378 compatible = "snps,dwc3"; 2379 reg = <0x0 0xff500000 0x0 0x100000>; 2380 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2381 dr_mode = "host"; 2382 snps,dis_u2_susphy_quirk; 2383 snps,quirk-frame-length-adjustment; 2384 snps,parkmode-disable-ss-quirk; 2385 }; 2386 }; 2387 2388 mali: gpu@ffe40000 { 2389 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2390 reg = <0x0 0xffe40000 0x0 0x40000>; 2391 interrupt-parent = <&gic>; 2392 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2395 interrupt-names = "job", "mmu", "gpu"; 2396 clocks = <&clkc CLKID_MALI>; 2397 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2398 operating-points-v2 = <&gpu_opp_table>; 2399 #cooling-cells = <2>; 2400 }; 2401 }; 2402 2403 timer { 2404 compatible = "arm,armv8-timer"; 2405 interrupts = <GIC_PPI 13 2406 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2407 <GIC_PPI 14 2408 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2409 <GIC_PPI 11 2410 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2411 <GIC_PPI 10 2412 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2413 arm,no-tick-in-suspend; 2414 }; 2415 2416 xtal: xtal-clk { 2417 compatible = "fixed-clock"; 2418 clock-frequency = <24000000>; 2419 clock-output-names = "xtal"; 2420 #clock-cells = <0>; 2421 }; 2422 2423}; 2424