1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7 8/ { 9 compatible = "nvidia,tegra210"; 10 interrupt-parent = <&lic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 pcie@1003000 { 15 compatible = "nvidia,tegra210-pcie"; 16 device_type = "pci"; 17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 20 reg-names = "pads", "afi", "cs"; 21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23 interrupt-names = "intr", "msi"; 24 25 #interrupt-cells = <1>; 26 interrupt-map-mask = <0 0 0 0>; 27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 28 29 bus-range = <0x00 0xff>; 30 #address-cells = <3>; 31 #size-cells = <2>; 32 33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 38 39 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 40 <&tegra_car TEGRA210_CLK_AFI>, 41 <&tegra_car TEGRA210_CLK_PLL_E>, 42 <&tegra_car TEGRA210_CLK_CML0>; 43 clock-names = "pex", "afi", "pll_e", "cml"; 44 resets = <&tegra_car 70>, 45 <&tegra_car 72>, 46 <&tegra_car 74>; 47 reset-names = "pex", "afi", "pcie_x"; 48 status = "disabled"; 49 50 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 51 phy-names = "pcie"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 status = "disabled"; 58 59 #address-cells = <3>; 60 #size-cells = <2>; 61 ranges; 62 63 nvidia,num-lanes = <4>; 64 }; 65 66 pci@2,0 { 67 device_type = "pci"; 68 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 69 reg = <0x001000 0 0 0 0>; 70 status = "disabled"; 71 72 #address-cells = <3>; 73 #size-cells = <2>; 74 ranges; 75 76 nvidia,num-lanes = <1>; 77 }; 78 }; 79 80 host1x@50000000 { 81 compatible = "nvidia,tegra210-host1x", "simple-bus"; 82 reg = <0x0 0x50000000 0x0 0x00034000>; 83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 85 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 86 clock-names = "host1x"; 87 resets = <&tegra_car 28>; 88 reset-names = "host1x"; 89 90 #address-cells = <2>; 91 #size-cells = <2>; 92 93 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 94 95 dpaux1: dpaux@54040000 { 96 compatible = "nvidia,tegra210-dpaux"; 97 reg = <0x0 0x54040000 0x0 0x00040000>; 98 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 100 <&tegra_car TEGRA210_CLK_PLL_DP>; 101 clock-names = "dpaux", "parent"; 102 resets = <&tegra_car 207>; 103 reset-names = "dpaux"; 104 status = "disabled"; 105 }; 106 107 vi@54080000 { 108 compatible = "nvidia,tegra210-vi"; 109 reg = <0x0 0x54080000 0x0 0x00040000>; 110 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 111 status = "disabled"; 112 }; 113 114 tsec@54100000 { 115 compatible = "nvidia,tegra210-tsec"; 116 reg = <0x0 0x54100000 0x0 0x00040000>; 117 }; 118 119 dc@54200000 { 120 compatible = "nvidia,tegra210-dc"; 121 reg = <0x0 0x54200000 0x0 0x00040000>; 122 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 124 <&tegra_car TEGRA210_CLK_PLL_P>; 125 clock-names = "dc", "parent"; 126 resets = <&tegra_car 27>; 127 reset-names = "dc"; 128 129 iommus = <&mc TEGRA_SWGROUP_DC>; 130 131 nvidia,head = <0>; 132 }; 133 134 dc@54240000 { 135 compatible = "nvidia,tegra210-dc"; 136 reg = <0x0 0x54240000 0x0 0x00040000>; 137 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 139 <&tegra_car TEGRA210_CLK_PLL_P>; 140 clock-names = "dc", "parent"; 141 resets = <&tegra_car 26>; 142 reset-names = "dc"; 143 144 iommus = <&mc TEGRA_SWGROUP_DCB>; 145 146 nvidia,head = <1>; 147 }; 148 149 dsi@54300000 { 150 compatible = "nvidia,tegra210-dsi"; 151 reg = <0x0 0x54300000 0x0 0x00040000>; 152 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 153 <&tegra_car TEGRA210_CLK_DSIALP>, 154 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 155 clock-names = "dsi", "lp", "parent"; 156 resets = <&tegra_car 48>; 157 reset-names = "dsi"; 158 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 159 160 status = "disabled"; 161 162 #address-cells = <1>; 163 #size-cells = <0>; 164 }; 165 166 vic@54340000 { 167 compatible = "nvidia,tegra210-vic"; 168 reg = <0x0 0x54340000 0x0 0x00040000>; 169 status = "disabled"; 170 }; 171 172 nvjpg@54380000 { 173 compatible = "nvidia,tegra210-nvjpg"; 174 reg = <0x0 0x54380000 0x0 0x00040000>; 175 status = "disabled"; 176 }; 177 178 dsi@54400000 { 179 compatible = "nvidia,tegra210-dsi"; 180 reg = <0x0 0x54400000 0x0 0x00040000>; 181 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 182 <&tegra_car TEGRA210_CLK_DSIBLP>, 183 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 184 clock-names = "dsi", "lp", "parent"; 185 resets = <&tegra_car 82>; 186 reset-names = "dsi"; 187 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 188 189 status = "disabled"; 190 191 #address-cells = <1>; 192 #size-cells = <0>; 193 }; 194 195 nvdec@54480000 { 196 compatible = "nvidia,tegra210-nvdec"; 197 reg = <0x0 0x54480000 0x0 0x00040000>; 198 status = "disabled"; 199 }; 200 201 nvenc@544c0000 { 202 compatible = "nvidia,tegra210-nvenc"; 203 reg = <0x0 0x544c0000 0x0 0x00040000>; 204 status = "disabled"; 205 }; 206 207 tsec@54500000 { 208 compatible = "nvidia,tegra210-tsec"; 209 reg = <0x0 0x54500000 0x0 0x00040000>; 210 status = "disabled"; 211 }; 212 213 sor@54540000 { 214 compatible = "nvidia,tegra210-sor"; 215 reg = <0x0 0x54540000 0x0 0x00040000>; 216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 218 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 219 <&tegra_car TEGRA210_CLK_PLL_DP>, 220 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 221 clock-names = "sor", "parent", "dp", "safe"; 222 resets = <&tegra_car 182>; 223 reset-names = "sor"; 224 status = "disabled"; 225 }; 226 227 sor@54580000 { 228 compatible = "nvidia,tegra210-sor1"; 229 reg = <0x0 0x54580000 0x0 0x00040000>; 230 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 232 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 233 <&tegra_car TEGRA210_CLK_PLL_DP>, 234 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 235 clock-names = "sor", "parent", "dp", "safe"; 236 resets = <&tegra_car 183>; 237 reset-names = "sor"; 238 status = "disabled"; 239 }; 240 241 dpaux: dpaux@545c0000 { 242 compatible = "nvidia,tegra124-dpaux"; 243 reg = <0x0 0x545c0000 0x0 0x00040000>; 244 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 246 <&tegra_car TEGRA210_CLK_PLL_DP>; 247 clock-names = "dpaux", "parent"; 248 resets = <&tegra_car 181>; 249 reset-names = "dpaux"; 250 status = "disabled"; 251 }; 252 253 isp@54600000 { 254 compatible = "nvidia,tegra210-isp"; 255 reg = <0x0 0x54600000 0x0 0x00040000>; 256 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 257 status = "disabled"; 258 }; 259 260 isp@54680000 { 261 compatible = "nvidia,tegra210-isp"; 262 reg = <0x0 0x54680000 0x0 0x00040000>; 263 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 264 status = "disabled"; 265 }; 266 267 i2c@546c0000 { 268 compatible = "nvidia,tegra210-i2c-vi"; 269 reg = <0x0 0x546c0000 0x0 0x00040000>; 270 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 271 status = "disabled"; 272 }; 273 }; 274 275 gic: interrupt-controller@50041000 { 276 compatible = "arm,gic-400"; 277 #interrupt-cells = <3>; 278 interrupt-controller; 279 reg = <0x0 0x50041000 0x0 0x1000>, 280 <0x0 0x50042000 0x0 0x2000>, 281 <0x0 0x50044000 0x0 0x2000>, 282 <0x0 0x50046000 0x0 0x2000>; 283 interrupts = <GIC_PPI 9 284 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 285 interrupt-parent = <&gic>; 286 }; 287 288 gpu@57000000 { 289 compatible = "nvidia,gm20b"; 290 reg = <0x0 0x57000000 0x0 0x01000000>, 291 <0x0 0x58000000 0x0 0x01000000>; 292 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 294 interrupt-names = "stall", "nonstall"; 295 clocks = <&tegra_car TEGRA210_CLK_GPU>, 296 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 297 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 298 clock-names = "gpu", "pwr", "ref"; 299 resets = <&tegra_car 184>; 300 reset-names = "gpu"; 301 302 iommus = <&mc TEGRA_SWGROUP_GPU>; 303 304 status = "disabled"; 305 }; 306 307 lic: interrupt-controller@60004000 { 308 compatible = "nvidia,tegra210-ictlr"; 309 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 310 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 311 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 312 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 313 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 314 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 315 interrupt-controller; 316 #interrupt-cells = <3>; 317 interrupt-parent = <&gic>; 318 }; 319 320 timer@60005000 { 321 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 322 reg = <0x0 0x60005000 0x0 0x400>; 323 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 330 clock-names = "timer"; 331 }; 332 333 tegra_car: clock@60006000 { 334 compatible = "nvidia,tegra210-car"; 335 reg = <0x0 0x60006000 0x0 0x1000>; 336 #clock-cells = <1>; 337 #reset-cells = <1>; 338 }; 339 340 flow-controller@60007000 { 341 compatible = "nvidia,tegra210-flowctrl"; 342 reg = <0x0 0x60007000 0x0 0x1000>; 343 }; 344 345 gpio: gpio@6000d000 { 346 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 347 reg = <0x0 0x6000d000 0x0 0x1000>; 348 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 356 #gpio-cells = <2>; 357 gpio-controller; 358 #interrupt-cells = <2>; 359 interrupt-controller; 360 }; 361 362 apbdma: dma@60020000 { 363 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 364 reg = <0x0 0x60020000 0x0 0x1400>; 365 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 398 clock-names = "dma"; 399 resets = <&tegra_car 34>; 400 reset-names = "dma"; 401 #dma-cells = <1>; 402 }; 403 404 apbmisc@70000800 { 405 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 406 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 407 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 408 }; 409 410 pinmux: pinmux@700008d4 { 411 compatible = "nvidia,tegra210-pinmux"; 412 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 413 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 414 }; 415 416 /* 417 * There are two serial driver i.e. 8250 based simple serial 418 * driver and APB DMA based serial driver for higher baudrate 419 * and performance. To enable the 8250 based driver, the compatible 420 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 421 * the APB DMA based serial driver, the compatible is 422 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 423 */ 424 uarta: serial@70006000 { 425 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 426 reg = <0x0 0x70006000 0x0 0x40>; 427 reg-shift = <2>; 428 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 430 clock-names = "serial"; 431 resets = <&tegra_car 6>; 432 reset-names = "serial"; 433 dmas = <&apbdma 8>, <&apbdma 8>; 434 dma-names = "rx", "tx"; 435 status = "disabled"; 436 }; 437 438 uartb: serial@70006040 { 439 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 440 reg = <0x0 0x70006040 0x0 0x40>; 441 reg-shift = <2>; 442 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 444 clock-names = "serial"; 445 resets = <&tegra_car 7>; 446 reset-names = "serial"; 447 dmas = <&apbdma 9>, <&apbdma 9>; 448 dma-names = "rx", "tx"; 449 status = "disabled"; 450 }; 451 452 uartc: serial@70006200 { 453 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 454 reg = <0x0 0x70006200 0x0 0x40>; 455 reg-shift = <2>; 456 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 458 clock-names = "serial"; 459 resets = <&tegra_car 55>; 460 reset-names = "serial"; 461 dmas = <&apbdma 10>, <&apbdma 10>; 462 dma-names = "rx", "tx"; 463 status = "disabled"; 464 }; 465 466 uartd: serial@70006300 { 467 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 468 reg = <0x0 0x70006300 0x0 0x40>; 469 reg-shift = <2>; 470 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 472 clock-names = "serial"; 473 resets = <&tegra_car 65>; 474 reset-names = "serial"; 475 dmas = <&apbdma 19>, <&apbdma 19>; 476 dma-names = "rx", "tx"; 477 status = "disabled"; 478 }; 479 480 pwm: pwm@7000a000 { 481 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 482 reg = <0x0 0x7000a000 0x0 0x100>; 483 #pwm-cells = <2>; 484 clocks = <&tegra_car TEGRA210_CLK_PWM>; 485 clock-names = "pwm"; 486 resets = <&tegra_car 17>; 487 reset-names = "pwm"; 488 status = "disabled"; 489 }; 490 491 i2c@7000c000 { 492 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 493 reg = <0x0 0x7000c000 0x0 0x100>; 494 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 498 clock-names = "div-clk"; 499 resets = <&tegra_car 12>; 500 reset-names = "i2c"; 501 dmas = <&apbdma 21>, <&apbdma 21>; 502 dma-names = "rx", "tx"; 503 status = "disabled"; 504 }; 505 506 i2c@7000c400 { 507 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 508 reg = <0x0 0x7000c400 0x0 0x100>; 509 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 513 clock-names = "div-clk"; 514 resets = <&tegra_car 54>; 515 reset-names = "i2c"; 516 dmas = <&apbdma 22>, <&apbdma 22>; 517 dma-names = "rx", "tx"; 518 status = "disabled"; 519 }; 520 521 i2c@7000c500 { 522 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 523 reg = <0x0 0x7000c500 0x0 0x100>; 524 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 528 clock-names = "div-clk"; 529 resets = <&tegra_car 67>; 530 reset-names = "i2c"; 531 dmas = <&apbdma 23>, <&apbdma 23>; 532 dma-names = "rx", "tx"; 533 status = "disabled"; 534 }; 535 536 i2c@7000c700 { 537 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 538 reg = <0x0 0x7000c700 0x0 0x100>; 539 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 543 clock-names = "div-clk"; 544 resets = <&tegra_car 103>; 545 reset-names = "i2c"; 546 dmas = <&apbdma 26>, <&apbdma 26>; 547 dma-names = "rx", "tx"; 548 status = "disabled"; 549 }; 550 551 i2c@7000d000 { 552 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 553 reg = <0x0 0x7000d000 0x0 0x100>; 554 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 558 clock-names = "div-clk"; 559 resets = <&tegra_car 47>; 560 reset-names = "i2c"; 561 dmas = <&apbdma 24>, <&apbdma 24>; 562 dma-names = "rx", "tx"; 563 status = "disabled"; 564 }; 565 566 i2c@7000d100 { 567 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 568 reg = <0x0 0x7000d100 0x0 0x100>; 569 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 573 clock-names = "div-clk"; 574 resets = <&tegra_car 166>; 575 reset-names = "i2c"; 576 dmas = <&apbdma 30>, <&apbdma 30>; 577 dma-names = "rx", "tx"; 578 status = "disabled"; 579 }; 580 581 spi@7000d400 { 582 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 583 reg = <0x0 0x7000d400 0x0 0x200>; 584 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 588 clock-names = "spi"; 589 resets = <&tegra_car 41>; 590 reset-names = "spi"; 591 dmas = <&apbdma 15>, <&apbdma 15>; 592 dma-names = "rx", "tx"; 593 status = "disabled"; 594 }; 595 596 spi@7000d600 { 597 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 598 reg = <0x0 0x7000d600 0x0 0x200>; 599 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 603 clock-names = "spi"; 604 resets = <&tegra_car 44>; 605 reset-names = "spi"; 606 dmas = <&apbdma 16>, <&apbdma 16>; 607 dma-names = "rx", "tx"; 608 status = "disabled"; 609 }; 610 611 spi@7000d800 { 612 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 613 reg = <0x0 0x7000d800 0x0 0x200>; 614 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 618 clock-names = "spi"; 619 resets = <&tegra_car 46>; 620 reset-names = "spi"; 621 dmas = <&apbdma 17>, <&apbdma 17>; 622 dma-names = "rx", "tx"; 623 status = "disabled"; 624 }; 625 626 spi@7000da00 { 627 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 628 reg = <0x0 0x7000da00 0x0 0x200>; 629 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 633 clock-names = "spi"; 634 resets = <&tegra_car 68>; 635 reset-names = "spi"; 636 dmas = <&apbdma 18>, <&apbdma 18>; 637 dma-names = "rx", "tx"; 638 status = "disabled"; 639 }; 640 641 rtc@7000e000 { 642 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 643 reg = <0x0 0x7000e000 0x0 0x100>; 644 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&tegra_car TEGRA210_CLK_RTC>; 646 clock-names = "rtc"; 647 }; 648 649 pmc: pmc@7000e400 { 650 compatible = "nvidia,tegra210-pmc"; 651 reg = <0x0 0x7000e400 0x0 0x400>; 652 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 653 clock-names = "pclk", "clk32k_in"; 654 }; 655 656 fuse@7000f800 { 657 compatible = "nvidia,tegra210-efuse"; 658 reg = <0x0 0x7000f800 0x0 0x400>; 659 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 660 clock-names = "fuse"; 661 resets = <&tegra_car 39>; 662 reset-names = "fuse"; 663 }; 664 665 mc: memory-controller@70019000 { 666 compatible = "nvidia,tegra210-mc"; 667 reg = <0x0 0x70019000 0x0 0x1000>; 668 clocks = <&tegra_car TEGRA210_CLK_MC>; 669 clock-names = "mc"; 670 671 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 672 673 #iommu-cells = <1>; 674 }; 675 676 hda@70030000 { 677 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 678 reg = <0x0 0x70030000 0x0 0x10000>; 679 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&tegra_car TEGRA210_CLK_HDA>, 681 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 682 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 683 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 684 resets = <&tegra_car 125>, /* hda */ 685 <&tegra_car 128>, /* hda2hdmi */ 686 <&tegra_car 111>; /* hda2codec_2x */ 687 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 688 status = "disabled"; 689 }; 690 691 padctl: padctl@7009f000 { 692 compatible = "nvidia,tegra210-xusb-padctl"; 693 reg = <0x0 0x7009f000 0x0 0x1000>; 694 resets = <&tegra_car 142>; 695 reset-names = "padctl"; 696 #phy-cells = <1>; 697 }; 698 699 sdhci@700b0000 { 700 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 701 reg = <0x0 0x700b0000 0x0 0x200>; 702 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 704 clock-names = "sdhci"; 705 resets = <&tegra_car 14>; 706 reset-names = "sdhci"; 707 status = "disabled"; 708 }; 709 710 sdhci@700b0200 { 711 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 712 reg = <0x0 0x700b0200 0x0 0x200>; 713 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 715 clock-names = "sdhci"; 716 resets = <&tegra_car 9>; 717 reset-names = "sdhci"; 718 status = "disabled"; 719 }; 720 721 sdhci@700b0400 { 722 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 723 reg = <0x0 0x700b0400 0x0 0x200>; 724 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 726 clock-names = "sdhci"; 727 resets = <&tegra_car 69>; 728 reset-names = "sdhci"; 729 status = "disabled"; 730 }; 731 732 sdhci@700b0600 { 733 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 734 reg = <0x0 0x700b0600 0x0 0x200>; 735 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 737 clock-names = "sdhci"; 738 resets = <&tegra_car 15>; 739 reset-names = "sdhci"; 740 status = "disabled"; 741 }; 742 743 mipi: mipi@700e3000 { 744 compatible = "nvidia,tegra210-mipi"; 745 reg = <0x0 0x700e3000 0x0 0x100>; 746 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 747 clock-names = "mipi-cal"; 748 #nvidia,mipi-calibrate-cells = <1>; 749 }; 750 751 spi@70410000 { 752 compatible = "nvidia,tegra210-qspi"; 753 reg = <0x0 0x70410000 0x0 0x1000>; 754 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 758 clock-names = "qspi"; 759 resets = <&tegra_car 211>; 760 reset-names = "qspi"; 761 dmas = <&apbdma 5>, <&apbdma 5>; 762 dma-names = "rx", "tx"; 763 status = "disabled"; 764 }; 765 766 usb@7d000000 { 767 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 768 reg = <0x0 0x7d000000 0x0 0x4000>; 769 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 770 phy_type = "utmi"; 771 clocks = <&tegra_car TEGRA210_CLK_USBD>; 772 clock-names = "usb"; 773 resets = <&tegra_car 22>; 774 reset-names = "usb"; 775 nvidia,phy = <&phy1>; 776 status = "disabled"; 777 }; 778 779 phy1: usb-phy@7d000000 { 780 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 781 reg = <0x0 0x7d000000 0x0 0x4000>, 782 <0x0 0x7d000000 0x0 0x4000>; 783 phy_type = "utmi"; 784 clocks = <&tegra_car TEGRA210_CLK_USBD>, 785 <&tegra_car TEGRA210_CLK_PLL_U>, 786 <&tegra_car TEGRA210_CLK_USBD>; 787 clock-names = "reg", "pll_u", "utmi-pads"; 788 resets = <&tegra_car 22>, <&tegra_car 22>; 789 reset-names = "usb", "utmi-pads"; 790 nvidia,hssync-start-delay = <0>; 791 nvidia,idle-wait-delay = <17>; 792 nvidia,elastic-limit = <16>; 793 nvidia,term-range-adj = <6>; 794 nvidia,xcvr-setup = <9>; 795 nvidia,xcvr-lsfslew = <0>; 796 nvidia,xcvr-lsrslew = <3>; 797 nvidia,hssquelch-level = <2>; 798 nvidia,hsdiscon-level = <5>; 799 nvidia,xcvr-hsslew = <12>; 800 nvidia,has-utmi-pad-registers; 801 status = "disabled"; 802 }; 803 804 usb@7d004000 { 805 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 806 reg = <0x0 0x7d004000 0x0 0x4000>; 807 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 808 phy_type = "utmi"; 809 clocks = <&tegra_car TEGRA210_CLK_USB2>; 810 clock-names = "usb"; 811 resets = <&tegra_car 58>; 812 reset-names = "usb"; 813 nvidia,phy = <&phy2>; 814 status = "disabled"; 815 }; 816 817 phy2: usb-phy@7d004000 { 818 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 819 reg = <0x0 0x7d004000 0x0 0x4000>, 820 <0x0 0x7d000000 0x0 0x4000>; 821 phy_type = "utmi"; 822 clocks = <&tegra_car TEGRA210_CLK_USB2>, 823 <&tegra_car TEGRA210_CLK_PLL_U>, 824 <&tegra_car TEGRA210_CLK_USBD>; 825 clock-names = "reg", "pll_u", "utmi-pads"; 826 resets = <&tegra_car 58>, <&tegra_car 22>; 827 reset-names = "usb", "utmi-pads"; 828 nvidia,hssync-start-delay = <0>; 829 nvidia,idle-wait-delay = <17>; 830 nvidia,elastic-limit = <16>; 831 nvidia,term-range-adj = <6>; 832 nvidia,xcvr-setup = <9>; 833 nvidia,xcvr-lsfslew = <0>; 834 nvidia,xcvr-lsrslew = <3>; 835 nvidia,hssquelch-level = <2>; 836 nvidia,hsdiscon-level = <5>; 837 nvidia,xcvr-hsslew = <12>; 838 status = "disabled"; 839 }; 840 841 cpus { 842 #address-cells = <1>; 843 #size-cells = <0>; 844 845 cpu@0 { 846 device_type = "cpu"; 847 compatible = "arm,cortex-a57"; 848 reg = <0>; 849 }; 850 851 cpu@1 { 852 device_type = "cpu"; 853 compatible = "arm,cortex-a57"; 854 reg = <1>; 855 }; 856 857 cpu@2 { 858 device_type = "cpu"; 859 compatible = "arm,cortex-a57"; 860 reg = <2>; 861 }; 862 863 cpu@3 { 864 device_type = "cpu"; 865 compatible = "arm,cortex-a57"; 866 reg = <3>; 867 }; 868 }; 869 870 psci { 871 compatible = "arm,psci-1.0"; 872 method = "smc"; 873 }; 874 875 timer { 876 compatible = "arm,armv8-timer"; 877 interrupts = <GIC_PPI 13 878 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 879 <GIC_PPI 14 880 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 881 <GIC_PPI 11 882 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 883 <GIC_PPI 10 884 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 885 interrupt-parent = <&gic>; 886 }; 887}; 888