1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/net/ti-dp83867.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 15/dts-v1/; 16/plugin/; 17 18/{ 19 compatible = "xlnx,zynqmp-sk-kv260-rev1", 20 "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA", 21 "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; 22 23 fragment1 { 24 target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */ 25 26 __overlay__ { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 pinctrl-names = "default", "gpio"; 30 pinctrl-0 = <&pinctrl_i2c1_default>; 31 pinctrl-1 = <&pinctrl_i2c1_gpio>; 32 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 33 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 34 35 u14: ina260@40 { /* u14 */ 36 compatible = "ti,ina260"; 37 #io-channel-cells = <1>; 38 label = "ina260-u14"; 39 reg = <0x40>; 40 }; 41 usbhub: usb5744@2d { /* u43 */ 42 compatible = "microchip,usb5744"; 43 reg = <0x2d>; 44 reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; 45 }; 46 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 47 }; 48 }; 49 50 fragment1a { 51 target = <&amba>; 52 __overlay__ { 53 ina260-u14 { 54 compatible = "iio-hwmon"; 55 io-channels = <&u14 0>, <&u14 1>, <&u14 2>; 56 }; 57 58 si5332_0: si5332_0 { /* u17 */ 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <125000000>; 62 }; 63 64 si5332_1: si5332_1 { /* u17 */ 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <25000000>; 68 }; 69 70 si5332_2: si5332_2 { /* u17 */ 71 compatible = "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <48000000>; 74 }; 75 76 si5332_3: si5332_3 { /* u17 */ 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <24000000>; 80 }; 81 82 si5332_4: si5332_4 { /* u17 */ 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <26000000>; 86 }; 87 88 si5332_5: si5332_5 { /* u17 */ 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <27000000>; 92 }; 93 }; 94 }; 95 96/* DP/USB 3.0 */ 97 fragment2 { 98 target = <&psgtr>; 99 __overlay__ { 100 status = "okay"; 101 /* pcie, usb3, sata */ 102 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 103 clock-names = "ref0", "ref1", "ref2"; 104 }; 105 }; 106 107 fragment4 { 108 target = <&zynqmp_dpsub>; 109 __overlay__ { 110 status = "disabled"; 111 phy-names = "dp-phy0", "dp-phy1"; 112 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 113 }; 114 }; 115 116 fragment9 { 117 target = <&zynqmp_dpdma>; 118 __overlay__ { 119 status = "okay"; 120 }; 121 }; 122 123 fragment10 { 124 target = <&usb0>; 125 __overlay__ { 126 status = "okay"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_usb0_default>; 129 }; 130 }; 131 132 fragment11 { 133 target = <&dwc3_0>; 134 __overlay__ { 135 status = "okay"; 136 dr_mode = "host"; 137 snps,usb3_lpm_capable; 138 phy-names = "usb3-phy"; 139 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 140 maximum-speed = "super-speed"; 141 }; 142 }; 143 144 fragment12 { 145 target = <&sdhci1>; /* on CC with tuned parameters */ 146 __overlay__ { 147 status = "okay"; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_sdhci1_default>; 150 /* 151 * SD 3.0 requires level shifter and this property 152 * should be removed if the board has level shifter and 153 * need to work in UHS mode 154 */ 155 no-1-8-v; 156 disable-wp; 157 xlnx,mio-bank = <1>; 158 clk-phase-sd-hs = <126>, <60>; 159 clk-phase-uhs-sdr25 = <120>, <60>; 160 clk-phase-uhs-ddr50 = <126>, <48>; 161 }; 162 }; 163 164 fragment13 { 165 target = <&gem3>; /* required by spec */ 166 __overlay__ { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 status = "okay"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_gem3_default>; 172 phy-handle = <&phy0>; 173 phy-mode = "rgmii-id"; 174 175 mdio: mdio { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 179 reset-delay-us = <2>; 180 181 phy0: ethernet-phy@1 { 182 #phy-cells = <1>; 183 reg = <1>; 184 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 185 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 186 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 187 ti,dp83867-rxctrl-strap-quirk; 188 }; 189 }; 190 }; 191 }; 192 193 fragment14 { 194 target = <&pinctrl0>; /* required by spec */ 195 __overlay__ { 196 status = "okay"; 197 198 pinctrl_uart1_default: uart1-default { 199 conf { 200 groups = "uart1_9_grp"; 201 slew-rate = <SLEW_RATE_SLOW>; 202 power-source = <IO_STANDARD_LVCMOS18>; 203 drive-strength = <12>; 204 }; 205 206 conf-rx { 207 pins = "MIO37"; 208 bias-high-impedance; 209 }; 210 211 conf-tx { 212 pins = "MIO36"; 213 bias-disable; 214 }; 215 216 mux { 217 groups = "uart1_9_grp"; 218 function = "uart1"; 219 }; 220 }; 221 222 pinctrl_i2c1_default: i2c1-default { 223 conf { 224 groups = "i2c1_6_grp"; 225 bias-pull-up; 226 slew-rate = <SLEW_RATE_SLOW>; 227 power-source = <IO_STANDARD_LVCMOS18>; 228 }; 229 230 mux { 231 groups = "i2c1_6_grp"; 232 function = "i2c1"; 233 }; 234 }; 235 236 pinctrl_i2c1_gpio: i2c1-gpio { 237 conf { 238 groups = "gpio0_24_grp", "gpio0_25_grp"; 239 slew-rate = <SLEW_RATE_SLOW>; 240 power-source = <IO_STANDARD_LVCMOS18>; 241 }; 242 243 mux { 244 groups = "gpio0_24_grp", "gpio0_25_grp"; 245 function = "gpio0"; 246 }; 247 }; 248 249 pinctrl_gem3_default: gem3-default { 250 conf { 251 groups = "ethernet3_0_grp"; 252 slew-rate = <SLEW_RATE_SLOW>; 253 power-source = <IO_STANDARD_LVCMOS18>; 254 }; 255 256 conf-rx { 257 pins = "MIO70", "MIO72", "MIO74"; 258 bias-high-impedance; 259 low-power-disable; 260 }; 261 262 conf-bootstrap { 263 pins = "MIO71", "MIO73", "MIO75"; 264 bias-disable; 265 low-power-disable; 266 }; 267 268 conf-tx { 269 pins = "MIO64", "MIO65", "MIO66", 270 "MIO67", "MIO68", "MIO69"; 271 bias-disable; 272 low-power-enable; 273 }; 274 275 conf-mdio { 276 groups = "mdio3_0_grp"; 277 slew-rate = <SLEW_RATE_SLOW>; 278 power-source = <IO_STANDARD_LVCMOS18>; 279 bias-disable; 280 }; 281 282 mux-mdio { 283 function = "mdio3"; 284 groups = "mdio3_0_grp"; 285 }; 286 287 mux { 288 function = "ethernet3"; 289 groups = "ethernet3_0_grp"; 290 }; 291 }; 292 293 pinctrl_usb0_default: usb0-default { 294 conf { 295 groups = "usb0_0_grp"; 296 slew-rate = <SLEW_RATE_SLOW>; 297 power-source = <IO_STANDARD_LVCMOS18>; 298 }; 299 300 conf-rx { 301 pins = "MIO52", "MIO53", "MIO55"; 302 bias-high-impedance; 303 }; 304 305 conf-tx { 306 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 307 "MIO60", "MIO61", "MIO62", "MIO63"; 308 bias-disable; 309 }; 310 311 mux { 312 groups = "usb0_0_grp"; 313 function = "usb0"; 314 }; 315 }; 316 317 pinctrl_sdhci1_default: sdhci1-default { 318 conf { 319 groups = "sdio1_0_grp"; 320 slew-rate = <SLEW_RATE_SLOW>; 321 power-source = <IO_STANDARD_LVCMOS18>; 322 bias-disable; 323 }; 324 325 conf-cd { 326 groups = "sdio1_cd_0_grp"; 327 bias-high-impedance; 328 bias-pull-up; 329 slew-rate = <SLEW_RATE_SLOW>; 330 power-source = <IO_STANDARD_LVCMOS18>; 331 }; 332 333 mux-cd { 334 groups = "sdio1_cd_0_grp"; 335 function = "sdio1_cd"; 336 }; 337 338 mux { 339 groups = "sdio1_0_grp"; 340 function = "sdio1"; 341 }; 342 }; 343 }; 344 }; 345 fragment15 { 346 target = <&uart1>; 347 __overlay__ { 348 status = "okay"; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_uart1_default>; 351 }; 352 }; 353}; 354