1 /* 2 * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _IMX_NAND_BCB_H_ 8 #define _IMX_NAND_BCB_H_ 9 10 #define FCB_FINGERPRINT 0x20424346 /* 'FCB' */ 11 #define FCB_VERSION_1 0x01000000 12 #define FCB_FINGERPRINT_OFF 0x4 /* FCB fingerprint offset*/ 13 14 #define DBBT_FINGERPRINT 0x54424244 /* 'DBBT' */ 15 #define DBBT_VERSION_1 0x01000000 16 #define DBBT_FINGERPRINT_OFF 0x4 /* DBBT fingerprint offset*/ 17 18 struct dbbt_block { 19 u32 checksum; /* reserved on i.MX6 */ 20 u32 fingerprint; 21 u32 version; 22 u32 numberbb; /* reserved on i.MX6 */ 23 u32 dbbtpages; 24 }; 25 26 struct fcb_block { 27 u32 checksum; /* First fingerprint in first byte */ 28 u32 fingerprint; /* 2nd fingerprint at byte 4 */ 29 u32 version; /* 3rd fingerprint at byte 8 */ 30 u8 datasetup; 31 u8 datahold; 32 u8 addr_setup; 33 u8 dsample_time; 34 35 /* These are for application use only and not for ROM. */ 36 u8 nandtiming; 37 u8 rea; 38 u8 rloh; 39 u8 rhoh; 40 u32 pagesize; /* 2048 for 2K pages, 4096 for 4K pages */ 41 u32 oob_pagesize; /* 2112 for 2K pages, 4314 for 4K pages */ 42 u32 sectors; /* Number of 2K sections per block */ 43 u32 nr_nand; /* Total Number of NANDs - not used by ROM */ 44 u32 nr_die; /* Number of separate chips in this NAND */ 45 u32 celltype; /* MLC or SLC */ 46 u32 ecc_type; /* Type of ECC, can be one of BCH-0-20 */ 47 u32 ecc_nr; /* Number of bytes for Block0 - BCH */ 48 49 /* Block size in bytes for all blocks other than Block0 - BCH */ 50 u32 ecc_size; 51 u32 ecc_level; /* Ecc level for Block 0 - BCH */ 52 u32 meta_size; /* Metadata size - BCH */ 53 /* Number of blocks per page for ROM use - BCH */ 54 u32 nr_blocks; 55 u32 ecc_type_sdk; /* Type of ECC, can be one of BCH-0-20 */ 56 u32 ecc_nr_sdk; /* Number of bytes for Block0 - BCH */ 57 /* Block size in bytes for all blocks other than Block0 - BCH */ 58 u32 ecc_size_sdk; 59 u32 ecc_level_sdk; /* Ecc level for Block 0 - BCH */ 60 /* Number of blocks per page for SDK use - BCH */ 61 u32 nr_blocks_sdk; 62 u32 meta_size_sdk; /* Metadata size - BCH */ 63 u32 erase_th; /* To set into BCH_MODE register */ 64 65 /* 66 * 0: normal boot 67 * 1: to load patch starting next to FCB 68 */ 69 u32 bootpatch; 70 u32 patch_size; /* Size of patch in sectors */ 71 u32 fw1_start; /* Firmware image starts on this sector */ 72 u32 fw2_start; /* Secondary FW Image starting Sector */ 73 u32 fw1_pages; /* Number of sectors in firmware image */ 74 u32 fw2_pages; /* Number of sector in secondary FW image */ 75 u32 dbbt_start; /* Page address where dbbt search area begins */ 76 77 /* 78 * Byte in page data that have manufacturer marked bad block marker, 79 * this will be swapped with metadata[0] to complete page data. 80 */ 81 u32 bb_byte; 82 83 /* 84 * For BCH ECC sizes other than 8 and 16 the bad block marker does not 85 * start at 0th bit of bb_byte. This field is used to get to 86 * the start bit of bad block marker byte with in bb_byte 87 */ 88 u32 bb_start_bit; 89 90 /* 91 * FCB value that gives byte offset for 92 * bad block marker on physical NAND page 93 */ 94 u32 phy_offset; 95 u32 bchtype; 96 97 u32 readlatency; 98 u32 predelay; 99 u32 cedelay; 100 u32 postdelay; 101 u32 cmdaddpause; 102 u32 datapause; 103 u32 tmspeed; 104 u32 busytimeout; 105 106 /* the flag to enable (1)/disable(0) bi swap */ 107 u32 disbbm; 108 109 /* The swap position of main area in spare area */ 110 u32 spare_offset; 111 112 /* Actual for iMX7 only */ 113 u32 onfi_sync_enable; 114 u32 onfi_sync_speed; 115 u32 onfi_sync_nand_data; 116 u32 reserved2[6]; 117 u32 disbbm_search; 118 u32 disbbm_search_limit; 119 u32 reserved3[15]; 120 u32 read_retry_enable; 121 u32 reserved4[1]; 122 u32 fill_to_1024[183]; 123 }; 124 125 #endif /* _IMX_NAND_BCB_H_ */ 126