1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2017 Intel Corporation
4 */
5
6 #include <asm/global_data.h>
7 #include <asm/io.h>
8 #include <asm/arch/fpga_manager.h>
9 #include <asm/arch/misc.h>
10 #include <asm/arch/reset_manager.h>
11 #include <asm/arch/system_manager.h>
12 #include <common.h>
13 #include <errno.h>
14 #include <fdtdec.h>
15 #include <wait_bit.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 struct bridge_cfg {
20 int compat_id;
21 u32 mask_noc;
22 u32 mask_rstmgr;
23 };
24
25 static const struct bridge_cfg bridge_cfg_tbl[] = {
26 {
27 COMPAT_ALTERA_SOCFPGA_H2F_BRG,
28 ALT_SYSMGR_NOC_H2F_SET_MSK,
29 ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
30 },
31 {
32 COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
33 ALT_SYSMGR_NOC_LWH2F_SET_MSK,
34 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
35 },
36 {
37 COMPAT_ALTERA_SOCFPGA_F2H_BRG,
38 ALT_SYSMGR_NOC_F2H_SET_MSK,
39 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
40 },
41 {
42 COMPAT_ALTERA_SOCFPGA_F2SDR0,
43 ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
44 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
45 },
46 {
47 COMPAT_ALTERA_SOCFPGA_F2SDR1,
48 ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
49 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
50 },
51 {
52 COMPAT_ALTERA_SOCFPGA_F2SDR2,
53 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
54 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
55 },
56 };
57
58 /* Disable the watchdog (toggle reset to watchdog) */
socfpga_watchdog_disable(void)59 void socfpga_watchdog_disable(void)
60 {
61 /* assert reset for watchdog */
62 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
63 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
64 }
65
66 /* Release NOC ddr scheduler from reset */
socfpga_reset_deassert_noc_ddr_scheduler(void)67 void socfpga_reset_deassert_noc_ddr_scheduler(void)
68 {
69 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
70 ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
71 }
72
get_bridge_init_val(const void * blob,int compat_id)73 static int get_bridge_init_val(const void *blob, int compat_id)
74 {
75 int node;
76
77 node = fdtdec_next_compatible(blob, 0, compat_id);
78 if (node < 0)
79 return 0;
80
81 return fdtdec_get_uint(blob, node, "init-val", 0);
82 }
83
84 /* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
socfpga_reset_deassert_bridges_handoff(void)85 int socfpga_reset_deassert_bridges_handoff(void)
86 {
87 u32 mask_noc = 0, mask_rstmgr = 0;
88 int i;
89
90 for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
91 if (get_bridge_init_val(gd->fdt_blob,
92 bridge_cfg_tbl[i].compat_id)) {
93 mask_noc |= bridge_cfg_tbl[i].mask_noc;
94 mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
95 }
96 }
97
98 /* clear idle request to all bridges */
99 setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR,
100 mask_noc);
101
102 /* Release bridges from reset state per handoff value */
103 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
104 mask_rstmgr);
105
106 /* Poll until all idleack to 0, timeout at 1000ms */
107 return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
108 SYSMGR_A10_NOC_IDLEACK),
109 mask_noc, false, 1000, false);
110 }
111
112 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
socfpga_reset_deassert_osc1wd0(void)113 void socfpga_reset_deassert_osc1wd0(void)
114 {
115 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
116 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
117 }
118
119 /*
120 * Assert or de-assert SoCFPGA reset manager reset.
121 */
socfpga_per_reset(u32 reset,int set)122 void socfpga_per_reset(u32 reset, int set)
123 {
124 unsigned long reg;
125 u32 rstmgr_bank = RSTMGR_BANK(reset);
126
127 switch (rstmgr_bank) {
128 case 0:
129 reg = RSTMGR_A10_MPUMODRST;
130 break;
131 case 1:
132 reg = RSTMGR_A10_PER0MODRST;
133 break;
134 case 2:
135 reg = RSTMGR_A10_PER1MODRST;
136 break;
137 case 3:
138 reg = RSTMGR_A10_BRGMODRST;
139 break;
140 case 4:
141 reg = RSTMGR_A10_SYSMODRST;
142 break;
143
144 default:
145 return;
146 }
147
148 if (set)
149 setbits_le32(socfpga_get_rstmgr_addr() + reg,
150 1 << RSTMGR_RESET(reset));
151 else
152 clrbits_le32(socfpga_get_rstmgr_addr() + reg,
153 1 << RSTMGR_RESET(reset));
154 }
155
156 /*
157 * Assert reset on every peripheral but L4WD0.
158 * Watchdog must be kept intact to prevent glitches
159 * and/or hangs.
160 * For the Arria10, we disable all the peripherals except L4 watchdog0,
161 * L4 Timer 0, and ECC.
162 */
socfpga_per_reset_all(void)163 void socfpga_per_reset_all(void)
164 {
165 const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
166 (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
167 unsigned mask_ecc_ocp =
168 ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
169 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
170 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
171 ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
172 ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
173 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
174 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
175 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
176
177 /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
178 writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
179 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
180 ~mask_ecc_ocp);
181
182 /* Finally disable the ECC_OCP */
183 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
184 mask_ecc_ocp);
185 }
186
socfpga_bridges_reset(void)187 int socfpga_bridges_reset(void)
188 {
189 int ret;
190
191 /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
192 fpga2sdram) */
193 /* set idle request to all bridges */
194 writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
195 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
196 ALT_SYSMGR_NOC_F2H_SET_MSK |
197 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
198 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
199 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
200 socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_SET);
201
202 /* Enable the NOC timeout */
203 writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
204 socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
205
206 /* Poll until all idleack to 1 */
207 ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
208 SYSMGR_A10_NOC_IDLEACK),
209 ALT_SYSMGR_NOC_H2F_SET_MSK |
210 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
211 ALT_SYSMGR_NOC_F2H_SET_MSK |
212 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
213 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
214 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
215 true, 10000, false);
216 if (ret)
217 return ret;
218
219 /* Poll until all idlestatus to 1 */
220 ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
221 SYSMGR_A10_NOC_IDLESTATUS),
222 ALT_SYSMGR_NOC_H2F_SET_MSK |
223 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
224 ALT_SYSMGR_NOC_F2H_SET_MSK |
225 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
226 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
227 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
228 true, 10000, false);
229 if (ret)
230 return ret;
231
232 /* Put all bridges (except NOR DDR scheduler) into reset state */
233 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
234 (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
235 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
236 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
237 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
238 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
239 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
240
241 /* Disable NOC timeout */
242 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
243
244 return 0;
245 }
246