1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <asm/arch/clock_manager.h>
8 #include <asm/arch/system_manager.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <command.h>
12 #include <init.h>
13 #include <wait_bit.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
cm_wait_for_lock(u32 mask)17 void cm_wait_for_lock(u32 mask)
18 {
19 u32 inter_val;
20 u32 retry = 0;
21 do {
22 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
23 inter_val = readl(socfpga_get_clkmgr_addr() +
24 CLKMGR_INTER) & mask;
25 #else
26 inter_val = readl(socfpga_get_clkmgr_addr() +
27 CLKMGR_STAT) & mask;
28 #endif
29 /* Wait for stable lock */
30 if (inter_val == mask)
31 retry++;
32 else
33 retry = 0;
34 if (retry >= 10)
35 break;
36 } while (1);
37 }
38
39 /* function to poll in the fsm busy bit */
cm_wait_for_fsm(void)40 int cm_wait_for_fsm(void)
41 {
42 return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
43 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
44 false);
45 }
46
set_cpu_clk_info(void)47 int set_cpu_clk_info(void)
48 {
49 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
50 /* Calculate the clock frequencies required for drivers */
51 cm_get_l4_sp_clk_hz();
52 cm_get_mmc_controller_clk_hz();
53 #endif
54
55 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
56 gd->bd->bi_dsp_freq = 0;
57
58 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
59 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
60 #else
61 gd->bd->bi_ddr_freq = 0;
62 #endif
63
64 return 0;
65 }
66
67 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
cm_set_qspi_controller_clk_hz(u32 clk_hz)68 int cm_set_qspi_controller_clk_hz(u32 clk_hz)
69 {
70 u32 reg;
71 u32 clk_khz;
72
73 /*
74 * Store QSPI ref clock and set into sysmgr boot register.
75 * Only clock freq in kHz degree is accepted due to limited bits[27:0]
76 * is reserved for storing the QSPI clock freq into boot scratch cold0
77 * register.
78 */
79 if (clk_hz < 1000)
80 return -EINVAL;
81
82 clk_khz = clk_hz / 1000;
83 printf("QSPI: Reference clock at %d kHz\n", clk_khz);
84
85 reg = (readl(socfpga_get_sysmgr_addr() +
86 SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
87 ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
88
89 writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
90 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
91
92 return 0;
93 }
94
cm_get_qspi_controller_clk_hz(void)95 unsigned int cm_get_qspi_controller_clk_hz(void)
96 {
97 return (readl(socfpga_get_sysmgr_addr() +
98 SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
99 SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
100 }
101 #endif
102
103 #ifndef CONFIG_SPL_BUILD
do_showclocks(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])104 static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
105 char *const argv[])
106 {
107 cm_print_clock_quick_summary();
108 return 0;
109 }
110
111 U_BOOT_CMD(
112 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
113 "display clocks",
114 ""
115 );
116 #endif
117