1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4  *
5  */
6 
7 #include <common.h>
8 #include <asm/armv8/mmu.h>
9 #include <asm/global_data.h>
10 
11 DECLARE_GLOBAL_DATA_PTR;
12 
13 static struct mm_region socfpga_stratix10_mem_map[] = {
14 	{
15 		/* MEM 2GB*/
16 		.virt	= 0x0UL,
17 		.phys	= 0x0UL,
18 		.size	= 0x80000000UL,
19 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
20 				PTE_BLOCK_INNER_SHARE,
21 	}, {
22 		/* FPGA 1.5GB */
23 		.virt	= 0x80000000UL,
24 		.phys	= 0x80000000UL,
25 		.size	= 0x60000000UL,
26 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 				PTE_BLOCK_NON_SHARE |
28 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
29 	}, {
30 		/* DEVICE 142MB */
31 		.virt	= 0xF7000000UL,
32 		.phys	= 0xF7000000UL,
33 		.size	= 0x08E00000UL,
34 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 				PTE_BLOCK_NON_SHARE |
36 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
37 	}, {
38 		/* OCRAM 1MB but available 256KB */
39 		.virt	= 0xFFE00000UL,
40 		.phys	= 0xFFE00000UL,
41 		.size	= 0x00100000UL,
42 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
43 				PTE_BLOCK_INNER_SHARE,
44 	}, {
45 		/* DEVICE 32KB */
46 		.virt	= 0xFFFC0000UL,
47 		.phys	= 0xFFFC0000UL,
48 		.size	= 0x00008000UL,
49 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 				PTE_BLOCK_NON_SHARE |
51 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
52 	}, {
53 		/* MEM 124GB */
54 		.virt	= 0x0100000000UL,
55 		.phys	= 0x0100000000UL,
56 		.size	= 0x1F00000000UL,
57 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
58 				PTE_BLOCK_INNER_SHARE,
59 	}, {
60 		/* DEVICE 4GB */
61 		.virt	= 0x2000000000UL,
62 		.phys	= 0x2000000000UL,
63 		.size	= 0x0100000000UL,
64 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65 				PTE_BLOCK_NON_SHARE |
66 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
67 	}, {
68 		/* List terminator */
69 	},
70 };
71 
72 struct mm_region *mem_map = socfpga_stratix10_mem_map;
73