1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2017 Andes Technology Corporation
4  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5  */
6 
7 #ifndef _ASM_RISCV_CACHE_H
8 #define _ASM_RISCV_CACHE_H
9 
10 /* cache */
11 void	cache_flush(void);
12 
13 /*
14  * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
15  * We use that value for aligning DMA buffers unless the board config has
16  * specified an alternate cache line size.
17  */
18 #ifdef CONFIG_SYS_CACHELINE_SIZE
19 #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
20 #else
21 #define ARCH_DMA_MINALIGN	32
22 #endif
23 
24 #endif /* _ASM_RISCV_CACHE_H */
25