1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some init for sunxi platform.
10 */
11
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <init.h>
15 #include <log.h>
16 #include <mmc.h>
17 #include <i2c.h>
18 #include <serial.h>
19 #include <spl.h>
20 #include <asm/cache.h>
21 #include <asm/gpio.h>
22 #include <asm/io.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/spl.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/timer.h>
28 #include <asm/arch/tzpc.h>
29 #include <asm/arch/mmc.h>
30
31 #include <linux/compiler.h>
32
33 struct fel_stash {
34 uint32_t sp;
35 uint32_t lr;
36 uint32_t cpsr;
37 uint32_t sctlr;
38 uint32_t vbar;
39 uint32_t cr;
40 };
41
42 struct fel_stash fel_stash __section(".data");
43
44 #ifdef CONFIG_ARM64
45 #include <asm/armv8/mmu.h>
46
47 static struct mm_region sunxi_mem_map[] = {
48 {
49 /* SRAM, MMIO regions */
50 .virt = 0x0UL,
51 .phys = 0x0UL,
52 .size = 0x40000000UL,
53 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
54 PTE_BLOCK_NON_SHARE
55 }, {
56 /* RAM */
57 .virt = 0x40000000UL,
58 .phys = 0x40000000UL,
59 .size = 0xC0000000UL,
60 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
61 PTE_BLOCK_INNER_SHARE
62 }, {
63 /* List terminator */
64 0,
65 }
66 };
67 struct mm_region *mem_map = sunxi_mem_map;
68 #endif
69
gpio_init(void)70 static int gpio_init(void)
71 {
72 __maybe_unused uint val;
73 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
74 #if defined(CONFIG_MACH_SUN4I) || \
75 defined(CONFIG_MACH_SUN7I) || \
76 defined(CONFIG_MACH_SUN8I_R40)
77 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
78 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
79 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
80 #endif
81 #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
82 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
83 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
84 #else
85 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
86 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
87 #endif
88 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
89 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
90 defined(CONFIG_MACH_SUN7I) || \
91 defined(CONFIG_MACH_SUN8I_R40))
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
94 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
95 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
97 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
98 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
99 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
102 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
103 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
104 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
106 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
107 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
108 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
110 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
111 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
114 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
115 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
118 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
119 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
122 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
123 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
124 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
125 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
126 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
127 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
130 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
131 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
134 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
135 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
136 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
137 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
138 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
139 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
140 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
141 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
142 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
143 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
144 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
145 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
146 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
147 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
148 !defined(CONFIG_MACH_SUN8I_R40)
149 sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
150 sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
151 sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
152 #else
153 #error Unsupported console port number. Please fix pin mux settings in board.c
154 #endif
155
156 #ifdef CONFIG_SUN50I_GEN_H6
157 /* Update PIO power bias configuration by copy hardware detected value */
158 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
159 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
160 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
161 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
162 #endif
163
164 return 0;
165 }
166
167 #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
spl_board_load_image(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)168 static int spl_board_load_image(struct spl_image_info *spl_image,
169 struct spl_boot_device *bootdev)
170 {
171 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
172 return_to_fel(fel_stash.sp, fel_stash.lr);
173
174 return 0;
175 }
176 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
177 #endif
178
s_init(void)179 void s_init(void)
180 {
181 /*
182 * Undocumented magic taken from boot0, without this DRAM
183 * access gets messed up (seems cache related).
184 * The boot0 sources describe this as: "config ema for cache sram"
185 */
186 #if defined CONFIG_MACH_SUN6I
187 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
188 #elif defined CONFIG_MACH_SUN8I
189 __maybe_unused uint version;
190
191 /* Unlock sram version info reg, read it, relock */
192 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
193 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
194 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
195
196 /*
197 * Ideally this would be a switch case, but we do not know exactly
198 * which versions there are and which version needs which settings,
199 * so reproduce the per SoC code from the BSP.
200 */
201 #if defined CONFIG_MACH_SUN8I_A23
202 if (version == 0x1650)
203 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
204 else /* 0x1661 ? */
205 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
206 #elif defined CONFIG_MACH_SUN8I_A33
207 if (version != 0x1667)
208 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
209 #endif
210 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
211 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
212 #endif
213
214 #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
215 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
216 asm volatile(
217 "mrc p15, 0, r0, c1, c0, 1\n"
218 "orr r0, r0, #1 << 6\n"
219 "mcr p15, 0, r0, c1, c0, 1\n"
220 ::: "r0");
221 #endif
222 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
223 /* Enable non-secure access to some peripherals */
224 tzpc_init();
225 #endif
226
227 clock_init();
228 timer_init();
229 gpio_init();
230 #if !CONFIG_IS_ENABLED(DM_I2C)
231 i2c_init_board();
232 #endif
233 eth_init_board();
234 }
235
236 #define SUNXI_INVALID_BOOT_SOURCE -1
237
sunxi_get_boot_source(void)238 static int sunxi_get_boot_source(void)
239 {
240 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
241 return SUNXI_INVALID_BOOT_SOURCE;
242
243 return readb(SPL_ADDR + 0x28);
244 }
245
246 /* The sunxi internal brom will try to loader external bootloader
247 * from mmc0, nand flash, mmc2.
248 */
sunxi_get_boot_device(void)249 uint32_t sunxi_get_boot_device(void)
250 {
251 int boot_source = sunxi_get_boot_source();
252
253 /*
254 * When booting from the SD card or NAND memory, the "eGON.BT0"
255 * signature is expected to be found in memory at the address 0x0004
256 * (see the "mksunxiboot" tool, which generates this header).
257 *
258 * When booting in the FEL mode over USB, this signature is patched in
259 * memory and replaced with something else by the 'fel' tool. This other
260 * signature is selected in such a way, that it can't be present in a
261 * valid bootable SD card image (because the BROM would refuse to
262 * execute the SPL in this case).
263 *
264 * This checks for the signature and if it is not found returns to
265 * the FEL code in the BROM to wait and receive the main u-boot
266 * binary over USB. If it is found, it determines where SPL was
267 * read from.
268 */
269 switch (boot_source) {
270 case SUNXI_INVALID_BOOT_SOURCE:
271 return BOOT_DEVICE_BOARD;
272 case SUNXI_BOOTED_FROM_MMC0:
273 case SUNXI_BOOTED_FROM_MMC0_HIGH:
274 return BOOT_DEVICE_MMC1;
275 case SUNXI_BOOTED_FROM_NAND:
276 return BOOT_DEVICE_NAND;
277 case SUNXI_BOOTED_FROM_MMC2:
278 case SUNXI_BOOTED_FROM_MMC2_HIGH:
279 return BOOT_DEVICE_MMC2;
280 case SUNXI_BOOTED_FROM_SPI:
281 return BOOT_DEVICE_SPI;
282 }
283
284 panic("Unknown boot source %d\n", boot_source);
285 return -1; /* Never reached */
286 }
287
288 #ifdef CONFIG_SPL_BUILD
sunxi_get_spl_size(void)289 static u32 sunxi_get_spl_size(void)
290 {
291 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
292 return 0;
293
294 return readl(SPL_ADDR + 0x10);
295 }
296
297 /*
298 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
299 * an eMMC device. The boot source has bit 4 set in the latter case.
300 * By adding 120KB to the normal offset when booting from a "high" location
301 * we can support both cases.
302 * Also U-Boot proper is located at least 32KB after the SPL, but will
303 * immediately follow the SPL if that is bigger than that.
304 */
spl_mmc_get_uboot_raw_sector(struct mmc * mmc,unsigned long raw_sect)305 unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
306 unsigned long raw_sect)
307 {
308 unsigned long spl_size = sunxi_get_spl_size();
309 unsigned long sector;
310
311 sector = max(raw_sect, spl_size / 512);
312
313 switch (sunxi_get_boot_source()) {
314 case SUNXI_BOOTED_FROM_MMC0_HIGH:
315 case SUNXI_BOOTED_FROM_MMC2_HIGH:
316 sector += (128 - 8) * 2;
317 break;
318 }
319
320 return sector;
321 }
322
spl_boot_device(void)323 u32 spl_boot_device(void)
324 {
325 return sunxi_get_boot_device();
326 }
327
board_init_f(ulong dummy)328 void board_init_f(ulong dummy)
329 {
330 spl_init();
331 preloader_console_init();
332
333 #ifdef CONFIG_SPL_I2C_SUPPORT
334 /* Needed early by sunxi_board_init if PMU is enabled */
335 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
336 #endif
337 sunxi_board_init();
338 }
339 #endif
340
reset_cpu(void)341 void reset_cpu(void)
342 {
343 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
344 static const struct sunxi_wdog *wdog =
345 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
346
347 /* Set the watchdog for its shortest interval (.5s) and wait */
348 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
349 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
350
351 while (1) {
352 /* sun5i sometimes gets stuck without this */
353 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
354 }
355 #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
356 #if defined(CONFIG_MACH_SUN50I_H6)
357 /* WDOG is broken for some H6 rev. use the R_WDOG instead */
358 static const struct sunxi_wdog *wdog =
359 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
360 #else
361 static const struct sunxi_wdog *wdog =
362 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
363 #endif
364 /* Set the watchdog for its shortest interval (.5s) and wait */
365 writel(WDT_CFG_RESET, &wdog->cfg);
366 writel(WDT_MODE_EN, &wdog->mode);
367 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
368 while (1) { }
369 #endif
370 }
371
372 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
enable_caches(void)373 void enable_caches(void)
374 {
375 /* Enable D-cache. I-cache is already enabled in start.S */
376 dcache_enable();
377 }
378 #endif
379