1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 */
6
7 #ifndef __PINCTRL_UNIPHIER_H__
8 #define __PINCTRL_UNIPHIER_H__
9
10 #include <linux/bitops.h>
11 #include <linux/bug.h>
12 #include <linux/build_bug.h>
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15
16 /* drive strength control register number */
17 #define UNIPHIER_PIN_DRVCTRL_SHIFT 0
18 #define UNIPHIER_PIN_DRVCTRL_BITS 9
19 #define UNIPHIER_PIN_DRVCTRL_MASK ((1U << (UNIPHIER_PIN_DRVCTRL_BITS)) \
20 - 1)
21
22 /* drive control type */
23 #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
24 (UNIPHIER_PIN_DRVCTRL_BITS))
25 #define UNIPHIER_PIN_DRV_TYPE_BITS 2
26 #define UNIPHIER_PIN_DRV_TYPE_MASK ((1U << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
27 - 1)
28
29 /* drive control type */
30 enum uniphier_pin_drv_type {
31 UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
32 UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
33 UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
34 };
35
36 #define UNIPHIER_PIN_DRVCTRL(x) \
37 (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
38 #define UNIPHIER_PIN_DRV_TYPE(x) \
39 (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
40
41 #define UNIPHIER_PIN_ATTR_PACKED(drvctrl, drv_type) \
42 UNIPHIER_PIN_DRVCTRL(drvctrl) | \
43 UNIPHIER_PIN_DRV_TYPE(drv_type)
44
uniphier_pin_get_drvctrl(unsigned int data)45 static inline unsigned int uniphier_pin_get_drvctrl(unsigned int data)
46 {
47 return (data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & UNIPHIER_PIN_DRVCTRL_MASK;
48 }
49
uniphier_pin_get_drv_type(unsigned int data)50 static inline unsigned int uniphier_pin_get_drv_type(unsigned int data)
51 {
52 return (data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
53 UNIPHIER_PIN_DRV_TYPE_MASK;
54 }
55
56 /**
57 * struct uniphier_pinctrl_pin - pin data for UniPhier SoC
58 *
59 * @number: pin number
60 * @data: additional per-pin data
61 */
62 struct uniphier_pinctrl_pin {
63 unsigned number;
64 const char *name;
65 unsigned int data;
66 };
67
68 /**
69 * struct uniphier_pinctrl_group - pin group data for UniPhier SoC
70 *
71 * @name: pin group name
72 * @pins: array of pins that belong to the group
73 * @num_pins: number of pins in the group
74 * @muxvals: array of values to be set to pinmux registers
75 */
76 struct uniphier_pinctrl_group {
77 const char *name;
78 const unsigned *pins;
79 unsigned num_pins;
80 const int *muxvals;
81 };
82
83 /**
84 * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller
85 *
86 * @pins: array of pin data
87 * @pins_count: number of pin data
88 * @groups: array of pin group data
89 * @groups_count: number of pin group data
90 * @functions: array of pinmux function names
91 * @functions_count: number of pinmux functions
92 * @mux_bits: bit width of each pinmux register
93 * @reg_stride: stride of pinmux register address
94 * @caps: SoC-specific capability flag
95 */
96 struct uniphier_pinctrl_socdata {
97 const struct uniphier_pinctrl_pin *pins;
98 int pins_count;
99 const struct uniphier_pinctrl_group *groups;
100 int groups_count;
101 const char * const *functions;
102 int functions_count;
103 unsigned caps;
104 #define UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE BIT(3)
105 #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2)
106 #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1)
107 #define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
108 };
109
110 #define UNIPHIER_PINCTRL_PIN(a, b, c, d) \
111 { \
112 .number = a, \
113 .name = b, \
114 .data = UNIPHIER_PIN_ATTR_PACKED(c, d), \
115 }
116
117 #define __UNIPHIER_PINCTRL_GROUP(grp) \
118 { \
119 .name = #grp, \
120 .pins = grp##_pins, \
121 .num_pins = ARRAY_SIZE(grp##_pins), \
122 .muxvals = grp##_muxvals + \
123 BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
124 ARRAY_SIZE(grp##_muxvals)), \
125 }
126
127 #define __UNIPHIER_PINMUX_FUNCTION(func) #func
128
129 #ifdef CONFIG_SPL_BUILD
130 /*
131 * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
132 * suppressing "defined but not used" warnings.
133 */
134 #define UNIPHIER_PINCTRL_GROUP(grp) \
135 { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
136 #define UNIPHIER_PINMUX_FUNCTION(func) NULL
137 #else
138 #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp)
139 #define UNIPHIER_PINMUX_FUNCTION(func) __UNIPHIER_PINMUX_FUNCTION(func)
140 #endif
141
142 #define UNIPHIER_PINCTRL_GROUP_SPL(grp) __UNIPHIER_PINCTRL_GROUP(grp)
143 #define UNIPHIER_PINMUX_FUNCTION_SPL(func) __UNIPHIER_PINMUX_FUNCTION(func)
144
145 /**
146 * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver
147 *
148 * @base: base address of the pinctrl device
149 * @socdata: SoC specific data
150 */
151 struct uniphier_pinctrl_priv {
152 void __iomem *base;
153 struct uniphier_pinctrl_socdata *socdata;
154 };
155
156 extern const struct pinctrl_ops uniphier_pinctrl_ops;
157
158 int uniphier_pinctrl_probe(struct udevice *dev,
159 struct uniphier_pinctrl_socdata *socdata);
160
161 #endif /* __PINCTRL_UNIPHIER_H__ */
162