1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012-2013, Xilinx, Michal Simek 4 * 5 * (C) Copyright 2012 6 * Joe Hershberger <joe.hershberger@ni.com> 7 */ 8 9 #ifndef _ZYNQPL_H_ 10 #define _ZYNQPL_H_ 11 12 #include <xilinx.h> 13 14 #ifdef CONFIG_CMD_ZYNQ_AES 15 int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen, 16 u8 bstype); 17 #endif 18 19 extern struct xilinx_fpga_op zynq_op; 20 21 #define XILINX_ZYNQ_XC7Z007S 0x3 22 #define XILINX_ZYNQ_XC7Z010 0x2 23 #define XILINX_ZYNQ_XC7Z012S 0x1c 24 #define XILINX_ZYNQ_XC7Z014S 0x8 25 #define XILINX_ZYNQ_XC7Z015 0x1b 26 #define XILINX_ZYNQ_XC7Z020 0x7 27 #define XILINX_ZYNQ_XC7Z030 0xc 28 #define XILINX_ZYNQ_XC7Z035 0x12 29 #define XILINX_ZYNQ_XC7Z045 0x11 30 #define XILINX_ZYNQ_XC7Z100 0x16 31 32 /* Device Image Sizes */ 33 #define XILINX_XC7Z007S_SIZE 16669920/8 34 #define XILINX_XC7Z010_SIZE 16669920/8 35 #define XILINX_XC7Z012S_SIZE 28085344/8 36 #define XILINX_XC7Z014S_SIZE 32364512/8 37 #define XILINX_XC7Z015_SIZE 28085344/8 38 #define XILINX_XC7Z020_SIZE 32364512/8 39 #define XILINX_XC7Z030_SIZE 47839328/8 40 #define XILINX_XC7Z035_SIZE 106571232/8 41 #define XILINX_XC7Z045_SIZE 106571232/8 42 #define XILINX_XC7Z100_SIZE 139330784/8 43 44 /* Device Names */ 45 #define XILINX_XC7Z007S_NAME "7z007s" 46 #define XILINX_XC7Z010_NAME "7z010" 47 #define XILINX_XC7Z012S_NAME "7z012s" 48 #define XILINX_XC7Z014S_NAME "7z014s" 49 #define XILINX_XC7Z015_NAME "7z015" 50 #define XILINX_XC7Z020_NAME "7z020" 51 #define XILINX_XC7Z030_NAME "7z030" 52 #define XILINX_XC7Z035_NAME "7z035" 53 #define XILINX_XC7Z045_NAME "7z045" 54 #define XILINX_XC7Z100_NAME "7z100" 55 56 #if defined(CONFIG_FPGA) 57 #define ZYNQ_DESC(name) { \ 58 .idcode = XILINX_ZYNQ_XC##name, \ 59 .fpga_size = XILINX_XC##name##_SIZE, \ 60 .devicename = XILINX_XC##name##_NAME \ 61 } 62 #else 63 #define ZYNQ_DESC(name) { \ 64 .idcode = XILINX_ZYNQ_XC##name, \ 65 .devicename = XILINX_XC##name##_NAME \ 66 } 67 #endif 68 69 #endif /* _ZYNQPL_H_ */ 70