1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Cortina CS4315/CS4340 10G PHY drivers
4 *
5 * Copyright 2014 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
7 *
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <linux/ctype.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/err.h>
18 #include <phy.h>
19 #include <cortina.h>
20 #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
21 #include <nand.h>
22 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
23 #include <spi_flash.h>
24 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
25 #include <mmc.h>
26 #endif
27
28 #ifndef CONFIG_PHYLIB_10G
29 #error The Cortina PHY needs 10G support
30 #endif
31
32 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
33 struct cortina_reg_config cortina_reg_cfg[] = {
34 /* CS4315_enable_sr_mode */
35 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
36 {VILLA_MSEQ_OPTIONS, 0xf},
37 {VILLA_MSEQ_PC, 0x0},
38 {VILLA_MSEQ_BANKSELECT, 0x4},
39 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
40 {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
41 {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
42 {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
43 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
44 {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
45 {VILLA_MSEQ_ENABLE_MSB, 0x0000},
46 {VILLA_MSEQ_SPARE21_LSB, 0x6},
47 {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
48 {VILLA_MSEQ_SPARE12_MSB, 0x0000},
49 /*
50 * to invert the receiver path, uncomment the next line
51 * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
52 *
53 * SPARE2_LSB is used to configure the device while in sr mode to
54 * enable power savings and to use the optical module LOS signal.
55 * in power savings mode, the internal prbs checker can not be used.
56 * if the optical module LOS signal is used as an input to the micro
57 * code, then the micro code will wait until the optical module
58 * LOS = 0 before turning on the adaptive equalizer.
59 * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
60 * while setting bit 0 to 0 disables power savings mode.
61 * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
62 * optical module LOS signal while setting bit 2 to 1 configures the
63 * device so that it will ignore the optical module LOS SPARE2_LSB = 0
64 */
65
66 /* enable power savings, ignore optical module LOS */
67 {VILLA_MSEQ_SPARE2_LSB, 0x5},
68
69 {VILLA_MSEQ_SPARE7_LSB, 0x1e},
70 {VILLA_MSEQ_BANKSELECT, 0x4},
71 {VILLA_MSEQ_SPARE9_LSB, 0x2},
72 {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
73 {VILLA_MSEQ_SPARE3_MSB, 0x2006},
74 {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
75 {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
76 {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
77 {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
78 {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
79 {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
80 {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
81 {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
82 {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
83 {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
84 {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
85 {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
86 {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
87 {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
88 {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
89 {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
90 {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
91 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
92 {VILLA_MSEQ_OPTIONS, 0x7},
93
94 /* set up min value for ffe1 */
95 {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
96 {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
97
98 /* CS4315_sr_rx_pre_eq_set_4in */
99 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
100 {VILLA_MSEQ_OPTIONS, 0xf},
101 {VILLA_MSEQ_BANKSELECT, 0x4},
102 {VILLA_MSEQ_PC, 0x0},
103
104 /* for lengths from 3.5 to 4.5inches */
105 {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
106 {VILLA_MSEQ_SPARE25_LSB, 0x0306},
107 {VILLA_MSEQ_SPARE21_LSB, 0x2},
108 {VILLA_MSEQ_SPARE23_LSB, 0x2},
109 {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
110
111 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
112 {VILLA_MSEQ_OPTIONS, 0x7},
113
114 /* CS4315_rx_drive_4inch */
115 /* for length 4inches */
116 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
117 {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
118 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
119
120 /* CS4315_tx_drive_4inch */
121 /* for length 4inches */
122 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
123 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
124 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
125 };
126
cs4340_upload_firmware(struct phy_device * phydev)127 void cs4340_upload_firmware(struct phy_device *phydev)
128 {
129 char line_temp[0x50] = {0};
130 char reg_addr[0x50] = {0};
131 char reg_data[0x50] = {0};
132 int i, line_cnt = 0, column_cnt = 0;
133 struct cortina_reg_config fw_temp;
134 char *addr = NULL;
135
136 #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
137 defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
138
139 addr = (char *)CONFIG_CORTINA_FW_ADDR;
140 #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
141 int ret;
142 size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
143
144 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
145 ret = nand_read(get_nand_dev_by_index(0),
146 (loff_t)CONFIG_CORTINA_FW_ADDR,
147 &fw_length, (u_char *)addr);
148 if (ret == -EUCLEAN) {
149 printf("NAND read of Cortina firmware at 0x%x failed %d\n",
150 CONFIG_CORTINA_FW_ADDR, ret);
151 }
152 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
153 int ret;
154 struct spi_flash *ucode_flash;
155
156 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
157 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
158 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
159 if (!ucode_flash) {
160 puts("SF: probe for Cortina ucode failed\n");
161 } else {
162 ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
163 CONFIG_CORTINA_FW_LENGTH, addr);
164 if (ret)
165 puts("SF: read for Cortina ucode failed\n");
166 spi_flash_free(ucode_flash);
167 }
168 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
169 int dev = CONFIG_SYS_MMC_ENV_DEV;
170 u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
171 u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
172 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
173
174 if (!mmc) {
175 puts("Failed to find MMC device for Cortina ucode\n");
176 } else {
177 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
178 printf("MMC read: dev # %u, block # %u, count %u ...\n",
179 dev, blk, cnt);
180 mmc_init(mmc);
181 #ifdef CONFIG_BLK
182 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
183 addr);
184 #else
185 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
186 addr);
187 #endif
188 }
189 #endif
190
191 while (*addr != 'Q') {
192 i = 0;
193
194 while (*addr != 0x0a) {
195 line_temp[i++] = *addr++;
196 if (0x50 < i) {
197 printf("Not found Cortina PHY ucode at 0x%p\n",
198 (char *)CONFIG_CORTINA_FW_ADDR);
199 return;
200 }
201 }
202
203 addr++; /* skip '\n' */
204 line_cnt++;
205 column_cnt = i;
206 line_temp[column_cnt] = '\0';
207
208 if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
209 return;
210
211 for (i = 0; i < column_cnt; i++) {
212 if (isspace(line_temp[i++]))
213 break;
214 }
215
216 memcpy(reg_addr, line_temp, i);
217 memcpy(reg_data, &line_temp[i], column_cnt - i);
218 strim(reg_addr);
219 strim(reg_data);
220 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
221 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
222 0xffff;
223 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
224 }
225 }
226 #endif
227
cs4340_phy_init(struct phy_device * phydev)228 int cs4340_phy_init(struct phy_device *phydev)
229 {
230 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
231 int timeout = 100; /* 100ms */
232 #endif
233 int reg_value;
234
235 /*
236 * Cortina phy has provision to store
237 * phy firmware in attached dedicated EEPROM.
238 * Boards designed with EEPROM attached to Cortina
239 * does not require FW upload.
240 */
241 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
242 /* step1: BIST test */
243 phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
244 phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
245 phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
246 while (--timeout) {
247 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
248 if (reg_value & mseq_edc_bist_done) {
249 if (0 == (reg_value & mseq_edc_bist_fail))
250 break;
251 }
252 udelay(1000);
253 }
254
255 if (!timeout) {
256 printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
257 return -1;
258 }
259
260 /* setp2: upload ucode */
261 cs4340_upload_firmware(phydev);
262 #endif
263 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
264 if (reg_value) {
265 debug("%s checksum status failed.\n", __func__);
266 return -1;
267 }
268
269 return 0;
270 }
271
cs4340_config(struct phy_device * phydev)272 int cs4340_config(struct phy_device *phydev)
273 {
274 cs4340_phy_init(phydev);
275 return 0;
276 }
277
cs4340_probe(struct phy_device * phydev)278 int cs4340_probe(struct phy_device *phydev)
279 {
280 phydev->flags = PHY_FLAG_BROKEN_RESET;
281 return 0;
282 }
283
cs4340_startup(struct phy_device * phydev)284 int cs4340_startup(struct phy_device *phydev)
285 {
286 phydev->link = 1;
287
288 /* For now just lie and say it's 10G all the time */
289 phydev->speed = SPEED_10000;
290 phydev->duplex = DUPLEX_FULL;
291 return 0;
292 }
293
cs4223_phy_init(struct phy_device * phydev)294 int cs4223_phy_init(struct phy_device *phydev)
295 {
296 int reg_value;
297
298 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
299 if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
300 printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
301 return -ENOSYS;
302 }
303
304 return 0;
305 }
306
cs4223_config(struct phy_device * phydev)307 int cs4223_config(struct phy_device *phydev)
308 {
309 return cs4223_phy_init(phydev);
310 }
311
cs4223_probe(struct phy_device * phydev)312 int cs4223_probe(struct phy_device *phydev)
313 {
314 phydev->flags = PHY_FLAG_BROKEN_RESET;
315 return 0;
316 }
317
cs4223_startup(struct phy_device * phydev)318 int cs4223_startup(struct phy_device *phydev)
319 {
320 phydev->link = 1;
321 phydev->speed = SPEED_10000;
322 phydev->duplex = DUPLEX_FULL;
323 return 0;
324 }
325
326 struct phy_driver cs4340_driver = {
327 .name = "Cortina CS4315/CS4340",
328 .uid = PHY_UID_CS4340,
329 .mask = 0xfffffff0,
330 .features = PHY_10G_FEATURES,
331 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
332 MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
333 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
334 .config = &cs4340_config,
335 .probe = &cs4340_probe,
336 .startup = &cs4340_startup,
337 .shutdown = &gen10g_shutdown,
338 };
339
340 struct phy_driver cs4223_driver = {
341 .name = "Cortina CS4223",
342 .uid = PHY_UID_CS4223,
343 .mask = 0x0ffff00f,
344 .features = PHY_10G_FEATURES,
345 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
346 MDIO_DEVS_AN),
347 .config = &cs4223_config,
348 .probe = &cs4223_probe,
349 .startup = &cs4223_startup,
350 .shutdown = &gen10g_shutdown,
351 };
352
phy_cortina_init(void)353 int phy_cortina_init(void)
354 {
355 phy_register(&cs4340_driver);
356 phy_register(&cs4223_driver);
357 return 0;
358 }
359
get_phy_id(struct mii_dev * bus,int addr,int devad,u32 * phy_id)360 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
361 {
362 int phy_reg;
363
364 /* Cortina PHY has non-standard offset of PHY ID registers */
365 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
366 if (phy_reg < 0)
367 return -EIO;
368 *phy_id = (phy_reg & 0xffff) << 16;
369
370 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
371 if (phy_reg < 0)
372 return -EIO;
373 *phy_id |= (phy_reg & 0xffff);
374
375 if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
376 return 0;
377
378 /*
379 * If Cortina PHY not detected,
380 * try generic way to find PHY ID registers
381 */
382 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
383 if (phy_reg < 0)
384 return -EIO;
385 *phy_id = (phy_reg & 0xffff) << 16;
386
387 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
388 if (phy_reg < 0)
389 return -EIO;
390 *phy_id |= (phy_reg & 0xffff);
391
392 return 0;
393 }
394