1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP ls1028AQDS device tree source
4 *
5 * Copyright 2019 NXP
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-ls1028a.dtsi"
12
13/ {
14	model = "NXP Layerscape 1028a QDS Board";
15	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
16	aliases {
17		spi0 = &fspi;
18		spi1 = &dspi0;
19		spi2 = &dspi1;
20		spi3 = &dspi2;
21	};
22
23};
24
25&dspi0 {
26	bus-num = <0>;
27	status = "okay";
28
29	dflash0: sst25wf040b {
30		#address-cells = <1>;
31		#size-cells = <1>;
32		compatible = "spi-flash";
33		spi-max-frequency = <3000000>;
34		spi-cpol;
35		spi-cpha;
36		reg = <0>;
37	};
38
39	dflash1: en25s64 {
40		#address-cells = <1>;
41		#size-cells = <1>;
42		compatible = "spi-flash";
43		spi-max-frequency = <3000000>;
44		spi-cpol;
45		spi-cpha;
46		reg = <1>;
47	};
48	dflash2: n25q128a {
49		#address-cells = <1>;
50		#size-cells = <1>;
51		compatible = "spi-flash";
52		spi-max-frequency = <3000000>;
53		spi-cpol;
54		spi-cpha;
55		reg = <2>;
56	};
57};
58
59&dspi1 {
60	bus-num = <0>;
61	status = "okay";
62
63	dflash3: sst25wf040b {
64		#address-cells = <1>;
65		#size-cells = <1>;
66		compatible = "spi-flash";
67		spi-max-frequency = <3000000>;
68		spi-cpol;
69		spi-cpha;
70		reg = <0>;
71	};
72
73	dflash4: en25s64 {
74		#address-cells = <1>;
75		#size-cells = <1>;
76		compatible = "spi-flash";
77		spi-max-frequency = <3000000>;
78		spi-cpol;
79		spi-cpha;
80		reg = <1>;
81	};
82	dflash5: n25q128a {
83		#address-cells = <1>;
84		#size-cells = <1>;
85		compatible = "spi-flash";
86		spi-max-frequency = <3000000>;
87		spi-cpol;
88		spi-cpha;
89		reg = <2>;
90	};
91};
92
93&dspi2 {
94	bus-num = <0>;
95	status = "okay";
96
97	dflash8: en25s64 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		compatible = "spi-flash";
101		spi-max-frequency = <3000000>;
102		spi-cpol;
103		spi-cpha;
104		reg = <0>;
105	};
106};
107
108&esdhc0 {
109	status = "okay";
110};
111
112&esdhc1 {
113	status = "okay";
114
115};
116
117&fspi {
118	status = "okay";
119
120	mt35xu02g0: flash@0 {
121		#address-cells = <1>;
122		#size-cells = <1>;
123		compatible = "jedec,spi-nor";
124		spi-max-frequency = <50000000>;
125		reg = <0>;
126		spi-rx-bus-width = <8>;
127		spi-tx-bus-width = <1>;
128	};
129};
130
131&i2c0 {
132	status = "okay";
133	u-boot,dm-pre-reloc;
134
135	fpga@66 {
136		#address-cells = <1>;
137		#size-cells = <0>;
138		compatible = "simple-mfd";
139		reg = <0x66>;
140
141		mux-mdio@54 {
142			#address-cells = <1>;
143			#size-cells = <0>;
144			compatible = "mdio-mux-i2creg";
145			reg = <0x54>;
146			#mux-control-cells = <1>;
147			mux-reg-masks = <0x54 0xf0>;
148			mdio-parent-bus = <&mdio0>;
149
150			/* on-board MDIO with a single RGMII PHY */
151			mdio@00 {
152				#address-cells = <1>;
153				#size-cells = <0>;
154				reg = <0x00>;
155
156				qds_phy0: phy@5 {
157					reg = <5>;
158				};
159			};
160			/* slot 1 */
161			slot1: mdio@40 {
162				#address-cells = <1>;
163				#size-cells = <0>;
164				reg = <0x40>;
165			};
166			/* slot 2 */
167			slot2: mdio@50 {
168				#address-cells = <1>;
169				#size-cells = <0>;
170				reg = <0x50>;
171			};
172			/* slot 3 */
173			slot3: mdio@60 {
174				#address-cells = <1>;
175				#size-cells = <0>;
176				reg = <0x60>;
177			};
178			/* slot 4 */
179			slot4: mdio@70 {
180				#address-cells = <1>;
181				#size-cells = <0>;
182				reg = <0x70>;
183			};
184		};
185	};
186
187	i2c-mux@77 {
188		compatible = "nxp,pca9547";
189		reg = <0x77>;
190		#address-cells = <1>;
191		#size-cells = <0>;
192	};
193};
194
195&i2c1 {
196	status = "okay";
197
198	rtc@51 {
199		compatible = "pcf2127-rtc";
200		reg = <0x51>;
201	};
202};
203
204&i2c2 {
205	status = "okay";
206};
207
208&i2c3 {
209	status = "okay";
210};
211
212&i2c4 {
213	status = "okay";
214};
215
216&i2c5 {
217	status = "okay";
218};
219
220&i2c6 {
221	status = "okay";
222};
223
224&i2c7 {
225	status = "okay";
226};
227
228&lpuart0 {
229	status = "okay";
230};
231
232&sata {
233	status = "okay";
234};
235
236&serial0 {
237	status = "okay";
238};
239
240&serial1 {
241	status = "okay";
242};
243
244&usb1 {
245	status = "okay";
246};
247
248&usb2 {
249	status = "okay";
250};
251
252&enetc1 {
253	status = "okay";
254	phy-mode = "rgmii";
255	phy-handle = <&qds_phy0>;
256};
257
258&mdio0 {
259	status = "okay";
260};
261
262#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
263#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"
264