1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP LX2162AQDS device tree source 4 * 5 * Copyright 2020-2021 NXP 6 * 7 */ 8 9/dts-v1/; 10 11#include "fsl-lx2160a-qds.dtsi" 12 13/ { 14 model = "NXP Layerscape LX2162AQDS Board"; 15 compatible = "fsl,lx2162aqds", "fsl,lx2160a"; 16 17 aliases { 18 spi1 = &dspi0; 19 spi2 = &dspi1; 20 spi3 = &dspi2; 21 }; 22}; 23 24&usb1 { 25 status = "disabled"; 26}; 27 28&pcie2 { 29 status = "disabled"; 30}; 31 32&pcie5 { 33 status = "disabled"; 34}; 35 36&pcie6 { 37 status = "disabled"; 38}; 39 40&dspi0 { 41 bus-num = <0>; 42 status = "okay"; 43 44 dflash0: n25q128a { 45 #address-cells = <1>; 46 #size-cells = <1>; 47 compatible = "spi-flash"; 48 spi-max-frequency = <3000000>; 49 spi-cpol; 50 spi-cpha; 51 reg = <0>; 52 }; 53 dflash1: sst25wf040b { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 compatible = "spi-flash"; 57 spi-max-frequency = <3000000>; 58 spi-cpol; 59 spi-cpha; 60 reg = <1>; 61 }; 62 dflash2: en25s64 { 63 #address-cells = <1>; 64 #size-cells = <1>; 65 compatible = "spi-flash"; 66 spi-max-frequency = <3000000>; 67 spi-cpol; 68 spi-cpha; 69 reg = <2>; 70 }; 71}; 72 73&dspi1 { 74 bus-num = <0>; 75 status = "okay"; 76 77 dflash3: n25q128a { 78 #address-cells = <1>; 79 #size-cells = <1>; 80 compatible = "spi-flash"; 81 spi-max-frequency = <3000000>; 82 spi-cpol; 83 spi-cpha; 84 reg = <0>; 85 }; 86 dflash4: sst25wf040b { 87 #address-cells = <1>; 88 #size-cells = <1>; 89 compatible = "spi-flash"; 90 spi-max-frequency = <3000000>; 91 spi-cpol; 92 spi-cpha; 93 reg = <1>; 94 }; 95 dflash5: en25s64 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 compatible = "spi-flash"; 99 spi-max-frequency = <3000000>; 100 spi-cpol; 101 spi-cpha; 102 reg = <2>; 103 }; 104}; 105 106&dspi2 { 107 bus-num = <0>; 108 status = "okay"; 109 110 dflash6: n25q128a { 111 #address-cells = <1>; 112 #size-cells = <1>; 113 compatible = "spi-flash"; 114 spi-max-frequency = <3000000>; 115 spi-cpol; 116 spi-cpha; 117 reg = <0>; 118 }; 119 dflash7: sst25wf040b { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 compatible = "spi-flash"; 123 spi-max-frequency = <3000000>; 124 spi-cpol; 125 spi-cpha; 126 reg = <1>; 127 }; 128 dflash8: en25s64 { 129 #address-cells = <1>; 130 #size-cells = <1>; 131 compatible = "spi-flash"; 132 spi-max-frequency = <3000000>; 133 spi-cpol; 134 spi-cpha; 135 reg = <2>; 136 }; 137}; 138 139&esdhc1 { 140 mmc-hs200-1_8v; 141 mmc-hs400-1_8v; 142 bus-width = <8>; 143}; 144