1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	/* these are used by bootloader for disabling nodes */
12	aliases {
13		led0 = &led0;
14		led1 = &led1;
15		led2 = &led2;
16		mmc0 = &usdhc3;
17		nand = &gpmi;
18		usb0 = &usbh1;
19		usb1 = &usbotg;
20	};
21
22	chosen {
23		stdout-path = &uart2;
24	};
25
26	gpio-keys {
27		compatible = "gpio-keys";
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		user-pb {
32			label = "user_pb";
33			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
34			linux,code = <BTN_0>;
35		};
36
37		user-pb1x {
38			label = "user_pb1x";
39			linux,code = <BTN_1>;
40			interrupt-parent = <&gsc>;
41			interrupts = <0>;
42		};
43
44		key-erased {
45			label = "key-erased";
46			linux,code = <BTN_2>;
47			interrupt-parent = <&gsc>;
48			interrupts = <1>;
49		};
50
51		eeprom-wp {
52			label = "eeprom_wp";
53			linux,code = <BTN_3>;
54			interrupt-parent = <&gsc>;
55			interrupts = <2>;
56		};
57
58		tamper {
59			label = "tamper";
60			linux,code = <BTN_4>;
61			interrupt-parent = <&gsc>;
62			interrupts = <5>;
63		};
64
65		switch-hold {
66			label = "switch_hold";
67			linux,code = <BTN_5>;
68			interrupt-parent = <&gsc>;
69			interrupts = <7>;
70		};
71	};
72
73	leds {
74		compatible = "gpio-leds";
75		pinctrl-names = "default";
76		pinctrl-0 = <&pinctrl_gpio_leds>;
77
78		led0: user1 {
79			label = "user1";
80			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
81			default-state = "on";
82			linux,default-trigger = "heartbeat";
83		};
84
85		led1: user2 {
86			label = "user2";
87			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
88			default-state = "off";
89		};
90
91		led2: user3 {
92			label = "user3";
93			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
94			default-state = "off";
95		};
96	};
97
98	memory@10000000 {
99		device_type = "memory";
100		reg = <0x10000000 0x40000000>;
101	};
102
103	pps {
104		compatible = "pps-gpio";
105		pinctrl-names = "default";
106		pinctrl-0 = <&pinctrl_pps>;
107		gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
108	};
109
110	reg_3p3v: regulator-3p3v {
111		compatible = "regulator-fixed";
112		regulator-name = "3P3V";
113		regulator-min-microvolt = <3300000>;
114		regulator-max-microvolt = <3300000>;
115		regulator-always-on;
116	};
117
118	reg_usb_vbus: regulator-5p0v {
119		compatible = "regulator-fixed";
120		regulator-name = "usb_vbus";
121		regulator-min-microvolt = <5000000>;
122		regulator-max-microvolt = <5000000>;
123		regulator-always-on;
124	};
125};
126
127&can1 {
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_flexcan1>;
130	status = "okay";
131};
132
133&ecspi2 {
134	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_ecspi2>;
137	status = "okay";
138};
139
140&fec {
141	pinctrl-names = "default";
142	pinctrl-0 = <&pinctrl_enet>;
143	phy-mode = "rgmii-id";
144	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
145	phy-reset-duration = <10>;
146	phy-reset-post-delay = <100>;
147	status = "okay";
148};
149
150&gpmi {
151	pinctrl-names = "default";
152	pinctrl-0 = <&pinctrl_gpmi_nand>;
153	status = "okay";
154};
155
156&i2c1 {
157	clock-frequency = <100000>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_i2c1>;
160	status = "okay";
161
162	gsc: gsc@20 {
163		compatible = "gw,gsc";
164		reg = <0x20>;
165		interrupt-parent = <&gpio1>;
166		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
167		interrupt-controller;
168		#interrupt-cells = <1>;
169		#address-cells = <1>;
170		#size-cells = <0>;
171
172		adc {
173			compatible = "gw,gsc-adc";
174			#address-cells = <1>;
175			#size-cells = <0>;
176
177			channel@0 {
178				gw,mode = <0>;
179				reg = <0x00>;
180				label = "temp";
181			};
182
183			channel@2 {
184				gw,mode = <1>;
185				reg = <0x02>;
186				label = "vdd_vin";
187			};
188
189			channel@5 {
190				gw,mode = <1>;
191				reg = <0x05>;
192				label = "vdd_3p3";
193			};
194
195			channel@8 {
196				gw,mode = <1>;
197				reg = <0x08>;
198				label = "vdd_bat";
199			};
200
201			channel@b {
202				gw,mode = <1>;
203				reg = <0x0b>;
204				label = "vdd_5p0";
205			};
206
207			channel@e {
208				gw,mode = <1>;
209				reg = <0xe>;
210				label = "vdd_arm";
211			};
212
213			channel@11 {
214				gw,mode = <1>;
215				reg = <0x11>;
216				label = "vdd_soc";
217			};
218
219			channel@14 {
220				gw,mode = <1>;
221				reg = <0x14>;
222				label = "vdd_3p0";
223			};
224
225			channel@17 {
226				gw,mode = <1>;
227				reg = <0x17>;
228				label = "vdd_1p5";
229			};
230
231			channel@1d {
232				gw,mode = <1>;
233				reg = <0x1d>;
234				label = "vdd_1p8";
235			};
236
237			channel@20 {
238				gw,mode = <1>;
239				reg = <0x20>;
240				label = "vdd_1p0";
241			};
242
243			channel@23 {
244				gw,mode = <1>;
245				reg = <0x23>;
246				label = "vdd_2p5";
247			};
248		};
249
250		fan-controller@a {
251			compatible = "gw,gsc-fan";
252			#address-cells = <1>;
253			#size-cells = <0>;
254			reg = <0x0a>;
255		};
256	};
257
258	gsc_gpio: gpio@23 {
259		compatible = "nxp,pca9555";
260		reg = <0x23>;
261		gpio-controller;
262		#gpio-cells = <2>;
263		interrupt-parent = <&gsc>;
264		interrupts = <4>;
265	};
266
267	eeprom@50 {
268		compatible = "atmel,24c02";
269		reg = <0x50>;
270		pagesize = <16>;
271	};
272
273	eeprom@51 {
274		compatible = "atmel,24c02";
275		reg = <0x51>;
276		pagesize = <16>;
277	};
278
279	eeprom@52 {
280		compatible = "atmel,24c02";
281		reg = <0x52>;
282		pagesize = <16>;
283	};
284
285	eeprom@53 {
286		compatible = "atmel,24c02";
287		reg = <0x53>;
288		pagesize = <16>;
289	};
290
291	rtc@68 {
292		compatible = "dallas,ds1672";
293		reg = <0x68>;
294	};
295};
296
297&i2c2 {
298	clock-frequency = <100000>;
299	pinctrl-names = "default";
300	pinctrl-0 = <&pinctrl_i2c2>;
301	status = "okay";
302};
303
304&i2c3 {
305	clock-frequency = <100000>;
306	pinctrl-names = "default";
307	pinctrl-0 = <&pinctrl_i2c3>;
308	status = "okay";
309
310	accel@19 {
311		pinctrl-names = "default";
312		pinctrl-0 = <&pinctrl_accel>;
313		compatible = "st,lis2de12";
314		reg = <0x19>;
315		st,drdy-int-pin = <1>;
316		interrupt-parent = <&gpio7>;
317		interrupts = <13 0>;
318		interrupt-names = "INT1";
319	};
320};
321
322&pcie {
323	pinctrl-names = "default";
324	pinctrl-0 = <&pinctrl_pcie>;
325	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
326	status = "okay";
327};
328
329&pwm1 {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
332	status = "disabled";
333};
334
335&pwm2 {
336	pinctrl-names = "default";
337	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
338	status = "disabled";
339};
340
341&pwm3 {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
344	status = "disabled";
345};
346
347&pwm4 {
348	pinctrl-names = "default";
349	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
350	status = "disabled";
351};
352
353&uart1 {
354	pinctrl-names = "default";
355	pinctrl-0 = <&pinctrl_uart1>;
356	rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
357	status = "okay";
358};
359
360&uart2 {
361	pinctrl-names = "default";
362	pinctrl-0 = <&pinctrl_uart2>;
363	status = "okay";
364};
365
366&uart5 {
367	pinctrl-names = "default";
368	pinctrl-0 = <&pinctrl_uart5>;
369	status = "okay";
370};
371
372&usbotg {
373	vbus-supply = <&reg_usb_vbus>;
374	pinctrl-names = "default";
375	pinctrl-0 = <&pinctrl_usbotg>;
376	disable-over-current;
377	dr_mode = "host";
378	status = "okay";
379};
380
381&usbh1 {
382	vbus-supply = <&reg_usb_vbus>;
383	status = "okay";
384};
385
386&usdhc3 {
387	pinctrl-names = "default", "state_100mhz", "state_200mhz";
388	pinctrl-0 = <&pinctrl_usdhc3>;
389	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
390	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
391	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
392	vmmc-supply = <&reg_3p3v>;
393	no-1-8-v; /* firmware will remove if board revision supports */
394	status = "okay";
395};
396
397&wdog1 {
398	status = "disabled";
399};
400
401&wdog2 {
402	pinctrl-names = "default";
403	pinctrl-0 = <&pinctrl_wdog>;
404	fsl,ext-reset-output;
405	status = "okay";
406};
407
408&iomuxc {
409	pinctrl_accel: accelmuxgrp {
410		fsl,pins = <
411			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b1
412		>;
413	};
414
415	pinctrl_enet: enetgrp {
416		fsl,pins = <
417			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
418			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
419			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
420			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
421			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
422			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
423			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
424			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
425			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
426			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
427			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
428			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
429			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
430			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
431			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
432			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0
433		>;
434	};
435
436	pinctrl_ecspi2: escpi2grp {
437		fsl,pins = <
438			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
439			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
440			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
441			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x100b1
442		>;
443	};
444
445	pinctrl_flexcan1: flexcan1grp {
446		fsl,pins = <
447			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
448			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
449			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0
450		>;
451	};
452
453	pinctrl_gpio_leds: gpioledsgrp {
454		fsl,pins = <
455			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
456			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
457			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
458		>;
459	};
460
461	pinctrl_gpmi_nand: gpminandgrp {
462		fsl,pins = <
463			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
464			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
465			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
466			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
467			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
468			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
469			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
470			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
471			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
472			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
473			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
474			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
475			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
476			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
477			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
478		>;
479	};
480
481	pinctrl_i2c1: i2c1grp {
482		fsl,pins = <
483			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
484			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
485			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x0001b0b0
486		>;
487	};
488
489	pinctrl_i2c2: i2c2grp {
490		fsl,pins = <
491			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
492			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
493		>;
494	};
495
496	pinctrl_i2c3: i2c3grp {
497		fsl,pins = <
498			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
499			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
500		>;
501	};
502
503	pinctrl_pcie: pciegrp {
504		fsl,pins = <
505			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
506			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0
507		>;
508	};
509
510	pinctrl_pps: ppsgrp {
511		fsl,pins = <
512			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x1b0b1
513		>;
514	};
515
516	pinctrl_pwm1: pwm1grp {
517		fsl,pins = <
518			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
519		>;
520	};
521
522	pinctrl_pwm2: pwm2grp {
523		fsl,pins = <
524			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
525		>;
526	};
527
528	pinctrl_pwm3: pwm3grp {
529		fsl,pins = <
530			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
531		>;
532	};
533
534	pinctrl_pwm4: pwm4grp {
535		fsl,pins = <
536			MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
537		>;
538	};
539
540	pinctrl_uart1: uart1grp {
541		fsl,pins = <
542			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
543			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
544			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x4001b0b1
545		>;
546	};
547
548	pinctrl_uart2: uart2grp {
549		fsl,pins = <
550			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
551			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
552			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x4001b0b1
553		>;
554	};
555
556	pinctrl_uart5: uart5grp {
557		fsl,pins = <
558			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
559			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
560		>;
561	};
562
563	pinctrl_usbotg: usbotggrp {
564		fsl,pins = <
565			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x13059
566		>;
567	};
568
569	pinctrl_usdhc3: usdhc3grp {
570		fsl,pins = <
571			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
572			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
573			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
574			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
575			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
576			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
577			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
578			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
579		>;
580	};
581
582	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
583		fsl,pins = <
584			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
585			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
586			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
587			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
588			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
589			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
590			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
591			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
592		>;
593	};
594
595	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
596		fsl,pins = <
597			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
598			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
599			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
600			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
601			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
602			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
603			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
604			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
605		>;
606	};
607
608	pinctrl_wdog: wdoggrp {
609		fsl,pins = <
610			MX6QDL_PAD_SD1_DAT3__WDOG2_B		0x1b0b0
611		>;
612	};
613};
614