1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/memory/stm32-sdram.h>
8/{
9	clocks {
10		u-boot,dm-pre-reloc;
11	};
12
13	aliases {
14		/* Aliases for gpios so as to use sequence */
15		gpio0 = &gpioa;
16		gpio1 = &gpiob;
17		gpio2 = &gpioc;
18		gpio3 = &gpiod;
19		gpio4 = &gpioe;
20		gpio5 = &gpiof;
21		gpio6 = &gpiog;
22		gpio7 = &gpioh;
23		gpio8 = &gpioi;
24		gpio9 = &gpioj;
25		gpio10 = &gpiok;
26	};
27
28	soc {
29		u-boot,dm-pre-reloc;
30		pin-controller {
31			u-boot,dm-pre-reloc;
32		};
33
34		fmc: fmc@A0000000 {
35			compatible = "st,stm32-fmc";
36			reg = <0xA0000000 0x1000>;
37			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
38			st,syscfg = <&syscfg>;
39			pinctrl-0 = <&fmc_pins_d32>;
40			pinctrl-names = "default";
41			st,mem_remap = <4>;
42			u-boot,dm-pre-reloc;
43
44			/*
45			 * Memory configuration from sdram
46			 * MICRON MT48LC4M32B2B5-7
47			 */
48			bank0: bank@0 {
49			       st,sdram-control = /bits/ 8 <NO_COL_9
50							    NO_ROW_12
51							    MWIDTH_32
52							    BANKS_4
53							    CAS_3
54							    SDCLK_2
55							    RD_BURST_EN
56							    RD_PIPE_DL_0>;
57			       st,sdram-timing = /bits/ 8 <TMRD_2
58							   TXSR_6
59							   TRAS_4
60							   TRC_6
61							   TWR_2
62							   TRP_2
63							   TRCD_2>;
64			       st,sdram-refcount = < 2812 >;
65		       };
66		};
67	};
68};
69
70&clk_hse {
71	u-boot,dm-pre-reloc;
72};
73
74&clk_lse {
75	u-boot,dm-pre-reloc;
76};
77
78&clk_i2s_ckin {
79	u-boot,dm-pre-reloc;
80};
81
82&pwrcfg {
83	u-boot,dm-pre-reloc;
84};
85
86&syscfg {
87	u-boot,dm-pre-reloc;
88};
89
90&rcc {
91	u-boot,dm-pre-reloc;
92};
93
94&gpioa {
95	u-boot,dm-pre-reloc;
96};
97
98&gpiob {
99	u-boot,dm-pre-reloc;
100};
101
102&gpioc {
103	u-boot,dm-pre-reloc;
104};
105
106&gpiod {
107	u-boot,dm-pre-reloc;
108};
109
110&gpioe {
111	u-boot,dm-pre-reloc;
112};
113
114&gpiof {
115	u-boot,dm-pre-reloc;
116};
117
118&gpiog {
119	u-boot,dm-pre-reloc;
120};
121
122&gpioh {
123	u-boot,dm-pre-reloc;
124};
125
126&gpioi {
127	u-boot,dm-pre-reloc;
128};
129
130&gpioj {
131	u-boot,dm-pre-reloc;
132};
133
134&gpiok {
135	u-boot,dm-pre-reloc;
136};
137
138&pinctrl {
139	usart1_pins_a: usart1-0	{
140		u-boot,dm-pre-reloc;
141		pins1 {
142			u-boot,dm-pre-reloc;
143		};
144		pins2 {
145			u-boot,dm-pre-reloc;
146		};
147	};
148
149	fmc_pins_d32: fmc_d32@0 {
150		u-boot,dm-pre-reloc;
151		pins
152		{
153			pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
154				 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
155				 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
156				 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
157				 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
158				 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
159				 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
160				 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
161				 <STM32_PINMUX('H',15, AF12)>, /* D23 */
162				 <STM32_PINMUX('H',14, AF12)>, /* D22 */
163				 <STM32_PINMUX('H',13, AF12)>, /* D21 */
164				 <STM32_PINMUX('H',12, AF12)>, /* D20 */
165				 <STM32_PINMUX('H',11, AF12)>, /* D19 */
166				 <STM32_PINMUX('H',10, AF12)>, /* D18 */
167				 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
168				 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
169
170				 <STM32_PINMUX('D',10, AF12)>, /* D15 */
171				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
172				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
173				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
174				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
175				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
176				 <STM32_PINMUX('E',12, AF12)>, /* D09 */
177				 <STM32_PINMUX('E',11, AF12)>, /* D08 */
178				 <STM32_PINMUX('E',10, AF12)>, /* D07 */
179				 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
180				 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
181				 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
182				 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
183				 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
184				 <STM32_PINMUX('D',15, AF12)>, /* D01 */
185				 <STM32_PINMUX('D',14, AF12)>, /* D00 */
186
187				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
188				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
189				 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
190				 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
191
192				 <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */
193				 <STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */
194				 <STM32_PINMUX('G', 3, AF12)>, /* A13 */
195				 <STM32_PINMUX('G', 2, AF12)>, /* A12 */
196				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
197				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
198				 <STM32_PINMUX('F',15, AF12)>, /* A09 */
199				 <STM32_PINMUX('F',14, AF12)>, /* A08 */
200				 <STM32_PINMUX('F',13, AF12)>, /* A07 */
201				 <STM32_PINMUX('F',12, AF12)>, /* A06 */
202				 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
203				 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
204				 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
205				 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
206				 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
207				 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
208
209				 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
210				 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
211				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
212				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
213				 <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
214				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
215			slew-rate = <2>;
216			u-boot,dm-pre-reloc;
217		};
218	};
219};
220
221&timer5 {
222	u-boot,dm-pre-reloc;
223};
224