1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU216 4 * 5 * (C) Copyright 2017 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU216 RevA"; 21 compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 gpio0 = &gpio; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 mmc0 = &sdhci1; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &dcc; 32 spi0 = &qspi; 33 usb0 = &usb0; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 xlnx,eeprom = <&eeprom>; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 autorepeat; 50 sw19 { 51 label = "sw19"; 52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 53 linux,code = <KEY_DOWN>; 54 wakeup-source; 55 autorepeat; 56 }; 57 }; 58 59 leds { 60 compatible = "gpio-leds"; 61 heartbeat_led { 62 label = "heartbeat"; 63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 64 linux,default-trigger = "heartbeat"; 65 }; 66 }; 67 68 ina226-vccint { 69 compatible = "iio-hwmon"; 70 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; 71 }; 72 ina226-vccint-io-bram-ps { 73 compatible = "iio-hwmon"; 74 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; 75 }; 76 ina226-vcc1v8 { 77 compatible = "iio-hwmon"; 78 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; 79 }; 80 ina226-vcc1v2 { 81 compatible = "iio-hwmon"; 82 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; 83 }; 84 ina226-vadj-fmc { 85 compatible = "iio-hwmon"; 86 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; 87 }; 88 ina226-mgtavcc { 89 compatible = "iio-hwmon"; 90 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; 91 }; 92 ina226-mgt1v2 { 93 compatible = "iio-hwmon"; 94 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; 95 }; 96 ina226-mgt1v8 { 97 compatible = "iio-hwmon"; 98 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; 99 }; 100 ina226-vccint-ams { 101 compatible = "iio-hwmon"; 102 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; 103 }; 104 ina226-dac-avtt { 105 compatible = "iio-hwmon"; 106 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; 107 }; 108 ina226-dac-avccaux { 109 compatible = "iio-hwmon"; 110 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; 111 }; 112 ina226-adc-avcc { 113 compatible = "iio-hwmon"; 114 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; 115 }; 116 ina226-adc-avccaux { 117 compatible = "iio-hwmon"; 118 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; 119 }; 120 ina226-dac-avcc { 121 compatible = "iio-hwmon"; 122 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; 123 }; 124 125 /* 48MHz reference crystal */ 126 ref48: ref48M { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <48000000>; 130 }; 131}; 132 133&psgtr { 134 status = "okay"; 135 /* pcie, sata, usb3, dp */ 136 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 137 clock-names = "ref0", "ref1", "ref2", "ref3"; 138}; 139 140&dcc { 141 status = "okay"; 142}; 143 144&fpd_dma_chan1 { 145 status = "okay"; 146}; 147 148&fpd_dma_chan2 { 149 status = "okay"; 150}; 151 152&fpd_dma_chan3 { 153 status = "okay"; 154}; 155 156&fpd_dma_chan4 { 157 status = "okay"; 158}; 159 160&fpd_dma_chan5 { 161 status = "okay"; 162}; 163 164&fpd_dma_chan6 { 165 status = "okay"; 166}; 167 168&fpd_dma_chan7 { 169 status = "okay"; 170}; 171 172&fpd_dma_chan8 { 173 status = "okay"; 174}; 175 176&gem3 { 177 status = "okay"; 178 phy-handle = <&phy0>; 179 phy-mode = "rgmii-id"; 180 phy0: ethernet-phy@c { 181 reg = <0xc>; 182 ti,rx-internal-delay = <0x8>; 183 ti,tx-internal-delay = <0xa>; 184 ti,fifo-depth = <0x1>; 185 ti,dp83867-rxctrl-strap-quirk; 186 }; 187}; 188 189&gpio { 190 status = "okay"; 191 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ 192 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ 193 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ 194 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ 195 "", "", "BUTTON", "LED", "", /* 20 - 24 */ 196 "", "PMU_INPUT", "", "", "", /* 25 - 29 */ 197 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ 198 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ 199 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ 200 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ 201 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ 202 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ 203 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ 204 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ 205 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ 206 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ 207 "", "", /* 78 - 79 */ 208 "", "", "", "", "", /* 80 - 84 */ 209 "", "", "", "", "", /* 85 -89 */ 210 "", "", "", "", "", /* 90 - 94 */ 211 "", "", "", "", "", /* 95 - 99 */ 212 "", "", "", "", "", /* 100 - 104 */ 213 "", "", "", "", "", /* 105 - 109 */ 214 "", "", "", "", "", /* 110 - 114 */ 215 "", "", "", "", "", /* 115 - 119 */ 216 "", "", "", "", "", /* 120 - 124 */ 217 "", "", "", "", "", /* 125 - 129 */ 218 "", "", "", "", "", /* 130 - 134 */ 219 "", "", "", "", "", /* 135 - 139 */ 220 "", "", "", "", "", /* 140 - 144 */ 221 "", "", "", "", "", /* 145 - 149 */ 222 "", "", "", "", "", /* 150 - 154 */ 223 "", "", "", "", "", /* 155 - 159 */ 224 "", "", "", "", "", /* 160 - 164 */ 225 "", "", "", "", "", /* 165 - 169 */ 226 "", "", "", ""; /* 170 - 174 */ 227}; 228 229&gpu { 230 status = "okay"; 231}; 232 233&i2c0 { 234 status = "okay"; 235 clock-frequency = <400000>; 236 pinctrl-names = "default", "gpio"; 237 pinctrl-0 = <&pinctrl_i2c0_default>; 238 pinctrl-1 = <&pinctrl_i2c0_gpio>; 239 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 240 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 241 242 tca6416_u15: gpio@20 { /* u15 */ 243 compatible = "ti,tca6416"; 244 reg = <0x20>; 245 gpio-controller; /* interrupt not connected */ 246 #gpio-cells = <2>; 247 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ 248 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ 249 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ 250 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ 251 }; 252 253 i2c-mux@75 { /* u17 */ 254 compatible = "nxp,pca9544"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 reg = <0x75>; 258 i2c@0 { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 reg = <0>; 262 /* PS_PMBUS */ 263 /* PMBUS_ALERT done via pca9544 */ 264 vccint: ina226@40 { /* u65 */ 265 compatible = "ti,ina226"; 266 #io-channel-cells = <1>; 267 label = "ina226-vccint"; 268 reg = <0x40>; 269 shunt-resistor = <5000>; 270 }; 271 vccint_io_bram_ps: ina226@41 { /* u57 */ 272 compatible = "ti,ina226"; 273 #io-channel-cells = <1>; 274 label = "ina226-vccint-io-bram-ps"; 275 reg = <0x41>; 276 shunt-resistor = <5000>; 277 }; 278 vcc1v8: ina226@42 { /* u60 */ 279 compatible = "ti,ina226"; 280 #io-channel-cells = <1>; 281 label = "ina226-vcc1v8"; 282 reg = <0x42>; 283 shunt-resistor = <2000>; 284 }; 285 vcc1v2: ina226@43 { /* u58 */ 286 compatible = "ti,ina226"; 287 #io-channel-cells = <1>; 288 label = "ina226-vcc1v2"; 289 reg = <0x43>; 290 shunt-resistor = <5000>; 291 }; 292 vadj_fmc: ina226@45 { /* u62 */ 293 compatible = "ti,ina226"; 294 #io-channel-cells = <1>; 295 label = "ina226-vadj-fmc"; 296 reg = <0x45>; 297 shunt-resistor = <5000>; 298 }; 299 mgtavcc: ina226@46 { /* u67 */ 300 compatible = "ti,ina226"; 301 #io-channel-cells = <1>; 302 label = "ina226-mgtavcc"; 303 reg = <0x46>; 304 shunt-resistor = <2000>; 305 }; 306 mgt1v2: ina226@47 { /* u63 */ 307 compatible = "ti,ina226"; 308 #io-channel-cells = <1>; 309 label = "ina226-mgt1v2"; 310 reg = <0x47>; 311 shunt-resistor = <5000>; 312 }; 313 mgt1v8: ina226@48 { /* u64 */ 314 compatible = "ti,ina226"; 315 #io-channel-cells = <1>; 316 label = "ina226-mgt1v8"; 317 reg = <0x48>; 318 shunt-resistor = <5000>; 319 }; 320 vccint_ams: ina226@49 { /* u61 */ 321 compatible = "ti,ina226"; 322 #io-channel-cells = <1>; 323 label = "ina226-vccint-ams"; 324 reg = <0x49>; 325 shunt-resistor = <5000>; 326 }; 327 dac_avtt: ina226@4a { /* u59 */ 328 compatible = "ti,ina226"; 329 #io-channel-cells = <1>; 330 label = "ina226-dac-avtt"; 331 reg = <0x4a>; 332 shunt-resistor = <5000>; 333 }; 334 dac_avccaux: ina226@4b { /* u124 */ 335 compatible = "ti,ina226"; 336 #io-channel-cells = <1>; 337 label = "ina226-dac-avccaux"; 338 reg = <0x4b>; 339 shunt-resistor = <5000>; 340 }; 341 adc_avcc: ina226@4c { /* u75 */ 342 compatible = "ti,ina226"; 343 #io-channel-cells = <1>; 344 label = "ina226-adc-avcc"; 345 reg = <0x4c>; 346 shunt-resistor = <5000>; 347 }; 348 adc_avccaux: ina226@4d { /* u71 */ 349 compatible = "ti,ina226"; 350 #io-channel-cells = <1>; 351 label = "ina226-adc-avccaux"; 352 reg = <0x4d>; 353 shunt-resistor = <5000>; 354 }; 355 dac_avcc: ina226@4e { /* u77 */ 356 compatible = "ti,ina226"; 357 #io-channel-cells = <1>; 358 label = "ina226-dac-avcc"; 359 reg = <0x4e>; 360 shunt-resistor = <5000>; 361 }; 362 }; 363 i2c@1 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 reg = <1>; 367 /* NC */ 368 }; 369 i2c@2 { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 reg = <2>; 373 /* u104 - ir35215 0x10/0x40 */ 374 /* u127 - ir38164 0x1b/0x4b */ 375 /* u112 - ir38164 0x13/0x43 */ 376 /* u123 - ir38164 0x1c/0x4c */ 377 378 irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ 379 compatible = "infineon,irps5401"; 380 reg = <0x44>; /* i2c addr 0x14 */ 381 }; 382 irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ 383 compatible = "infineon,irps5401"; 384 reg = <0x45>; /* i2c addr 0x15 */ 385 }; 386 /* J21 header too */ 387 388 }; 389 i2c@3 { 390 #address-cells = <1>; 391 #size-cells = <0>; 392 reg = <3>; 393 /* SYSMON */ 394 }; 395 }; 396 /* u38 MPS430 */ 397}; 398 399&i2c1 { 400 status = "okay"; 401 clock-frequency = <400000>; 402 pinctrl-names = "default", "gpio"; 403 pinctrl-0 = <&pinctrl_i2c1_default>; 404 pinctrl-1 = <&pinctrl_i2c1_gpio>; 405 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 406 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 407 408 i2c-mux@74 { 409 compatible = "nxp,pca9548"; /* u20 */ 410 #address-cells = <1>; 411 #size-cells = <0>; 412 reg = <0x74>; 413 i2c-mux-idle-disconnect; 414 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ 415 i2c_eeprom: i2c@0 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 reg = <0>; 419 /* 420 * IIC_EEPROM 1kB memory which uses 256B blocks 421 * where every block has different address. 422 * 0 - 256B address 0x54 423 * 256B - 512B address 0x55 424 * 512B - 768B address 0x56 425 * 768B - 1024B address 0x57 426 */ 427 eeprom: eeprom@54 { /* u21 */ 428 compatible = "atmel,24c128"; 429 reg = <0x54>; 430 }; 431 }; 432 i2c_si5341: i2c@1 { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 reg = <1>; 436 si5341: clock-generator@36 { /* SI5341 - u43 */ 437 compatible = "silabs,si5341"; 438 reg = <0x36>; 439 #clock-cells = <2>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&ref48>; 443 clock-names = "xtal"; 444 clock-output-names = "si5341"; 445 446 si5341_2: out@2 { 447 /* refclk2 for PS-GT, used for USB3 */ 448 reg = <2>; 449 always-on; 450 }; 451 si5341_3: out@3 { 452 /* refclk3 for PS-GT, used for SATA */ 453 reg = <3>; 454 always-on; 455 }; 456 si5341_5: out@5 { 457 /* refclk5 PL CLK100 */ 458 reg = <5>; 459 always-on; 460 }; 461 si5341_6: out@6 { 462 /* refclk6 PL CLK125 */ 463 reg = <6>; 464 always-on; 465 }; 466 si5341_9: out@9 { 467 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 468 reg = <9>; 469 always-on; 470 }; 471 }; 472 }; 473 i2c_si570_user_c0: i2c@2 { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 reg = <2>; 477 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ 478 #clock-cells = <0>; 479 compatible = "silabs,si570"; 480 reg = <0x5d>; 481 temperature-stability = <50>; 482 factory-fout = <300000000>; 483 clock-frequency = <300000000>; 484 clock-output-names = "si570_user_c0"; 485 }; 486 }; 487 i2c_si570_mgt: i2c@3 { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 reg = <3>; 491 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ 492 #clock-cells = <0>; 493 compatible = "silabs,si570"; 494 reg = <0x5d>; 495 temperature-stability = <50>; 496 factory-fout = <156250000>; 497 clock-frequency = <148500000>; 498 clock-output-names = "si570_mgt"; 499 }; 500 }; 501 i2c_8a34001: i2c@4 { 502 #address-cells = <1>; 503 #size-cells = <0>; 504 reg = <4>; 505 idt_8a34001: phc@5b { 506 compatible = "idt,8a34001"; /* u409B */ 507 reg = <0x5b>; 508 }; 509 }; 510 i2c_clk104: i2c@5 { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 reg = <5>; 514 /* CLK104_SDA */ 515 }; 516 i2c@6 { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 reg = <6>; 520 /* RFMCP connector */ 521 }; 522 /* 7 NC */ 523 }; 524 525 i2c-mux@75 { 526 compatible = "nxp,pca9548"; /* u22 */ 527 #address-cells = <1>; 528 #size-cells = <0>; 529 reg = <0x75>; 530 i2c-mux-idle-disconnect; 531 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ 532 i2c@0 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 reg = <0>; 536 /* FMCP_HSPC_IIC */ 537 }; 538 i2c_si570_user_c1: i2c@1 { 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <1>; 542 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ 543 #clock-cells = <0>; 544 compatible = "silabs,si570"; 545 reg = <0x5d>; 546 temperature-stability = <50>; 547 factory-fout = <300000000>; 548 clock-frequency = <300000000>; 549 clock-output-names = "si570_user_c1"; 550 }; 551 }; 552 i2c@2 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <2>; 556 /* SYSMON */ 557 }; 558 i2c@3 { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 reg = <3>; 562 /* DDR4 SODIMM */ 563 }; 564 i2c@4 { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 reg = <4>; 568 /* SFP3 */ 569 }; 570 i2c@5 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 reg = <5>; 574 /* SFP2 */ 575 }; 576 i2c@6 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 reg = <6>; 580 /* SFP1 */ 581 }; 582 i2c@7 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 reg = <7>; 586 /* SFP0 */ 587 }; 588 }; 589 /* MSP430 */ 590}; 591 592&pinctrl0 { 593 status = "okay"; 594 pinctrl_i2c0_default: i2c0-default { 595 mux { 596 groups = "i2c0_3_grp"; 597 function = "i2c0"; 598 }; 599 600 conf { 601 groups = "i2c0_3_grp"; 602 bias-pull-up; 603 slew-rate = <SLEW_RATE_SLOW>; 604 power-source = <IO_STANDARD_LVCMOS18>; 605 }; 606 }; 607 608 pinctrl_i2c0_gpio: i2c0-gpio { 609 mux { 610 groups = "gpio0_14_grp", "gpio0_15_grp"; 611 function = "gpio0"; 612 }; 613 614 conf { 615 groups = "gpio0_14_grp", "gpio0_15_grp"; 616 slew-rate = <SLEW_RATE_SLOW>; 617 power-source = <IO_STANDARD_LVCMOS18>; 618 }; 619 }; 620 621 pinctrl_i2c1_default: i2c1-default { 622 mux { 623 groups = "i2c1_4_grp"; 624 function = "i2c1"; 625 }; 626 627 conf { 628 groups = "i2c1_4_grp"; 629 bias-pull-up; 630 slew-rate = <SLEW_RATE_SLOW>; 631 power-source = <IO_STANDARD_LVCMOS18>; 632 }; 633 }; 634 635 pinctrl_i2c1_gpio: i2c1-gpio { 636 mux { 637 groups = "gpio0_16_grp", "gpio0_17_grp"; 638 function = "gpio0"; 639 }; 640 641 conf { 642 groups = "gpio0_16_grp", "gpio0_17_grp"; 643 slew-rate = <SLEW_RATE_SLOW>; 644 power-source = <IO_STANDARD_LVCMOS18>; 645 }; 646 }; 647}; 648 649&qspi { 650 status = "okay"; 651 is-dual = <1>; 652 flash@0 { 653 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ 654 #address-cells = <1>; 655 #size-cells = <1>; 656 reg = <0x0>; 657 spi-tx-bus-width = <1>; 658 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 659 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 660 }; 661}; 662 663&rtc { 664 status = "okay"; 665}; 666 667&sata { 668 status = "okay"; 669 /* SATA OOB timing settings */ 670 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 671 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 672 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 673 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 674 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 675 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 676 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 677 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 678 phy-names = "sata-phy"; 679 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; 680}; 681 682/* SD1 with level shifter */ 683&sdhci1 { 684 status = "okay"; 685 disable-wp; 686 /* 687 * This property should be removed for supporting UHS mode 688 */ 689 no-1-8-v; 690 xlnx,mio-bank = <1>; 691}; 692 693&uart0 { 694 status = "okay"; 695}; 696 697/* ULPI SMSC USB3320 */ 698&usb0 { 699 status = "okay"; 700}; 701 702&dwc3_0 { 703 status = "okay"; 704 dr_mode = "host"; 705 snps,usb3_lpm_capable; 706 phy-names = "usb3-phy"; 707 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 708}; 709