1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Keystone2: Common SoC definitions, structures etc.
4  *
5  * (C) Copyright 2012-2014
6  *     Texas Instruments Incorporated, <www.ti.com>
7  */
8 #ifndef __ASM_ARCH_HARDWARE_H
9 #define __ASM_ARCH_HARDWARE_H
10 
11 #include <config.h>
12 
13 #ifndef __ASSEMBLY__
14 #include <linux/bitops.h>
15 
16 #include <linux/sizes.h>
17 #include <asm/io.h>
18 
19 #define	REG(addr)        (*(volatile unsigned int *)(addr))
20 #define REG_P(addr)      ((volatile unsigned int *)(addr))
21 
22 typedef volatile unsigned int   dv_reg;
23 typedef volatile unsigned int   *dv_reg_p;
24 
25 #endif
26 
27 #define KS2_DDRPHY_PIR_OFFSET           0x04
28 #define KS2_DDRPHY_PGCR0_OFFSET         0x08
29 #define KS2_DDRPHY_PGCR1_OFFSET         0x0C
30 #define KS2_DDRPHY_PGSR0_OFFSET         0x10
31 #define KS2_DDRPHY_PGSR1_OFFSET         0x14
32 #define KS2_DDRPHY_PLLCR_OFFSET         0x18
33 #define KS2_DDRPHY_PTR0_OFFSET          0x1C
34 #define KS2_DDRPHY_PTR1_OFFSET          0x20
35 #define KS2_DDRPHY_PTR2_OFFSET          0x24
36 #define KS2_DDRPHY_PTR3_OFFSET          0x28
37 #define KS2_DDRPHY_PTR4_OFFSET          0x2C
38 #define KS2_DDRPHY_DCR_OFFSET           0x44
39 
40 #define KS2_DDRPHY_DTPR0_OFFSET         0x48
41 #define KS2_DDRPHY_DTPR1_OFFSET         0x4C
42 #define KS2_DDRPHY_DTPR2_OFFSET         0x50
43 
44 #define KS2_DDRPHY_MR0_OFFSET           0x54
45 #define KS2_DDRPHY_MR1_OFFSET           0x58
46 #define KS2_DDRPHY_MR2_OFFSET           0x5C
47 #define KS2_DDRPHY_DTCR_OFFSET          0x68
48 #define KS2_DDRPHY_PGCR2_OFFSET         0x8C
49 
50 #define KS2_DDRPHY_ZQ0CR1_OFFSET        0x184
51 #define KS2_DDRPHY_ZQ1CR1_OFFSET        0x194
52 #define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
53 #define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
54 
55 #define KS2_DDRPHY_DATX8_2_OFFSET       0x240
56 #define KS2_DDRPHY_DATX8_3_OFFSET       0x280
57 #define KS2_DDRPHY_DATX8_4_OFFSET       0x2C0
58 #define KS2_DDRPHY_DATX8_5_OFFSET       0x300
59 #define KS2_DDRPHY_DATX8_6_OFFSET       0x340
60 #define KS2_DDRPHY_DATX8_7_OFFSET       0x380
61 #define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
62 
63 #define IODDRM_MASK                     0x00000180
64 #define ZCKSEL_MASK                     0x01800000
65 #define CL_MASK                         0x00000072
66 #define WR_MASK                         0x00000E00
67 #define BL_MASK                         0x00000003
68 #define RRMODE_MASK                     0x00040000
69 #define UDIMM_MASK                      0x20000000
70 #define BYTEMASK_MASK                   0x0003FC00
71 #define MPRDQ_MASK                      0x00000080
72 #define PDQ_MASK                        0x00000070
73 #define NOSRA_MASK                      0x08000000
74 #define ECC_MASK                        0x00000001
75 #define DXEN_MASK                       0x00000001
76 
77 /* DDR3 definitions */
78 #define KS2_DDR3A_EMIF_CTRL_BASE	0x21010000
79 #define KS2_DDR3A_EMIF_DATA_BASE	0x80000000
80 #define KS2_DDR3A_DDRPHYC		0x02329000
81 #define EMIF1_BASE			KS2_DDR3A_EMIF_CTRL_BASE
82 
83 #define KS2_DDR3_MIDR_OFFSET            0x00
84 #define KS2_DDR3_STATUS_OFFSET          0x04
85 #define KS2_DDR3_SDCFG_OFFSET           0x08
86 #define KS2_DDR3_SDRFC_OFFSET           0x10
87 #define KS2_DDR3_SDTIM1_OFFSET          0x18
88 #define KS2_DDR3_SDTIM2_OFFSET          0x1C
89 #define KS2_DDR3_SDTIM3_OFFSET          0x20
90 #define KS2_DDR3_SDTIM4_OFFSET          0x28
91 #define KS2_DDR3_PMCTL_OFFSET           0x38
92 #define KS2_DDR3_ZQCFG_OFFSET           0xC8
93 
94 #define KS2_DDR3_PLLCTRL_PHY_RESET	0x80000000
95 
96 /* DDR3 ECC */
97 #define KS2_DDR3_ECC_INT_STATUS_OFFSET			0x0AC
98 #define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET		0x0B4
99 #define KS2_DDR3_ECC_CTRL_OFFSET			0x110
100 #define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET			0x114
101 #define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET		0x130
102 #define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET	0x13C
103 
104 /* DDR3 ECC Interrupt Status register */
105 #define KS2_DDR3_1B_ECC_ERR_SYS		BIT(5)
106 #define KS2_DDR3_2B_ECC_ERR_SYS		BIT(4)
107 #define KS2_DDR3_WR_ECC_ERR_SYS		BIT(3)
108 
109 /* DDR3 ECC Control register */
110 #define KS2_DDR3_ECC_EN			BIT(31)
111 #define KS2_DDR3_ECC_ADDR_RNG_PROT	BIT(30)
112 #define KS2_DDR3_ECC_VERIFY_EN		BIT(29)
113 #define KS2_DDR3_ECC_RMW_EN		BIT(28)
114 #define KS2_DDR3_ECC_ADDR_RNG_1_EN	BIT(0)
115 
116 #define KS2_DDR3_ECC_ENABLE		(KS2_DDR3_ECC_EN | \
117 					KS2_DDR3_ECC_ADDR_RNG_PROT | \
118 					KS2_DDR3_ECC_VERIFY_EN)
119 
120 /* EDMA */
121 #define KS2_EDMA0_BASE			0x02700000
122 
123 /* EDMA3 register offsets */
124 #define KS2_EDMA_QCHMAP0		0x0200
125 #define KS2_EDMA_IPR			0x1068
126 #define KS2_EDMA_ICR			0x1070
127 #define KS2_EDMA_QEECR			0x1088
128 #define KS2_EDMA_QEESR			0x108c
129 #define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
130 
131 /* NETCP pktdma */
132 #ifdef CONFIG_SOC_K2G
133 #define KS2_NETCP_PDMA_RX_FREE_QUEUE	113
134 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	114
135 #else
136 #define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
137 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
138 #endif
139 
140 /* Chip Interrupt Controller */
141 #define KS2_CIC2_BASE			0x02608000
142 
143 /* Chip Interrupt Controller register offsets */
144 #define KS2_CIC_CTRL			0x04
145 #define KS2_CIC_HOST_CTRL		0x0C
146 #define KS2_CIC_GLOBAL_ENABLE		0x10
147 #define KS2_CIC_SYS_ENABLE_IDX_SET	0x28
148 #define KS2_CIC_HOST_ENABLE_IDX_SET	0x34
149 #define KS2_CIC_CHAN_MAP(n)		(0x0400 + (n << 2))
150 
151 #define KS2_UART0_BASE                	0x02530c00
152 #define KS2_UART1_BASE                	0x02531000
153 
154 /* Boot Config */
155 #define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
156 #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
157 #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
158 #define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
159 #define KS2_ETHERNET_CFG		(KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
160 #define KS2_ETHERNET_RGMII		2
161 
162 /* PSC */
163 #define KS2_PSC_BASE			0x02350000
164 #define KS2_LPSC_GEM_0			15
165 #define KS2_LPSC_TETRIS			52
166 #define KS2_TETRIS_PWR_DOMAIN		31
167 #define KS2_GEM_0_PWR_DOMAIN		8
168 
169 /* Chip configuration unlock codes and registers */
170 #define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
171 #define KS2_KICK1			(KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
172 #define KS2_KICK0_MAGIC			0x83e70b13
173 #define KS2_KICK1_MAGIC			0x95a4f1e0
174 
175 /* PLL control registers */
176 #define KS2_MAINPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x350)
177 #define KS2_MAINPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x354)
178 #define KS2_PASSPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x358)
179 #define KS2_PASSPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
180 #define KS2_DDR3APLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x360)
181 #define KS2_DDR3APLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x364)
182 #define KS2_DDR3BPLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x368)
183 #define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
184 #define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
185 #define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
186 #define KS2_UARTPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x390)
187 #define KS2_UARTPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x394)
188 
189 #define KS2_PLL_CNTRL_BASE		0x02310000
190 #define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
191 #define KS2_RSTCTRL_RSTYPE		(KS2_PLL_CNTRL_BASE + 0xe4)
192 #define KS2_RSTCTRL			(KS2_PLL_CNTRL_BASE + 0xe8)
193 #define KS2_RSTCTRL_RSCFG		(KS2_PLL_CNTRL_BASE + 0xec)
194 #define KS2_RSTCTRL_KEY			0x5a69
195 #define KS2_RSTCTRL_MASK		0xffff0000
196 #define KS2_RSTCTRL_SWRST		0xfffe0000
197 #define KS2_RSTYPE_PLL_SOFT		BIT(13)
198 
199 /* SPI */
200 #ifdef CONFIG_SOC_K2G
201 #define KS2_SPI0_BASE			0x21805400
202 #define KS2_SPI1_BASE			0x21805800
203 #define KS2_SPI2_BASE			0x21805c00
204 #define KS2_SPI3_BASE			0x21806000
205 #else
206 #define KS2_SPI0_BASE			0x21000400
207 #define KS2_SPI1_BASE			0x21000600
208 #define KS2_SPI2_BASE			0x21000800
209 #define KS2_SPI_BASE			KS2_SPI0_BASE
210 #endif
211 
212 /* AEMIF */
213 #define KS2_AEMIF_CNTRL_BASE       	0x21000a00
214 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
215 
216 /* Flag from ks2_debug options to check if DSPs need to stay ON */
217 #define DBG_LEAVE_DSPS_ON		0x1
218 
219 /* MSMC control */
220 #define KS2_MSMC_CTRL_BASE		0x0bc00000
221 #define KS2_MSMC_DATA_BASE		0x0c000000
222 
223 /* KS2 Generic Privilege ID Settings for MSMC2 */
224 #define KS2_MSMC_SEGMENT_C6X_0		0
225 #define KS2_MSMC_SEGMENT_C6X_1		1
226 #define KS2_MSMC_SEGMENT_C6X_2		2
227 #define KS2_MSMC_SEGMENT_C6X_3		3
228 #define KS2_MSMC_SEGMENT_C6X_4		4
229 #define KS2_MSMC_SEGMENT_C6X_5		5
230 #define KS2_MSMC_SEGMENT_C6X_6		6
231 #define KS2_MSMC_SEGMENT_C6X_7		7
232 
233 #define KS2_MSMC_SEGMENT_DEBUG		12
234 
235 /* KS2 HK/L/E MSMC PRIVIDs  for MSMC2 */
236 #define K2HKLE_MSMC_SEGMENT_ARM		8
237 #define K2HKLE_MSMC_SEGMENT_NETCP	9
238 #define K2HKLE_MSMC_SEGMENT_QM_PDSP	10
239 #define K2HKLE_MSMC_SEGMENT_PCIE0	11
240 
241 /* K2HK specific Privilege ID Settings */
242 #define K2HKE_MSMC_SEGMENT_HYPERLINK	14
243 
244 /* K2L specific Privilege ID Settings */
245 #define K2L_MSMC_SEGMENT_PCIE1		14
246 
247 /* K2E specific Privilege ID Settings */
248 #define K2E_MSMC_SEGMENT_PCIE1		13
249 #define K2E_MSMC_SEGMENT_TSIP		15
250 
251 /* K2G specific Privilege ID Settings */
252 #define K2G_MSMC_SEGMENT_ARM		1
253 #define K2G_MSMC_SEGMENT_ICSS0		2
254 #define K2G_MSMC_SEGMENT_ICSS1		3
255 #define K2G_MSMC_SEGMENT_NSS		4
256 #define K2G_MSMC_SEGMENT_PCIE		5
257 #define K2G_MSMC_SEGMENT_USB		6
258 #define K2G_MSMC_SEGMENT_MLB		8
259 #define K2G_MSMC_SEGMENT_PMMC		9
260 #define K2G_MSMC_SEGMENT_DSS		10
261 #define K2G_MSMC_SEGMENT_MMC		11
262 
263 /* MSMC segment size shift bits */
264 #define KS2_MSMC_SEG_SIZE_SHIFT		12
265 #define KS2_MSMC_MAP_SEG_NUM		(2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
266 #define KS2_MSMC_DST_SEG_BASE		(CONFIG_SYS_LPAE_SDRAM_BASE >> \
267 					KS2_MSMC_SEG_SIZE_SHIFT)
268 
269 /* Device speed */
270 #define KS2_REV1_DEVSPEED		(KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
271 #define KS2_EFUSE_BOOTROM		(KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
272 #define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
273 
274 /* Queue manager */
275 #ifdef CONFIG_SOC_K2G
276 #define KS2_QM_BASE_ADDRESS		0x040C0000
277 #define KS2_QM_CONF_BASE		0x04040000
278 #define KS2_QM_DESC_SETUP_BASE		0x04080000
279 #define KS2_QM_STATUS_RAM_BASE		0x0 /* K2G doesn't have it */
280 #define KS2_QM_INTD_CONF_BASE		0x0
281 #define KS2_QM_PDSP1_CMD_BASE		0x0
282 #define KS2_QM_PDSP1_CTRL_BASE		0x0
283 #define KS2_QM_PDSP1_IRAM_BASE		0x0
284 #define KS2_QM_MANAGER_QUEUES_BASE	0x040c0000
285 #define KS2_QM_MANAGER_Q_PROXY_BASE	0x04040200
286 #define KS2_QM_QUEUE_STATUS_BASE	0x04100000
287 #define KS2_QM_LINK_RAM_BASE		0x04020000
288 #define KS2_QM_REGION_NUM		8
289 #define KS2_QM_QPOOL_NUM		112
290 #else
291 #define KS2_QM_BASE_ADDRESS		0x23a80000
292 #define KS2_QM_CONF_BASE		0x02a02000
293 #define KS2_QM_DESC_SETUP_BASE		0x02a03000
294 #define KS2_QM_STATUS_RAM_BASE		0x02a06000
295 #define KS2_QM_INTD_CONF_BASE		0x02a0c000
296 #define KS2_QM_PDSP1_CMD_BASE		0x02a20000
297 #define KS2_QM_PDSP1_CTRL_BASE		0x02a0f000
298 #define KS2_QM_PDSP1_IRAM_BASE		0x02a10000
299 #define KS2_QM_MANAGER_QUEUES_BASE	0x02a80000
300 #define KS2_QM_MANAGER_Q_PROXY_BASE	0x02ac0000
301 #define KS2_QM_QUEUE_STATUS_BASE	0x02a40000
302 #define KS2_QM_LINK_RAM_BASE		0x00100000
303 #define KS2_QM_REGION_NUM		64
304 #define KS2_QM_QPOOL_NUM		4000
305 #endif
306 
307 /* USB */
308 #define KS2_USB_SS_BASE			0x02680000
309 #define KS2_USB_HOST_XHCI_BASE		(KS2_USB_SS_BASE + 0x10000)
310 #define KS2_DEV_USB_PHY_BASE		0x02620738
311 #define KS2_USB_PHY_CFG_BASE		0x02630000
312 
313 #define KS2_MAC_ID_BASE_ADDR		(KS2_DEVICE_STATE_CTRL_BASE + 0x110)
314 
315 /* SGMII SerDes */
316 #define KS2_SGMII_SERDES_BASE		0x0232a000
317 
318 /* JTAG ID register */
319 #define JTAGID_VARIANT_SHIFT	28
320 #define JTAGID_VARIANT_MASK	(0xf << 28)
321 #define JTAGID_PART_NUM_SHIFT	12
322 #define JTAGID_PART_NUM_MASK	(0xffff << 12)
323 
324 /* PART NUMBER definitions */
325 #define CPU_66AK2Hx	0xb981
326 #define CPU_66AK2Ex	0xb9a6
327 #define CPU_66AK2Lx	0xb9a7
328 #define CPU_66AK2Gx	0xbb06
329 
330 /* Variant definitions */
331 #define CPU_66AK2G1x	0x08
332 
333 /* DEVSPEED register */
334 #define DEVSPEED_DEVSPEED_SHIFT	16
335 #define DEVSPEED_DEVSPEED_MASK	(0xfff << 16)
336 #define DEVSPEED_ARMSPEED_SHIFT	0
337 #define DEVSPEED_ARMSPEED_MASK	0xfff
338 #define DEVSPEED_NUMSPDS	12
339 
340 #ifdef CONFIG_SOC_K2HK
341 #include <asm/arch/hardware-k2hk.h>
342 #endif
343 
344 #ifdef CONFIG_SOC_K2E
345 #include <asm/arch/hardware-k2e.h>
346 #endif
347 
348 #ifdef CONFIG_SOC_K2L
349 #include <asm/arch/hardware-k2l.h>
350 #endif
351 
352 #ifdef CONFIG_SOC_K2G
353 #include <asm/arch/hardware-k2g.h>
354 #endif
355 
356 #ifndef __ASSEMBLY__
357 
get_part_number(void)358 static inline u16 get_part_number(void)
359 {
360 	u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
361 
362 	return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
363 }
364 
cpu_is_k2hk(void)365 static inline u8 cpu_is_k2hk(void)
366 {
367 	return get_part_number() == CPU_66AK2Hx;
368 }
369 
cpu_is_k2e(void)370 static inline u8 cpu_is_k2e(void)
371 {
372 	return get_part_number() == CPU_66AK2Ex;
373 }
374 
cpu_is_k2l(void)375 static inline u8 cpu_is_k2l(void)
376 {
377 	return get_part_number() == CPU_66AK2Lx;
378 }
379 
cpu_is_k2g(void)380 static inline u8 cpu_is_k2g(void)
381 {
382 	return get_part_number() == CPU_66AK2Gx;
383 }
384 
cpu_revision(void)385 static inline u8 cpu_revision(void)
386 {
387 	u32 jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
388 	u8 rev	= (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT;
389 
390 	return rev;
391 }
392 
393 int cpu_to_bus(u32 *ptr, u32 length);
394 void sdelay(unsigned long);
395 
396 #endif
397 
398 #endif /* __ASM_ARCH_HARDWARE_H */
399