1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <log.h>
11 #include <asm/gpio.h>
12 #include <asm/io.h>
13 #include <asm/arch/pinmux.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/mc.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <linux/delay.h>
19 #include <power/as3722.h>
20 #include <power/pmic.h>
21 #include "pinmux-config-nyan-big.h"
22
23 /*
24 * Routine: pinmux_init
25 * Description: Do individual peripheral pinmux configs
26 */
pinmux_init(void)27 void pinmux_init(void)
28 {
29 gpio_config_table(nyan_big_gpio_inits,
30 ARRAY_SIZE(nyan_big_gpio_inits));
31
32 pinmux_config_pingrp_table(nyan_big_pingrps,
33 ARRAY_SIZE(nyan_big_pingrps));
34
35 pinmux_config_drvgrp_table(nyan_big_drvgrps,
36 ARRAY_SIZE(nyan_big_drvgrps));
37 }
38
tegra_board_id(void)39 int tegra_board_id(void)
40 {
41 static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
42 TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
43 -1};
44
45 gpio_claim_vector(vector, "board_id%d");
46 return gpio_get_values_as_int(vector);
47 }
48
tegra_lcd_pmic_init(int board_id)49 int tegra_lcd_pmic_init(int board_id)
50 {
51 struct udevice *dev;
52 int ret;
53
54 ret = uclass_get_device_by_driver(UCLASS_PMIC,
55 DM_DRIVER_GET(pmic_as3722), &dev);
56 if (ret) {
57 debug("%s: Failed to find PMIC\n", __func__);
58 return ret;
59 }
60
61 if (board_id == 0)
62 pmic_reg_write(dev, 0x00, 0x3c);
63 else
64 pmic_reg_write(dev, 0x00, 0x50);
65 pmic_reg_write(dev, 0x12, 0x10);
66 pmic_reg_write(dev, 0x0c, 0x07);
67 pmic_reg_write(dev, 0x20, 0x10);
68
69 return 0;
70 }
71
72 /* Setup required information for Linux kernel */
setup_kernel_info(void)73 static void setup_kernel_info(void)
74 {
75 struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
76
77 /* The kernel graphics driver needs this region locked down */
78 writel(0, &mc->mc_video_protect_bom);
79 writel(0, &mc->mc_video_protect_size_mb);
80 writel(1, &mc->mc_video_protect_reg_ctrl);
81 }
82
83 /*
84 * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
85 * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
86 * Otherwise reading AHUB devices will hang when the kernel boots.
87 */
enable_required_clocks(void)88 static void enable_required_clocks(void)
89 {
90 static enum periph_id ids[] = {
91 PERIPH_ID_I2S0,
92 PERIPH_ID_I2S1,
93 PERIPH_ID_I2S2,
94 PERIPH_ID_I2S3,
95 PERIPH_ID_I2S4,
96 PERIPH_ID_AUDIO,
97 PERIPH_ID_APBIF,
98 PERIPH_ID_DAM0,
99 PERIPH_ID_DAM1,
100 PERIPH_ID_DAM2,
101 PERIPH_ID_AMX0,
102 PERIPH_ID_AMX1,
103 PERIPH_ID_ADX0,
104 PERIPH_ID_ADX1,
105 PERIPH_ID_SPDIF,
106 PERIPH_ID_AFC0,
107 PERIPH_ID_AFC1,
108 PERIPH_ID_AFC2,
109 PERIPH_ID_AFC3,
110 PERIPH_ID_AFC4,
111 PERIPH_ID_AFC5,
112 PERIPH_ID_EXTPERIPH1
113 };
114 int i;
115
116 for (i = 0; i < ARRAY_SIZE(ids); i++)
117 clock_enable(ids[i]);
118 udelay(2);
119 for (i = 0; i < ARRAY_SIZE(ids); i++)
120 reset_set_enable(ids[i], 0);
121 }
122
nvidia_board_init(void)123 int nvidia_board_init(void)
124 {
125 clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
126 clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
127
128 /* For external MAX98090 audio codec */
129 clock_external_output(1);
130 setup_kernel_info();
131 enable_required_clocks();
132
133 return 0;
134 }
135