1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal Mini eMMC0 Configuration
4 *
5 * (C) Copyright 2018-2019, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
9 */
10
11/dts-v1/;
12
13/ {
14	compatible = "xlnx,versal";
15	#address-cells = <2>;
16	#size-cells = <2>;
17	model = "Xilinx Versal MINI eMMC0";
18
19	clk200: clk200 {
20		compatible = "fixed-clock";
21		#clock-cells = <0x0>;
22		clock-frequency = <200000000>;
23	};
24
25	dcc: dcc {
26		compatible = "arm,dcc";
27		status = "okay";
28		u-boot,dm-pre-reloc;
29	};
30
31	amba: amba {
32		u-boot,dm-pre-reloc;
33		compatible = "simple-bus";
34		#address-cells = <0x2>;
35		#size-cells = <0x2>;
36		ranges;
37
38		sdhci0: sdhci@f1040000 {
39			compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
40			status = "okay";
41			non-removable;
42			disable-wp;
43			bus-width = <8>;
44			reg = <0x0 0xf1040000 0x0 0x10000>;
45			clock-names = "clk_xin", "clk_ahb";
46			clocks = <&clk200 &clk200>;
47			xlnx,device_id = <0>;
48			no-1-8-v;
49			xlnx,mio-bank = <0>;
50			#stream-id-cells = <1>;
51		};
52	};
53
54	aliases {
55		serial0 = &dcc;
56		mmc0 = &sdhci0;
57	};
58
59	chosen {
60		stdout-path = "serial0:115200";
61	};
62
63	memory@0 {
64		device_type = "memory";
65		reg = <0x0 0x0 0x0 0x20000000>;
66	};
67};
68