1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
4 *
5 * (C) Copyright 2015 - 2020, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16
17/ {
18	model = "ZynqMP zc1751-xm016-dc2 RevA";
19	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
20
21	aliases {
22		can0 = &can0;
23		can1 = &can1;
24		ethernet0 = &gem2;
25		gpio0 = &gpio;
26		i2c0 = &i2c0;
27		rtc0 = &rtc;
28		serial0 = &uart0;
29		serial1 = &uart1;
30		spi0 = &spi0;
31		spi1 = &spi1;
32		usb0 = &usb1;
33	};
34
35	chosen {
36		bootargs = "earlycon";
37		stdout-path = "serial0:115200n8";
38	};
39
40	memory@0 {
41		device_type = "memory";
42		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
43	};
44};
45
46&can0 {
47	status = "okay";
48	pinctrl-names = "default";
49	pinctrl-0 = <&pinctrl_can0_default>;
50};
51
52&can1 {
53	status = "okay";
54	pinctrl-names = "default";
55	pinctrl-0 = <&pinctrl_can1_default>;
56};
57
58&fpd_dma_chan1 {
59	status = "okay";
60};
61
62&fpd_dma_chan2 {
63	status = "okay";
64};
65
66&fpd_dma_chan3 {
67	status = "okay";
68};
69
70&fpd_dma_chan4 {
71	status = "okay";
72};
73
74&fpd_dma_chan5 {
75	status = "okay";
76};
77
78&fpd_dma_chan6 {
79	status = "okay";
80};
81
82&fpd_dma_chan7 {
83	status = "okay";
84};
85
86&fpd_dma_chan8 {
87	status = "okay";
88};
89
90&gem2 {
91	status = "okay";
92	phy-handle = <&phy0>;
93	phy-mode = "rgmii-id";
94	pinctrl-names = "default";
95	pinctrl-0 = <&pinctrl_gem2_default>;
96	phy0: ethernet-phy@5 {
97		reg = <5>;
98		ti,rx-internal-delay = <0x8>;
99		ti,tx-internal-delay = <0xa>;
100		ti,fifo-depth = <0x1>;
101		ti,dp83867-rxctrl-strap-quirk;
102	};
103};
104
105&gpio {
106	status = "okay";
107};
108
109&i2c0 {
110	status = "okay";
111	clock-frequency = <400000>;
112	pinctrl-names = "default", "gpio";
113	pinctrl-0 = <&pinctrl_i2c0_default>;
114	pinctrl-1 = <&pinctrl_i2c0_gpio>;
115	scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
116	sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
117
118	tca6416_u26: gpio@20 {
119		compatible = "ti,tca6416";
120		reg = <0x20>;
121		gpio-controller;
122		#gpio-cells = <2>;
123		/* IRQ not connected */
124	};
125
126	rtc@68 {
127		compatible = "dallas,ds1339";
128		reg = <0x68>;
129	};
130};
131
132&nand0 {
133	status = "okay";
134	pinctrl-names = "default";
135	pinctrl-0 = <&pinctrl_nand0_default>;
136	arasan,has-mdma;
137
138	nand@0 {
139		reg = <0x0>;
140		#address-cells = <0x2>;
141		#size-cells = <0x1>;
142		nand-ecc-mode = "soft";
143		nand-ecc-algo = "bch";
144		nand-rb = <0>;
145		label = "main-storage-0";
146
147		partition@0 {	/* for testing purpose */
148			label = "nand-fsbl-uboot";
149			reg = <0x0 0x0 0x400000>;
150		};
151		partition@1 {	/* for testing purpose */
152			label = "nand-linux";
153			reg = <0x0 0x400000 0x1400000>;
154		};
155		partition@2 {	/* for testing purpose */
156			label = "nand-device-tree";
157			reg = <0x0 0x1800000 0x400000>;
158		};
159		partition@3 {	/* for testing purpose */
160			label = "nand-rootfs";
161			reg = <0x0 0x1c00000 0x1400000>;
162		};
163		partition@4 {	/* for testing purpose */
164			label = "nand-bitstream";
165			reg = <0x0 0x3000000 0x400000>;
166		};
167		partition@5 {	/* for testing purpose */
168			label = "nand-misc";
169			reg = <0x0 0x3400000 0xfcc00000>;
170		};
171	};
172	nand@1 {
173		reg = <0x1>;
174		#address-cells = <0x2>;
175		#size-cells = <0x1>;
176		nand-ecc-mode = "soft";
177		nand-ecc-algo = "bch";
178		nand-rb = <0>;
179		label = "main-storage-1";
180
181		partition@0 {	/* for testing purpose */
182			label = "nand1-fsbl-uboot";
183			reg = <0x0 0x0 0x400000>;
184		};
185		partition@1 {	/* for testing purpose */
186			label = "nand1-linux";
187			reg = <0x0 0x400000 0x1400000>;
188		};
189		partition@2 {	/* for testing purpose */
190			label = "nand1-device-tree";
191			reg = <0x0 0x1800000 0x400000>;
192		};
193		partition@3 {	/* for testing purpose */
194			label = "nand1-rootfs";
195			reg = <0x0 0x1c00000 0x1400000>;
196		};
197		partition@4 {	/* for testing purpose */
198			label = "nand1-bitstream";
199			reg = <0x0 0x3000000 0x400000>;
200		};
201		partition@5 {	/* for testing purpose */
202			label = "nand1-misc";
203			reg = <0x0 0x3400000 0xfcc00000>;
204		};
205	};
206};
207
208&pinctrl0 {
209	status = "okay";
210	pinctrl_can0_default: can0-default {
211		mux {
212			function = "can0";
213			groups = "can0_9_grp";
214		};
215
216		conf {
217			groups = "can0_9_grp";
218			slew-rate = <SLEW_RATE_SLOW>;
219			power-source = <IO_STANDARD_LVCMOS18>;
220		};
221
222		conf-rx {
223			pins = "MIO38";
224			bias-high-impedance;
225		};
226
227		conf-tx {
228			pins = "MIO39";
229			bias-disable;
230		};
231	};
232
233	pinctrl_can1_default: can1-default {
234		mux {
235			function = "can1";
236			groups = "can1_8_grp";
237		};
238
239		conf {
240			groups = "can1_8_grp";
241			slew-rate = <SLEW_RATE_SLOW>;
242			power-source = <IO_STANDARD_LVCMOS18>;
243		};
244
245		conf-rx {
246			pins = "MIO33";
247			bias-high-impedance;
248		};
249
250		conf-tx {
251			pins = "MIO32";
252			bias-disable;
253		};
254	};
255
256	pinctrl_i2c0_default: i2c0-default {
257		mux {
258			groups = "i2c0_1_grp";
259			function = "i2c0";
260		};
261
262		conf {
263			groups = "i2c0_1_grp";
264			bias-pull-up;
265			slew-rate = <SLEW_RATE_SLOW>;
266			power-source = <IO_STANDARD_LVCMOS18>;
267		};
268	};
269
270	pinctrl_i2c0_gpio: i2c0-gpio {
271		mux {
272			groups = "gpio0_6_grp", "gpio0_7_grp";
273			function = "gpio0";
274		};
275
276		conf {
277			groups = "gpio0_6_grp", "gpio0_7_grp";
278			slew-rate = <SLEW_RATE_SLOW>;
279			power-source = <IO_STANDARD_LVCMOS18>;
280		};
281	};
282
283	pinctrl_uart0_default: uart0-default {
284		mux {
285			groups = "uart0_10_grp";
286			function = "uart0";
287		};
288
289		conf {
290			groups = "uart0_10_grp";
291			slew-rate = <SLEW_RATE_SLOW>;
292			power-source = <IO_STANDARD_LVCMOS18>;
293		};
294
295		conf-rx {
296			pins = "MIO42";
297			bias-high-impedance;
298		};
299
300		conf-tx {
301			pins = "MIO43";
302			bias-disable;
303		};
304	};
305
306	pinctrl_uart1_default: uart1-default {
307		mux {
308			groups = "uart1_10_grp";
309			function = "uart1";
310		};
311
312		conf {
313			groups = "uart1_10_grp";
314			slew-rate = <SLEW_RATE_SLOW>;
315			power-source = <IO_STANDARD_LVCMOS18>;
316		};
317
318		conf-rx {
319			pins = "MIO41";
320			bias-high-impedance;
321		};
322
323		conf-tx {
324			pins = "MIO40";
325			bias-disable;
326		};
327	};
328
329	pinctrl_usb1_default: usb1-default {
330		mux {
331			groups = "usb1_0_grp";
332			function = "usb1";
333		};
334
335		conf {
336			groups = "usb1_0_grp";
337			slew-rate = <SLEW_RATE_SLOW>;
338			power-source = <IO_STANDARD_LVCMOS18>;
339		};
340
341		conf-rx {
342			pins = "MIO64", "MIO65", "MIO67";
343			bias-high-impedance;
344		};
345
346		conf-tx {
347			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
348			       "MIO72", "MIO73", "MIO74", "MIO75";
349			bias-disable;
350		};
351	};
352
353	pinctrl_gem2_default: gem2-default {
354		mux {
355			function = "ethernet2";
356			groups = "ethernet2_0_grp";
357		};
358
359		conf {
360			groups = "ethernet2_0_grp";
361			slew-rate = <SLEW_RATE_SLOW>;
362			power-source = <IO_STANDARD_LVCMOS18>;
363		};
364
365		conf-rx {
366			pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
367									"MIO63";
368			bias-high-impedance;
369			low-power-disable;
370		};
371
372		conf-tx {
373			pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
374									"MIO57";
375			bias-disable;
376			low-power-enable;
377		};
378
379		mux-mdio {
380			function = "mdio2";
381			groups = "mdio2_0_grp";
382		};
383
384		conf-mdio {
385			groups = "mdio2_0_grp";
386			slew-rate = <SLEW_RATE_SLOW>;
387			power-source = <IO_STANDARD_LVCMOS18>;
388			bias-disable;
389		};
390	};
391
392	pinctrl_nand0_default: nand0-default {
393		mux {
394			groups = "nand0_0_grp";
395			function = "nand0";
396		};
397
398		conf {
399			groups = "nand0_0_grp";
400			bias-pull-up;
401		};
402
403		mux-ce {
404			groups = "nand0_ce_0_grp";
405			function = "nand0_ce";
406		};
407
408		conf-ce {
409			groups = "nand0_ce_0_grp";
410			bias-pull-up;
411		};
412
413		mux-rb {
414			groups = "nand0_rb_0_grp";
415			function = "nand0_rb";
416		};
417
418		conf-rb {
419			groups = "nand0_rb_0_grp";
420			bias-pull-up;
421		};
422
423		mux-dqs {
424			groups = "nand0_dqs_0_grp";
425			function = "nand0_dqs";
426		};
427
428		conf-dqs {
429			groups = "nand0_dqs_0_grp";
430			bias-pull-up;
431		};
432	};
433
434	pinctrl_spi0_default: spi0-default {
435		mux {
436			groups = "spi0_0_grp";
437			function = "spi0";
438		};
439
440		conf {
441			groups = "spi0_0_grp";
442			bias-disable;
443			slew-rate = <SLEW_RATE_SLOW>;
444			power-source = <IO_STANDARD_LVCMOS18>;
445		};
446
447		mux-cs {
448			groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
449							"spi0_ss_2_grp";
450			function = "spi0_ss";
451		};
452
453		conf-cs {
454			groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
455							"spi0_ss_2_grp";
456			bias-disable;
457		};
458	};
459
460	pinctrl_spi1_default: spi1-default {
461		mux {
462			groups = "spi1_3_grp";
463			function = "spi1";
464		};
465
466		conf {
467			groups = "spi1_3_grp";
468			bias-disable;
469			slew-rate = <SLEW_RATE_SLOW>;
470			power-source = <IO_STANDARD_LVCMOS18>;
471		};
472
473		mux-cs {
474			groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
475							"spi1_ss_11_grp";
476			function = "spi1_ss";
477		};
478
479		conf-cs {
480			groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
481							"spi1_ss_11_grp";
482			bias-disable;
483		};
484	};
485};
486
487&rtc {
488	status = "okay";
489};
490
491&spi0 {
492	status = "okay";
493	num-cs = <1>;
494	pinctrl-names = "default";
495	pinctrl-0 = <&pinctrl_spi0_default>;
496
497	spi0_flash0: flash@0 {
498		#address-cells = <1>;
499		#size-cells = <1>;
500		compatible = "sst,sst25wf080", "jedec,spi-nor";
501		spi-max-frequency = <50000000>;
502		reg = <0>;
503
504		partition@0 {
505			label = "spi0-data";
506			reg = <0x0 0x100000>;
507		};
508	};
509};
510
511&spi1 {
512	status = "okay";
513	num-cs = <1>;
514	pinctrl-names = "default";
515	pinctrl-0 = <&pinctrl_spi1_default>;
516
517	spi1_flash0: flash@0 {
518		#address-cells = <1>;
519		#size-cells = <1>;
520		compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
521		spi-max-frequency = <20000000>;
522		reg = <0>;
523
524		partition@0 {
525			label = "spi1-data";
526			reg = <0x0 0x84000>;
527		};
528	};
529};
530
531/* ULPI SMSC USB3320 */
532&usb1 {
533	status = "okay";
534	pinctrl-names = "default";
535	pinctrl-0 = <&pinctrl_usb1_default>;
536};
537
538&dwc3_1 {
539	status = "okay";
540	dr_mode = "host";
541};
542
543&uart0 {
544	status = "okay";
545	pinctrl-names = "default";
546	pinctrl-0 = <&pinctrl_uart0_default>;
547};
548
549&uart1 {
550	status = "okay";
551	pinctrl-names = "default";
552	pinctrl-0 = <&pinctrl_uart1_default>;
553};
554