1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef LPDDR4_IF_H 10 #define LPDDR4_IF_H 11 12 #include <linux/types.h> 13 #ifdef CONFIG_K3_AM64_DDRSS 14 #include <lpddr4_16bit_if.h> 15 #else 16 #include <lpddr4_32bit_if.h> 17 #endif 18 19 typedef struct lpddr4_config_s lpddr4_config; 20 typedef struct lpddr4_privatedata_s lpddr4_privatedata; 21 typedef struct lpddr4_debuginfo_s lpddr4_debuginfo; 22 typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs; 23 24 typedef enum { 25 LPDDR4_CTL_REGS = 0U, 26 LPDDR4_PHY_REGS = 1U, 27 LPDDR4_PHY_INDEP_REGS = 2U 28 } lpddr4_regblock; 29 30 typedef enum { 31 LPDDR4_DRV_NONE = 0U, 32 LPDDR4_DRV_SOC_PLL_UPDATE = 1U 33 } lpddr4_infotype; 34 35 typedef enum { 36 LPDDR4_LPI_PD_WAKEUP_FN = 0U, 37 LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U, 38 LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U, 39 LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U, 40 LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U, 41 LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U, 42 LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U 43 } lpddr4_lpiwakeupparam; 44 45 typedef enum { 46 LPDDR4_REDUC_ON = 0U, 47 LPDDR4_REDUC_OFF = 1U 48 } lpddr4_reducmode; 49 50 typedef enum { 51 LPDDR4_ECC_DISABLED = 0U, 52 LPDDR4_ECC_ENABLED = 1U, 53 LPDDR4_ECC_ERR_DETECT = 2U, 54 LPDDR4_ECC_ERR_DETECT_CORRECT = 3U 55 } lpddr4_eccenable; 56 57 typedef enum { 58 LPDDR4_DBI_RD_ON = 0U, 59 LPDDR4_DBI_RD_OFF = 1U, 60 LPDDR4_DBI_WR_ON = 2U, 61 LPDDR4_DBI_WR_OFF = 3U 62 } lpddr4_dbimode; 63 64 typedef enum { 65 LPDDR4_FSP_0 = 0U, 66 LPDDR4_FSP_1 = 1U, 67 LPDDR4_FSP_2 = 2U 68 } lpddr4_ctlfspnum; 69 70 typedef void (*lpddr4_infocallback)(const lpddr4_privatedata *pd, lpddr4_infotype infotype); 71 72 typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt ctlinterrupt, u8 chipselect); 73 74 typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt phyindepinterrupt, u8 chipselect); 75 76 u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize); 77 78 u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg); 79 80 u32 lpddr4_start(const lpddr4_privatedata *pd); 81 82 u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue); 83 84 u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue); 85 86 u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus); 87 88 u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus); 89 90 u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 91 92 u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 93 94 u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 95 96 u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 97 98 u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 99 100 u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 101 102 u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask); 103 104 u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask); 105 106 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus); 107 108 u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr); 109 110 u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask); 111 112 u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask); 113 114 u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus); 115 116 u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr); 117 118 u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo); 119 120 u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles); 121 122 u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles); 123 124 u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam); 125 126 u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam); 127 128 u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode); 129 130 u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); 131 132 u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off); 133 134 u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off); 135 136 u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode); 137 138 u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max); 139 140 u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); 141 142 u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval); 143 144 #endif /* LPDDR4_IF_H */ 145