1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013 Samsung Electronics 4 * Piotr Wilczek <p.wilczek@samsung.com> 5 */ 6 7 #ifndef __MAX77693_MUIC_H_ 8 #define __MAX77693_MUIC_H_ 9 10 #include <power/power_chrg.h> 11 12 /* 13 * MUIC REGISTER 14 */ 15 16 #define MAX77693_MUIC_PREFIX "max77693-muic:" 17 18 /* MAX77693_MUIC_STATUS1 */ 19 #define MAX77693_MUIC_ADC_MASK 0x1F 20 21 /* MAX77693_MUIC_STATUS2 */ 22 #define MAX77693_MUIC_CHG_NO 0x00 23 #define MAX77693_MUIC_CHG_USB 0x01 24 #define MAX77693_MUIC_CHG_USB_D 0x02 25 #define MAX77693_MUIC_CHG_TA 0x03 26 #define MAX77693_MUIC_CHG_TA_500 0x04 27 #define MAX77693_MUIC_CHG_TA_1A 0x05 28 #define MAX77693_MUIC_CHG_MASK 0x07 29 30 /* MAX77693_MUIC_CONTROL1 */ 31 #define MAX77693_MUIC_CTRL1_DN1DP2 ((0x1 << 3) | 0x1) 32 #define MAX77693_MUIC_CTRL1_UT1UR2 ((0x3 << 3) | 0x3) 33 #define MAX77693_MUIC_CTRL1_ADN1ADP2 ((0x4 << 3) | 0x4) 34 #define MAX77693_MUIC_CTRL1_AUT1AUR2 ((0x5 << 3) | 0x5) 35 #define MAX77693_MUIC_CTRL1_MASK 0xC0 36 37 #define MUIC_PATH_USB 0 38 #define MUIC_PATH_UART 1 39 40 #define MUIC_PATH_CP 0 41 #define MUIC_PATH_AP 1 42 43 enum muic_path { 44 MUIC_PATH_USB_CP, 45 MUIC_PATH_USB_AP, 46 MUIC_PATH_UART_CP, 47 MUIC_PATH_UART_AP, 48 }; 49 50 /* MAX 777693 MUIC registers */ 51 enum { 52 MAX77693_MUIC_ID = 0x00, 53 MAX77693_MUIC_INT1 = 0x01, 54 MAX77693_MUIC_INT2 = 0x02, 55 MAX77693_MUIC_INT3 = 0x03, 56 MAX77693_MUIC_STATUS1 = 0x04, 57 MAX77693_MUIC_STATUS2 = 0x05, 58 MAX77693_MUIC_STATUS3 = 0x06, 59 MAX77693_MUIC_INTMASK1 = 0x07, 60 MAX77693_MUIC_INTMASK2 = 0x08, 61 MAX77693_MUIC_INTMASK3 = 0x09, 62 MAX77693_MUIC_CDETCTRL = 0x0A, 63 MAX77693_MUIC_CONTROL1 = 0x0C, 64 MAX77693_MUIC_CONTROL2 = 0x0D, 65 MAX77693_MUIC_CONTROL3 = 0x0E, 66 67 MUIC_NUM_OF_REGS = 0x0F, 68 }; 69 70 #define MAX77693_MUIC_I2C_ADDR (0x4A >> 1) 71 72 int power_muic_init(unsigned int bus); 73 #endif /* __MAX77693_MUIC_H_ */ 74