1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2020 Marvell International Ltd.
4 */
5
6 #ifndef __CVMX_GSERX_DEFS_H__
7 #define __CVMX_GSERX_DEFS_H__
8
9 #define CVMX_GSERX_DLMX_TX_AMPLITUDE(offset, block_id) (0x0001180090003008ull)
10 #define CVMX_GSERX_DLMX_TX_PREEMPH(offset, block_id) (0x0001180090003028ull)
11 #define CVMX_GSERX_DLMX_MPLL_EN(offset, block_id) (0x0001180090001020ull)
12 #define CVMX_GSERX_DLMX_REF_SSP_EN(offset, block_id) (0x0001180090001048ull)
13 #define CVMX_GSERX_DLMX_TX_RATE(offset, block_id) (0x0001180090003030ull)
14 #define CVMX_GSERX_DLMX_TX_EN(offset, block_id) (0x0001180090003020ull)
15 #define CVMX_GSERX_DLMX_TX_CM_EN(offset, block_id) (0x0001180090003010ull)
16 #define CVMX_GSERX_DLMX_TX_RESET(offset, block_id) (0x0001180090003038ull)
17 #define CVMX_GSERX_DLMX_TX_DATA_EN(offset, block_id) (0x0001180090003018ull)
18 #define CVMX_GSERX_DLMX_RX_RATE(offset, block_id) (0x0001180090002028ull)
19 #define CVMX_GSERX_DLMX_RX_PLL_EN(offset, block_id) (0x0001180090002020ull)
20 #define CVMX_GSERX_DLMX_RX_DATA_EN(offset, block_id) (0x0001180090002008ull)
21 #define CVMX_GSERX_DLMX_RX_RESET(offset, block_id) (0x0001180090002030ull)
22
23 #define CVMX_GSERX_DLMX_TX_STATUS(offset, block_id) \
24 (0x0001180090003000ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
25 #define CVMX_GSERX_DLMX_RX_STATUS(offset, block_id) \
26 (0x0001180090002000ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
27
CVMX_GSERX_SATA_STATUS(unsigned long offset)28 static inline u64 CVMX_GSERX_SATA_STATUS(unsigned long offset)
29 {
30 switch (cvmx_get_octeon_family()) {
31 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
32 return 0x0001180090100200ull + (offset) * 0x1000000ull;
33 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
34 return 0x0001180090100900ull + (offset) * 0x1000000ull;
35 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
36 return 0x0001180090100900ull + (offset) * 0x1000000ull;
37 }
38 return 0x0001180090100900ull + (offset) * 0x1000000ull;
39 }
40
41 #define CVMX_GSERX_DLMX_RX_EQ(offset, block_id) \
42 (0x0001180090002010ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
43 #define CVMX_GSERX_DLMX_REF_USE_PAD(offset, block_id) \
44 (0x0001180090001050ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
45 #define CVMX_GSERX_DLMX_REFCLK_SEL(offset, block_id) \
46 (0x0001180090000008ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
47 #define CVMX_GSERX_DLMX_PHY_RESET(offset, block_id) \
48 (0x0001180090001038ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
49 #define CVMX_GSERX_DLMX_TEST_POWERDOWN(offset, block_id) \
50 (0x0001180090001060ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
51 #define CVMX_GSERX_DLMX_REF_CLKDIV2(offset, block_id) \
52 (0x0001180090001040ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
53 #define CVMX_GSERX_DLMX_MPLL_MULTIPLIER(offset, block_id) \
54 (0x0001180090001030ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
55 #define CVMX_GSERX_DLMX_MPLL_STATUS(offset, block_id) \
56 (0x0001180090001000ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
57
58 #define CVMX_GSERX_BR_RXX_CTL(offset, block_id) \
59 (0x0001180090000400ull + (((offset) & 3) + ((block_id) & 15) * 0x20000ull) * 128)
60 #define CVMX_GSERX_BR_RXX_EER(offset, block_id) \
61 (0x0001180090000418ull + (((offset) & 3) + ((block_id) & 15) * 0x20000ull) * 128)
62
63 #define CVMX_GSERX_PCIE_PIPE_PORT_SEL(offset) (0x0001180090080460ull)
64 #define CVMX_GSERX_PCIE_PIPE_RST(offset) (0x0001180090080448ull)
65
66 #define CVMX_GSERX_SATA_CFG(offset) (0x0001180090100208ull)
67 #define CVMX_GSERX_SATA_REF_SSP_EN(offset) (0x0001180090100600ull)
68
CVMX_GSERX_SATA_LANE_RST(unsigned long offset)69 static inline u64 CVMX_GSERX_SATA_LANE_RST(unsigned long offset)
70 {
71 switch (cvmx_get_octeon_family()) {
72 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
73 return 0x0001180090100210ull + (offset) * 0x1000000ull;
74 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
75 return 0x0001180090000908ull + (offset) * 0x1000000ull;
76 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
77 return 0x0001180090000908ull + (offset) * 0x1000000ull;
78 }
79 return 0x0001180090000908ull + (offset) * 0x1000000ull;
80 }
81
82 #define CVMX_GSERX_EQ_WAIT_TIME(offset) (0x00011800904E0000ull + ((offset) & 15) * 0x1000000ull)
83
84 #define CVMX_GSERX_GLBL_MISC_CONFIG_1(offset) (0x0001180090460030ull + ((offset) & 15) * 0x1000000ull)
85 #define CVMX_GSERX_GLBL_PLL_CFG_3(offset) (0x0001180090460018ull + ((offset) & 15) * 0x1000000ull)
86
87 #define CVMX_GSERX_PHYX_OVRD_IN_LO(offset, block_id) \
88 (0x0001180090400088ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 524288)
89
90 #define CVMX_GSERX_RX_PWR_CTRL_P1(offset) (0x00011800904600B0ull + ((offset) & 15) * 0x1000000ull)
91 #define CVMX_GSERX_RX_PWR_CTRL_P2(offset) (0x00011800904600B8ull + ((offset) & 15) * 0x1000000ull)
92 #define CVMX_GSERX_RX_EIE_DETSTS(offset) (0x0001180090000150ull + ((offset) & 15) * 0x1000000ull)
93
94 #define CVMX_GSERX_LANE_MODE(offset) (0x0001180090000118ull + ((offset) & 15) * 0x1000000ull)
95
96 #define CVMX_GSERX_LANE_VMA_FINE_CTRL_0(offset) \
97 (0x00011800904E01C8ull + ((offset) & 15) * 0x1000000ull)
98
99 #define CVMX_GSERX_LANEX_LBERT_CFG(offset, block_id) \
100 (0x00011800904C0020ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
101
102 #define CVMX_GSERX_LANEX_MISC_CFG_0(offset, block_id) \
103 (0x00011800904C0000ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
104
105 #define CVMX_GSERX_LANE_PX_MODE_0(offset, block_id) \
106 (0x00011800904E0040ull + (((offset) & 15) + ((block_id) & 15) * 0x80000ull) * 32)
107 #define CVMX_GSERX_LANE_PX_MODE_1(offset, block_id) \
108 (0x00011800904E0048ull + (((offset) & 15) + ((block_id) & 15) * 0x80000ull) * 32)
109
110 #define CVMX_GSERX_LANEX_RX_CFG_0(offset, block_id) \
111 (0x0001180090440000ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
112 #define CVMX_GSERX_LANEX_RX_CFG_1(offset, block_id) \
113 (0x0001180090440008ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
114 #define CVMX_GSERX_LANEX_RX_CFG_2(offset, block_id) \
115 (0x0001180090440010ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
116 #define CVMX_GSERX_LANEX_RX_CFG_3(offset, block_id) \
117 (0x0001180090440018ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
118 #define CVMX_GSERX_LANEX_RX_CFG_4(offset, block_id) \
119 (0x0001180090440020ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
120 #define CVMX_GSERX_LANEX_RX_CFG_5(offset, block_id) \
121 (0x0001180090440028ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
122 #define CVMX_GSERX_LANEX_RX_CTLE_CTRL(offset, block_id) \
123 (0x0001180090440058ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
124
125 #define CVMX_GSERX_LANEX_RX_LOOP_CTRL(offset, block_id) \
126 (0x0001180090440048ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
127 #define CVMX_GSERX_LANEX_RX_VALBBD_CTRL_0(offset, block_id) \
128 (0x0001180090440240ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
129 #define CVMX_GSERX_LANEX_RX_VALBBD_CTRL_1(offset, block_id) \
130 (0x0001180090440248ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
131 #define CVMX_GSERX_LANEX_RX_VALBBD_CTRL_2(offset, block_id) \
132 (0x0001180090440250ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
133 #define CVMX_GSERX_LANEX_RX_MISC_OVRRD(offset, block_id) \
134 (0x0001180090440258ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
135
136 #define CVMX_GSERX_LANEX_TX_CFG_0(offset, block_id) \
137 (0x00011800904400A8ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
138 #define CVMX_GSERX_LANEX_TX_CFG_1(offset, block_id) \
139 (0x00011800904400B0ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
140 #define CVMX_GSERX_LANEX_TX_CFG_2(offset, block_id) \
141 (0x00011800904400B8ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
142 #define CVMX_GSERX_LANEX_TX_CFG_3(offset, block_id) \
143 (0x00011800904400C0ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
144 #define CVMX_GSERX_LANEX_TX_PRE_EMPHASIS(offset, block_id) \
145 (0x00011800904400C8ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
146
147 #define CVMX_GSERX_RX_TXDIR_CTRL_0(offset) (0x00011800904600E8ull + ((offset) & 15) * 0x1000000ull)
148 #define CVMX_GSERX_RX_TXDIR_CTRL_1(offset) (0x00011800904600F0ull + ((offset) & 15) * 0x1000000ull)
149 #define CVMX_GSERX_RX_TXDIR_CTRL_2(offset) (0x00011800904600F8ull + ((offset) & 15) * 0x1000000ull)
150
151 #define CVMX_GSERX_LANEX_PCS_CTLIFC_0(offset, block_id) \
152 (0x00011800904C0060ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
153 #define CVMX_GSERX_LANEX_PCS_CTLIFC_1(offset, block_id) \
154 (0x00011800904C0068ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
155 #define CVMX_GSERX_LANEX_PCS_CTLIFC_2(offset, block_id) \
156 (0x00011800904C0070ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
157
158 #define CVMX_GSERX_LANEX_PWR_CTRL(offset, block_id) \
159 (0x00011800904400D8ull + (((offset) & 3) + ((block_id) & 15) * 0x10ull) * 1048576)
160
161 #define CVMX_GSERX_LANE_VMA_FINE_CTRL_2(offset) \
162 (0x00011800904E01D8ull + ((offset) & 15) * 0x1000000ull)
163
164 #define CVMX_GSERX_PLL_STAT(offset) (0x0001180090000010ull + ((offset) & 15) * 0x1000000ull)
165 #define CVMX_GSERX_QLM_STAT(offset) (0x00011800900000A0ull + ((offset) & 15) * 0x1000000ull)
166
167 #define CVMX_GSERX_PLL_PX_MODE_0(offset, block_id) \
168 (0x00011800904E0030ull + (((offset) & 15) + ((block_id) & 15) * 0x80000ull) * 32)
169 #define CVMX_GSERX_PLL_PX_MODE_1(offset, block_id) \
170 (0x00011800904E0038ull + (((offset) & 15) + ((block_id) & 15) * 0x80000ull) * 32)
171
172 #define CVMX_GSERX_SLICE_CFG(offset) (0x0001180090460060ull + ((offset) & 15) * 0x1000000ull)
173
174 #define CVMX_GSERX_SLICEX_PCIE1_MODE(offset, block_id) \
175 (0x0001180090460228ull + (((offset) & 1) + ((block_id) & 15) * 0x8ull) * 2097152)
176 #define CVMX_GSERX_SLICEX_PCIE2_MODE(offset, block_id) \
177 (0x0001180090460230ull + (((offset) & 1) + ((block_id) & 15) * 0x8ull) * 2097152)
178 #define CVMX_GSERX_SLICEX_PCIE3_MODE(offset, block_id) \
179 (0x0001180090460238ull + (((offset) & 1) + ((block_id) & 15) * 0x8ull) * 2097152)
180 #define CVMX_GSERX_SLICEX_RX_SDLL_CTRL(offset, block_id) \
181 (0x0001180090460220ull + (((offset) & 1) + ((block_id) & 15) * 0x8ull) * 2097152)
182
183 #define CVMX_GSERX_REFCLK_SEL(offset) (0x0001180090000008ull + ((offset) & 15) * 0x1000000ull)
184 #define CVMX_GSERX_PHY_CTL(offset) (0x0001180090000000ull + ((offset) & 15) * 0x1000000ull)
185 #define CVMX_GSERX_CFG(offset) (0x0001180090000080ull + ((offset) & 15) * 0x1000000ull)
186
187 /**
188 * cvmx_gser#_cfg
189 */
190 union cvmx_gserx_cfg {
191 u64 u64;
192 struct cvmx_gserx_cfg_s {
193 u64 reserved_9_63 : 55;
194 u64 rmac_pipe : 1;
195 u64 rmac : 1;
196 u64 srio : 1;
197 u64 sata : 1;
198 u64 bgx_quad : 1;
199 u64 bgx_dual : 1;
200 u64 bgx : 1;
201 u64 ila : 1;
202 u64 pcie : 1;
203 } s;
204 struct cvmx_gserx_cfg_cn73xx {
205 u64 reserved_6_63 : 58;
206 u64 sata : 1;
207 u64 bgx_quad : 1;
208 u64 bgx_dual : 1;
209 u64 bgx : 1;
210 u64 ila : 1;
211 u64 pcie : 1;
212 } cn73xx;
213 struct cvmx_gserx_cfg_cn78xx {
214 u64 reserved_5_63 : 59;
215 u64 bgx_quad : 1;
216 u64 bgx_dual : 1;
217 u64 bgx : 1;
218 u64 ila : 1;
219 u64 pcie : 1;
220 } cn78xx;
221 struct cvmx_gserx_cfg_cn78xx cn78xxp1;
222 struct cvmx_gserx_cfg_s cnf75xx;
223 };
224
225 typedef union cvmx_gserx_cfg cvmx_gserx_cfg_t;
226
227 /**
228 * cvmx_gser#_eq_wait_time
229 *
230 * These registers are for diagnostic use only.
231 * These registers are reset by hardware only during chip cold reset.
232 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
233 */
234 union cvmx_gserx_eq_wait_time {
235 u64 u64;
236 struct cvmx_gserx_eq_wait_time_s {
237 u64 reserved_8_63 : 56;
238 u64 rxeq_wait_cnt : 4;
239 u64 txeq_wait_cnt : 4;
240 } s;
241 struct cvmx_gserx_eq_wait_time_s cn73xx;
242 struct cvmx_gserx_eq_wait_time_s cn78xx;
243 struct cvmx_gserx_eq_wait_time_s cn78xxp1;
244 struct cvmx_gserx_eq_wait_time_s cnf75xx;
245 };
246
247 typedef union cvmx_gserx_eq_wait_time cvmx_gserx_eq_wait_time_t;
248
249 /**
250 * cvmx_gser#_glbl_misc_config_1
251 *
252 * These registers are for diagnostic use only.
253 * These registers are reset by hardware only during chip cold reset.
254 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
255 */
256 union cvmx_gserx_glbl_misc_config_1 {
257 u64 u64;
258 struct cvmx_gserx_glbl_misc_config_1_s {
259 u64 reserved_10_63 : 54;
260 u64 pcs_sds_vref_tr : 4;
261 u64 pcs_sds_trim_chp_reg : 2;
262 u64 pcs_sds_vco_reg_tr : 2;
263 u64 pcs_sds_cvbg_en : 1;
264 u64 pcs_sds_extvbg_en : 1;
265 } s;
266 struct cvmx_gserx_glbl_misc_config_1_s cn73xx;
267 struct cvmx_gserx_glbl_misc_config_1_s cn78xx;
268 struct cvmx_gserx_glbl_misc_config_1_s cn78xxp1;
269 struct cvmx_gserx_glbl_misc_config_1_s cnf75xx;
270 };
271
272 typedef union cvmx_gserx_glbl_misc_config_1 cvmx_gserx_glbl_misc_config_1_t;
273
274 /**
275 * cvmx_gser#_glbl_pll_cfg_3
276 *
277 * These registers are for diagnostic use only.
278 * These registers are reset by hardware only during chip cold reset.
279 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
280 */
281 union cvmx_gserx_glbl_pll_cfg_3 {
282 u64 u64;
283 struct cvmx_gserx_glbl_pll_cfg_3_s {
284 u64 reserved_10_63 : 54;
285 u64 pcs_sds_pll_vco_amp : 2;
286 u64 pll_bypass_uq : 1;
287 u64 pll_vctrl_sel_ovrrd_en : 1;
288 u64 pll_vctrl_sel_ovrrd_val : 2;
289 u64 pll_vctrl_sel_lcvco_val : 2;
290 u64 pll_vctrl_sel_rovco_val : 2;
291 } s;
292 struct cvmx_gserx_glbl_pll_cfg_3_s cn73xx;
293 struct cvmx_gserx_glbl_pll_cfg_3_s cn78xx;
294 struct cvmx_gserx_glbl_pll_cfg_3_s cn78xxp1;
295 struct cvmx_gserx_glbl_pll_cfg_3_s cnf75xx;
296 };
297
298 typedef union cvmx_gserx_glbl_pll_cfg_3 cvmx_gserx_glbl_pll_cfg_3_t;
299
300 /**
301 * cvmx_gser#_dlm#_rx_data_en
302 *
303 * DLM Receiver Enable.
304 *
305 */
306 union cvmx_gserx_dlmx_rx_data_en {
307 u64 u64;
308 struct cvmx_gserx_dlmx_rx_data_en_s {
309 u64 reserved_9_63 : 55;
310 u64 rx1_data_en : 1;
311 u64 reserved_1_7 : 7;
312 u64 rx0_data_en : 1;
313 } s;
314 struct cvmx_gserx_dlmx_rx_data_en_s cn70xx;
315 struct cvmx_gserx_dlmx_rx_data_en_s cn70xxp1;
316 };
317
318 typedef union cvmx_gserx_dlmx_rx_data_en cvmx_gserx_dlmx_rx_data_en_t;
319
320 /**
321 * cvmx_gser#_dlm#_rx_pll_en
322 *
323 * DLM0 DPLL Enable.
324 *
325 */
326 union cvmx_gserx_dlmx_rx_pll_en {
327 u64 u64;
328 struct cvmx_gserx_dlmx_rx_pll_en_s {
329 u64 reserved_9_63 : 55;
330 u64 rx1_pll_en : 1;
331 u64 reserved_1_7 : 7;
332 u64 rx0_pll_en : 1;
333 } s;
334 struct cvmx_gserx_dlmx_rx_pll_en_s cn70xx;
335 struct cvmx_gserx_dlmx_rx_pll_en_s cn70xxp1;
336 };
337
338 typedef union cvmx_gserx_dlmx_rx_pll_en cvmx_gserx_dlmx_rx_pll_en_t;
339
340 /**
341 * cvmx_gser#_dlm#_rx_rate
342 *
343 * DLM0 Rx Data Rate.
344 *
345 */
346 union cvmx_gserx_dlmx_rx_rate {
347 u64 u64;
348 struct cvmx_gserx_dlmx_rx_rate_s {
349 u64 reserved_10_63 : 54;
350 u64 rx1_rate : 2;
351 u64 reserved_2_7 : 6;
352 u64 rx0_rate : 2;
353 } s;
354 struct cvmx_gserx_dlmx_rx_rate_s cn70xx;
355 struct cvmx_gserx_dlmx_rx_rate_s cn70xxp1;
356 };
357
358 typedef union cvmx_gserx_dlmx_rx_rate cvmx_gserx_dlmx_rx_rate_t;
359
360 /**
361 * cvmx_gser#_dlm#_rx_reset
362 *
363 * DLM0 Receiver Reset.
364 *
365 */
366 union cvmx_gserx_dlmx_rx_reset {
367 u64 u64;
368 struct cvmx_gserx_dlmx_rx_reset_s {
369 u64 reserved_9_63 : 55;
370 u64 rx1_reset : 1;
371 u64 reserved_1_7 : 7;
372 u64 rx0_reset : 1;
373 } s;
374 struct cvmx_gserx_dlmx_rx_reset_s cn70xx;
375 struct cvmx_gserx_dlmx_rx_reset_s cn70xxp1;
376 };
377
378 typedef union cvmx_gserx_dlmx_rx_reset cvmx_gserx_dlmx_rx_reset_t;
379
380 /**
381 * cvmx_gser#_dlm#_test_powerdown
382 *
383 * DLM Test Powerdown.
384 *
385 */
386 union cvmx_gserx_dlmx_test_powerdown {
387 u64 u64;
388 struct cvmx_gserx_dlmx_test_powerdown_s {
389 u64 reserved_1_63 : 63;
390 u64 test_powerdown : 1;
391 } s;
392 struct cvmx_gserx_dlmx_test_powerdown_s cn70xx;
393 struct cvmx_gserx_dlmx_test_powerdown_s cn70xxp1;
394 };
395
396 typedef union cvmx_gserx_dlmx_test_powerdown cvmx_gserx_dlmx_test_powerdown_t;
397
398 /**
399 * cvmx_gser#_dlm#_tx_amplitude
400 *
401 * DLM0 Tx Amplitude (Full Swing Mode).
402 *
403 */
404 union cvmx_gserx_dlmx_tx_amplitude {
405 u64 u64;
406 struct cvmx_gserx_dlmx_tx_amplitude_s {
407 u64 reserved_15_63 : 49;
408 u64 tx1_amplitude : 7;
409 u64 reserved_7_7 : 1;
410 u64 tx0_amplitude : 7;
411 } s;
412 struct cvmx_gserx_dlmx_tx_amplitude_s cn70xx;
413 struct cvmx_gserx_dlmx_tx_amplitude_s cn70xxp1;
414 };
415
416 typedef union cvmx_gserx_dlmx_tx_amplitude cvmx_gserx_dlmx_tx_amplitude_t;
417
418 /**
419 * cvmx_gser#_dlm#_tx_en
420 *
421 * DLM Transmit Clocking and Data Sampling Enable.
422 *
423 */
424 union cvmx_gserx_dlmx_tx_en {
425 u64 u64;
426 struct cvmx_gserx_dlmx_tx_en_s {
427 u64 reserved_9_63 : 55;
428 u64 tx1_en : 1;
429 u64 reserved_1_7 : 7;
430 u64 tx0_en : 1;
431 } s;
432 struct cvmx_gserx_dlmx_tx_en_s cn70xx;
433 struct cvmx_gserx_dlmx_tx_en_s cn70xxp1;
434 };
435
436 typedef union cvmx_gserx_dlmx_tx_en cvmx_gserx_dlmx_tx_en_t;
437
438 /**
439 * cvmx_gser#_dlm#_tx_preemph
440 *
441 * DLM0 Tx Deemphasis.
442 *
443 */
444 union cvmx_gserx_dlmx_tx_preemph {
445 u64 u64;
446 struct cvmx_gserx_dlmx_tx_preemph_s {
447 u64 reserved_15_63 : 49;
448 u64 tx1_preemph : 7;
449 u64 reserved_7_7 : 1;
450 u64 tx0_preemph : 7;
451 } s;
452 struct cvmx_gserx_dlmx_tx_preemph_s cn70xx;
453 struct cvmx_gserx_dlmx_tx_preemph_s cn70xxp1;
454 };
455
456 typedef union cvmx_gserx_dlmx_tx_preemph cvmx_gserx_dlmx_tx_preemph_t;
457
458 /**
459 * cvmx_gser#_dlm#_tx_status
460 *
461 * DLM Transmit Common Mode Control Status.
462 *
463 */
464 union cvmx_gserx_dlmx_tx_status {
465 u64 u64;
466 struct cvmx_gserx_dlmx_tx_status_s {
467 u64 reserved_10_63 : 54;
468 u64 tx1_cm_status : 1;
469 u64 tx1_status : 1;
470 u64 reserved_2_7 : 6;
471 u64 tx0_cm_status : 1;
472 u64 tx0_status : 1;
473 } s;
474 struct cvmx_gserx_dlmx_tx_status_s cn70xx;
475 struct cvmx_gserx_dlmx_tx_status_s cn70xxp1;
476 };
477
478 typedef union cvmx_gserx_dlmx_tx_status cvmx_gserx_dlmx_tx_status_t;
479
480 /**
481 * cvmx_gser#_dlm#_rx_status
482 *
483 * DLM Receive DPLL State Indicator.
484 *
485 */
486 union cvmx_gserx_dlmx_rx_status {
487 u64 u64;
488 struct cvmx_gserx_dlmx_rx_status_s {
489 u64 reserved_9_63 : 55;
490 u64 rx1_status : 1;
491 u64 reserved_1_7 : 7;
492 u64 rx0_status : 1;
493 } s;
494 struct cvmx_gserx_dlmx_rx_status_s cn70xx;
495 struct cvmx_gserx_dlmx_rx_status_s cn70xxp1;
496 };
497
498 typedef union cvmx_gserx_dlmx_rx_status cvmx_gserx_dlmx_rx_status_t;
499
500 /**
501 * cvmx_gser#_dlm#_tx_rate
502 *
503 * DLM0 Tx Data Rate.
504 *
505 */
506 union cvmx_gserx_dlmx_tx_rate {
507 u64 u64;
508 struct cvmx_gserx_dlmx_tx_rate_s {
509 u64 reserved_10_63 : 54;
510 u64 tx1_rate : 2;
511 u64 reserved_2_7 : 6;
512 u64 tx0_rate : 2;
513 } s;
514 struct cvmx_gserx_dlmx_tx_rate_s cn70xx;
515 struct cvmx_gserx_dlmx_tx_rate_s cn70xxp1;
516 };
517
518 typedef union cvmx_gserx_dlmx_tx_rate cvmx_gserx_dlmx_tx_rate_t;
519
520 /**
521 * cvmx_gser#_sata_status
522 *
523 * SATA PHY Ready Status.
524 *
525 */
526 union cvmx_gserx_sata_status {
527 u64 u64;
528 struct cvmx_gserx_sata_status_s {
529 u64 reserved_2_63 : 62;
530 u64 p1_rdy : 1;
531 u64 p0_rdy : 1;
532 } s;
533 struct cvmx_gserx_sata_status_s cn70xx;
534 struct cvmx_gserx_sata_status_s cn70xxp1;
535 struct cvmx_gserx_sata_status_s cn73xx;
536 struct cvmx_gserx_sata_status_s cnf75xx;
537 };
538
539 typedef union cvmx_gserx_sata_status cvmx_gserx_sata_status_t;
540
541 /**
542 * cvmx_gser#_dlm#_tx_data_en
543 *
544 * DLM0 Transmit Driver Enable.
545 *
546 */
547 union cvmx_gserx_dlmx_tx_data_en {
548 u64 u64;
549 struct cvmx_gserx_dlmx_tx_data_en_s {
550 u64 reserved_9_63 : 55;
551 u64 tx1_data_en : 1;
552 u64 reserved_1_7 : 7;
553 u64 tx0_data_en : 1;
554 } s;
555 struct cvmx_gserx_dlmx_tx_data_en_s cn70xx;
556 struct cvmx_gserx_dlmx_tx_data_en_s cn70xxp1;
557 };
558
559 typedef union cvmx_gserx_dlmx_tx_data_en cvmx_gserx_dlmx_tx_data_en_t;
560
561 /**
562 * cvmx_gser#_dlm#_tx_cm_en
563 *
564 * DLM0 Transmit Common-Mode Control Enable.
565 *
566 */
567 union cvmx_gserx_dlmx_tx_cm_en {
568 u64 u64;
569 struct cvmx_gserx_dlmx_tx_cm_en_s {
570 u64 reserved_9_63 : 55;
571 u64 tx1_cm_en : 1;
572 u64 reserved_1_7 : 7;
573 u64 tx0_cm_en : 1;
574 } s;
575 struct cvmx_gserx_dlmx_tx_cm_en_s cn70xx;
576 struct cvmx_gserx_dlmx_tx_cm_en_s cn70xxp1;
577 };
578
579 typedef union cvmx_gserx_dlmx_tx_cm_en cvmx_gserx_dlmx_tx_cm_en_t;
580
581 /**
582 * cvmx_gser#_dlm#_tx_reset
583 *
584 * DLM0 Tx Reset.
585 *
586 */
587 union cvmx_gserx_dlmx_tx_reset {
588 u64 u64;
589 struct cvmx_gserx_dlmx_tx_reset_s {
590 u64 reserved_9_63 : 55;
591 u64 tx1_reset : 1;
592 u64 reserved_1_7 : 7;
593 u64 tx0_reset : 1;
594 } s;
595 struct cvmx_gserx_dlmx_tx_reset_s cn70xx;
596 struct cvmx_gserx_dlmx_tx_reset_s cn70xxp1;
597 };
598
599 typedef union cvmx_gserx_dlmx_tx_reset cvmx_gserx_dlmx_tx_reset_t;
600
601 /**
602 * cvmx_gser#_dlm#_mpll_status
603 *
604 * DLM PLL Lock Status.
605 *
606 */
607 union cvmx_gserx_dlmx_mpll_status {
608 u64 u64;
609 struct cvmx_gserx_dlmx_mpll_status_s {
610 u64 reserved_1_63 : 63;
611 u64 mpll_status : 1;
612 } s;
613 struct cvmx_gserx_dlmx_mpll_status_s cn70xx;
614 struct cvmx_gserx_dlmx_mpll_status_s cn70xxp1;
615 };
616
617 typedef union cvmx_gserx_dlmx_mpll_status cvmx_gserx_dlmx_mpll_status_t;
618
619 /**
620 * cvmx_gser#_dlm#_phy_reset
621 *
622 * DLM Core and State Machine Reset.
623 *
624 */
625 union cvmx_gserx_dlmx_phy_reset {
626 u64 u64;
627 struct cvmx_gserx_dlmx_phy_reset_s {
628 u64 reserved_1_63 : 63;
629 u64 phy_reset : 1;
630 } s;
631 struct cvmx_gserx_dlmx_phy_reset_s cn70xx;
632 struct cvmx_gserx_dlmx_phy_reset_s cn70xxp1;
633 };
634
635 typedef union cvmx_gserx_dlmx_phy_reset cvmx_gserx_dlmx_phy_reset_t;
636
637 /**
638 * cvmx_gser#_dlm#_ref_clkdiv2
639 *
640 * DLM Input Reference Clock Divider Control.
641 *
642 */
643 union cvmx_gserx_dlmx_ref_clkdiv2 {
644 u64 u64;
645 struct cvmx_gserx_dlmx_ref_clkdiv2_s {
646 u64 reserved_1_63 : 63;
647 u64 ref_clkdiv2 : 1;
648 } s;
649 struct cvmx_gserx_dlmx_ref_clkdiv2_s cn70xx;
650 struct cvmx_gserx_dlmx_ref_clkdiv2_s cn70xxp1;
651 };
652
653 typedef union cvmx_gserx_dlmx_ref_clkdiv2 cvmx_gserx_dlmx_ref_clkdiv2_t;
654
655 /**
656 * cvmx_gser#_dlm#_ref_ssp_en
657 *
658 * DLM0 Reference Clock Enable for the PHY.
659 *
660 */
661 union cvmx_gserx_dlmx_ref_ssp_en {
662 u64 u64;
663 struct cvmx_gserx_dlmx_ref_ssp_en_s {
664 u64 reserved_1_63 : 63;
665 u64 ref_ssp_en : 1;
666 } s;
667 struct cvmx_gserx_dlmx_ref_ssp_en_s cn70xx;
668 struct cvmx_gserx_dlmx_ref_ssp_en_s cn70xxp1;
669 };
670
671 typedef union cvmx_gserx_dlmx_ref_ssp_en cvmx_gserx_dlmx_ref_ssp_en_t;
672
673 union cvmx_gserx_dlmx_mpll_en {
674 u64 u64;
675 struct cvmx_gserx_dlmx_mpll_en_s {
676 u64 reserved_1_63 : 63;
677 u64 mpll_en : 1;
678 } s;
679 struct cvmx_gserx_dlmx_mpll_en_s cn70xx;
680 struct cvmx_gserx_dlmx_mpll_en_s cn70xxp1;
681 };
682
683 typedef union cvmx_gserx_dlmx_mpll_en cvmx_gserx_dlmx_mpll_en_t;
684
685 /**
686 * cvmx_gser#_dlm#_rx_eq
687 *
688 * DLM Receiver Equalization Setting.
689 *
690 */
691 union cvmx_gserx_dlmx_rx_eq {
692 u64 u64;
693 struct cvmx_gserx_dlmx_rx_eq_s {
694 u64 reserved_11_63 : 53;
695 u64 rx1_eq : 3;
696 u64 reserved_3_7 : 5;
697 u64 rx0_eq : 3;
698 } s;
699 struct cvmx_gserx_dlmx_rx_eq_s cn70xx;
700 struct cvmx_gserx_dlmx_rx_eq_s cn70xxp1;
701 };
702
703 typedef union cvmx_gserx_dlmx_rx_eq cvmx_gserx_dlmx_rx_eq_t;
704
705 /**
706 * cvmx_gser#_dlm#_mpll_multiplier
707 *
708 * DLM MPLL Frequency Multiplier Control.
709 *
710 */
711 union cvmx_gserx_dlmx_mpll_multiplier {
712 u64 u64;
713 struct cvmx_gserx_dlmx_mpll_multiplier_s {
714 u64 reserved_7_63 : 57;
715 u64 mpll_multiplier : 7;
716 } s;
717 struct cvmx_gserx_dlmx_mpll_multiplier_s cn70xx;
718 struct cvmx_gserx_dlmx_mpll_multiplier_s cn70xxp1;
719 };
720
721 typedef union cvmx_gserx_dlmx_mpll_multiplier cvmx_gserx_dlmx_mpll_multiplier_t;
722
723 /**
724 * cvmx_gser#_br_rx#_ctl
725 */
726 union cvmx_gserx_br_rxx_ctl {
727 u64 u64;
728 struct cvmx_gserx_br_rxx_ctl_s {
729 u64 reserved_4_63 : 60;
730 u64 rxt_adtmout_disable : 1;
731 u64 rxt_swm : 1;
732 u64 rxt_preset : 1;
733 u64 rxt_initialize : 1;
734 } s;
735 struct cvmx_gserx_br_rxx_ctl_s cn73xx;
736 struct cvmx_gserx_br_rxx_ctl_s cn78xx;
737 struct cvmx_gserx_br_rxx_ctl_cn78xxp1 {
738 u64 reserved_3_63 : 61;
739 u64 rxt_swm : 1;
740 u64 rxt_preset : 1;
741 u64 rxt_initialize : 1;
742 } cn78xxp1;
743 struct cvmx_gserx_br_rxx_ctl_s cnf75xx;
744 };
745
746 typedef union cvmx_gserx_br_rxx_ctl cvmx_gserx_br_rxx_ctl_t;
747
748 /**
749 * cvmx_gser#_br_rx#_eer
750 *
751 * GSER software BASE-R RX link training equalization evaluation request (EER). A write to
752 * [RXT_EER] initiates a equalization request to the RAW PCS. A read of this register returns the
753 * equalization status message and a valid bit indicating it was updated. These registers are for
754 * diagnostic use only.
755 */
756 union cvmx_gserx_br_rxx_eer {
757 u64 u64;
758 struct cvmx_gserx_br_rxx_eer_s {
759 u64 reserved_16_63 : 48;
760 u64 rxt_eer : 1;
761 u64 rxt_esv : 1;
762 u64 rxt_esm : 14;
763 } s;
764 struct cvmx_gserx_br_rxx_eer_s cn73xx;
765 struct cvmx_gserx_br_rxx_eer_s cn78xx;
766 struct cvmx_gserx_br_rxx_eer_s cn78xxp1;
767 struct cvmx_gserx_br_rxx_eer_s cnf75xx;
768 };
769
770 typedef union cvmx_gserx_br_rxx_eer cvmx_gserx_br_rxx_eer_t;
771
772 /**
773 * cvmx_gser#_pcie_pipe_port_sel
774 *
775 * PCIE PIPE Enable Request.
776 *
777 */
778 union cvmx_gserx_pcie_pipe_port_sel {
779 u64 u64;
780 struct cvmx_gserx_pcie_pipe_port_sel_s {
781 u64 reserved_3_63 : 61;
782 u64 cfg_pem1_dlm2 : 1;
783 u64 pipe_port_sel : 2;
784 } s;
785 struct cvmx_gserx_pcie_pipe_port_sel_s cn70xx;
786 struct cvmx_gserx_pcie_pipe_port_sel_s cn70xxp1;
787 };
788
789 typedef union cvmx_gserx_pcie_pipe_port_sel cvmx_gserx_pcie_pipe_port_sel_t;
790
791 /**
792 * cvmx_gser#_pcie_pipe_rst
793 *
794 * PCIE PIPE Reset.
795 *
796 */
797 union cvmx_gserx_pcie_pipe_rst {
798 u64 u64;
799 struct cvmx_gserx_pcie_pipe_rst_s {
800 u64 reserved_4_63 : 60;
801 u64 pipe3_rst : 1;
802 u64 pipe2_rst : 1;
803 u64 pipe1_rst : 1;
804 u64 pipe0_rst : 1;
805 } s;
806 struct cvmx_gserx_pcie_pipe_rst_s cn70xx;
807 struct cvmx_gserx_pcie_pipe_rst_s cn70xxp1;
808 };
809
810 typedef union cvmx_gserx_pcie_pipe_rst cvmx_gserx_pcie_pipe_rst_t;
811
812 /**
813 * cvmx_gser#_sata_cfg
814 *
815 * SATA Config Enable.
816 *
817 */
818 union cvmx_gserx_sata_cfg {
819 u64 u64;
820 struct cvmx_gserx_sata_cfg_s {
821 u64 reserved_1_63 : 63;
822 u64 sata_en : 1;
823 } s;
824 struct cvmx_gserx_sata_cfg_s cn70xx;
825 struct cvmx_gserx_sata_cfg_s cn70xxp1;
826 };
827
828 typedef union cvmx_gserx_sata_cfg cvmx_gserx_sata_cfg_t;
829
830 /**
831 * cvmx_gser#_sata_lane_rst
832 *
833 * Lane Reset Control.
834 *
835 */
836 union cvmx_gserx_sata_lane_rst {
837 u64 u64;
838 struct cvmx_gserx_sata_lane_rst_s {
839 u64 reserved_2_63 : 62;
840 u64 l1_rst : 1;
841 u64 l0_rst : 1;
842 } s;
843 struct cvmx_gserx_sata_lane_rst_s cn70xx;
844 struct cvmx_gserx_sata_lane_rst_s cn70xxp1;
845 struct cvmx_gserx_sata_lane_rst_s cn73xx;
846 struct cvmx_gserx_sata_lane_rst_s cnf75xx;
847 };
848
849 typedef union cvmx_gserx_sata_lane_rst cvmx_gserx_sata_lane_rst_t;
850
851 /**
852 * cvmx_gser#_sata_ref_ssp_en
853 *
854 * SATA Reference Clock Enable for the PHY.
855 *
856 */
857 union cvmx_gserx_sata_ref_ssp_en {
858 u64 u64;
859 struct cvmx_gserx_sata_ref_ssp_en_s {
860 u64 reserved_1_63 : 63;
861 u64 ref_ssp_en : 1;
862 } s;
863 struct cvmx_gserx_sata_ref_ssp_en_s cn70xx;
864 struct cvmx_gserx_sata_ref_ssp_en_s cn70xxp1;
865 };
866
867 typedef union cvmx_gserx_sata_ref_ssp_en cvmx_gserx_sata_ref_ssp_en_t;
868
869 /**
870 * cvmx_gser#_phy#_ovrd_in_lo
871 *
872 * PHY Override Input Low Register.
873 *
874 */
875 union cvmx_gserx_phyx_ovrd_in_lo {
876 u64 u64;
877 struct cvmx_gserx_phyx_ovrd_in_lo_s {
878 u64 reserved_16_63 : 48;
879 u64 res_ack_in_ovrd : 1;
880 u64 res_ack_in : 1;
881 u64 res_req_in_ovrd : 1;
882 u64 res_req_in : 1;
883 u64 rtune_req_ovrd : 1;
884 u64 rtune_req : 1;
885 u64 mpll_multiplier_ovrd : 1;
886 u64 mpll_multiplier : 7;
887 u64 mpll_en_ovrd : 1;
888 u64 mpll_en : 1;
889 } s;
890 struct cvmx_gserx_phyx_ovrd_in_lo_s cn70xx;
891 struct cvmx_gserx_phyx_ovrd_in_lo_s cn70xxp1;
892 };
893
894 typedef union cvmx_gserx_phyx_ovrd_in_lo cvmx_gserx_phyx_ovrd_in_lo_t;
895
896 /**
897 * cvmx_gser#_phy_ctl
898 *
899 * This register contains general PHY/PLL control of the RAW PCS.
900 * These registers are reset by hardware only during chip cold reset. The values of the CSR
901 * fields in these registers do not change during chip warm or soft resets.
902 */
903 union cvmx_gserx_phy_ctl {
904 u64 u64;
905 struct cvmx_gserx_phy_ctl_s {
906 u64 reserved_2_63 : 62;
907 u64 phy_reset : 1;
908 u64 phy_pd : 1;
909 } s;
910 struct cvmx_gserx_phy_ctl_s cn73xx;
911 struct cvmx_gserx_phy_ctl_s cn78xx;
912 struct cvmx_gserx_phy_ctl_s cn78xxp1;
913 struct cvmx_gserx_phy_ctl_s cnf75xx;
914 };
915
916 typedef union cvmx_gserx_phy_ctl cvmx_gserx_phy_ctl_t;
917
918 /**
919 * cvmx_gser#_rx_pwr_ctrl_p1
920 *
921 * These registers are for diagnostic use only.
922 * These registers are reset by hardware only during chip cold reset.
923 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
924 */
925 union cvmx_gserx_rx_pwr_ctrl_p1 {
926 u64 u64;
927 struct cvmx_gserx_rx_pwr_ctrl_p1_s {
928 u64 reserved_14_63 : 50;
929 u64 p1_rx_resetn : 1;
930 u64 pq_rx_allow_pll_pd : 1;
931 u64 pq_rx_pcs_reset : 1;
932 u64 p1_rx_agc_en : 1;
933 u64 p1_rx_dfe_en : 1;
934 u64 p1_rx_cdr_en : 1;
935 u64 p1_rx_cdr_coast : 1;
936 u64 p1_rx_cdr_clr : 1;
937 u64 p1_rx_subblk_pd : 5;
938 u64 p1_rx_chpd : 1;
939 } s;
940 struct cvmx_gserx_rx_pwr_ctrl_p1_s cn73xx;
941 struct cvmx_gserx_rx_pwr_ctrl_p1_s cn78xx;
942 struct cvmx_gserx_rx_pwr_ctrl_p1_s cn78xxp1;
943 struct cvmx_gserx_rx_pwr_ctrl_p1_s cnf75xx;
944 };
945
946 typedef union cvmx_gserx_rx_pwr_ctrl_p1 cvmx_gserx_rx_pwr_ctrl_p1_t;
947
948 /**
949 * cvmx_gser#_rx_pwr_ctrl_p2
950 *
951 * These registers are for diagnostic use only.
952 * These registers are reset by hardware only during chip cold reset.
953 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
954 */
955 union cvmx_gserx_rx_pwr_ctrl_p2 {
956 u64 u64;
957 struct cvmx_gserx_rx_pwr_ctrl_p2_s {
958 u64 reserved_14_63 : 50;
959 u64 p2_rx_resetn : 1;
960 u64 p2_rx_allow_pll_pd : 1;
961 u64 p2_rx_pcs_reset : 1;
962 u64 p2_rx_agc_en : 1;
963 u64 p2_rx_dfe_en : 1;
964 u64 p2_rx_cdr_en : 1;
965 u64 p2_rx_cdr_coast : 1;
966 u64 p2_rx_cdr_clr : 1;
967 u64 p2_rx_subblk_pd : 5;
968 u64 p2_rx_chpd : 1;
969 } s;
970 struct cvmx_gserx_rx_pwr_ctrl_p2_s cn73xx;
971 struct cvmx_gserx_rx_pwr_ctrl_p2_s cn78xx;
972 struct cvmx_gserx_rx_pwr_ctrl_p2_s cn78xxp1;
973 struct cvmx_gserx_rx_pwr_ctrl_p2_s cnf75xx;
974 };
975
976 typedef union cvmx_gserx_rx_pwr_ctrl_p2 cvmx_gserx_rx_pwr_ctrl_p2_t;
977
978 /**
979 * cvmx_gser#_rx_txdir_ctrl_0
980 *
981 * These registers are for diagnostic use only.
982 * These registers are reset by hardware only during chip cold reset.
983 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
984 */
985 union cvmx_gserx_rx_txdir_ctrl_0 {
986 u64 u64;
987 struct cvmx_gserx_rx_txdir_ctrl_0_s {
988 u64 reserved_13_63 : 51;
989 u64 rx_boost_hi_thrs : 4;
990 u64 rx_boost_lo_thrs : 4;
991 u64 rx_boost_hi_val : 5;
992 } s;
993 struct cvmx_gserx_rx_txdir_ctrl_0_s cn73xx;
994 struct cvmx_gserx_rx_txdir_ctrl_0_s cn78xx;
995 struct cvmx_gserx_rx_txdir_ctrl_0_s cn78xxp1;
996 struct cvmx_gserx_rx_txdir_ctrl_0_s cnf75xx;
997 };
998
999 typedef union cvmx_gserx_rx_txdir_ctrl_0 cvmx_gserx_rx_txdir_ctrl_0_t;
1000
1001 /**
1002 * cvmx_gser#_rx_txdir_ctrl_1
1003 *
1004 * These registers are for diagnostic use only.
1005 * These registers are reset by hardware only during chip cold reset.
1006 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1007 */
1008 union cvmx_gserx_rx_txdir_ctrl_1 {
1009 u64 u64;
1010 struct cvmx_gserx_rx_txdir_ctrl_1_s {
1011 u64 reserved_12_63 : 52;
1012 u64 rx_precorr_chg_dir : 1;
1013 u64 rx_tap1_chg_dir : 1;
1014 u64 rx_tap1_hi_thrs : 5;
1015 u64 rx_tap1_lo_thrs : 5;
1016 } s;
1017 struct cvmx_gserx_rx_txdir_ctrl_1_s cn73xx;
1018 struct cvmx_gserx_rx_txdir_ctrl_1_s cn78xx;
1019 struct cvmx_gserx_rx_txdir_ctrl_1_s cn78xxp1;
1020 struct cvmx_gserx_rx_txdir_ctrl_1_s cnf75xx;
1021 };
1022
1023 typedef union cvmx_gserx_rx_txdir_ctrl_1 cvmx_gserx_rx_txdir_ctrl_1_t;
1024
1025 /**
1026 * cvmx_gser#_rx_txdir_ctrl_2
1027 *
1028 * These registers are for diagnostic use only.
1029 * These registers are reset by hardware only during chip cold reset.
1030 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1031 */
1032 union cvmx_gserx_rx_txdir_ctrl_2 {
1033 u64 u64;
1034 struct cvmx_gserx_rx_txdir_ctrl_2_s {
1035 u64 reserved_16_63 : 48;
1036 u64 rx_precorr_hi_thrs : 8;
1037 u64 rx_precorr_lo_thrs : 8;
1038 } s;
1039 struct cvmx_gserx_rx_txdir_ctrl_2_s cn73xx;
1040 struct cvmx_gserx_rx_txdir_ctrl_2_s cn78xx;
1041 struct cvmx_gserx_rx_txdir_ctrl_2_s cn78xxp1;
1042 struct cvmx_gserx_rx_txdir_ctrl_2_s cnf75xx;
1043 };
1044
1045 typedef union cvmx_gserx_rx_txdir_ctrl_2 cvmx_gserx_rx_txdir_ctrl_2_t;
1046
1047 /**
1048 * cvmx_gser#_rx_eie_detsts
1049 */
1050 union cvmx_gserx_rx_eie_detsts {
1051 u64 u64;
1052 struct cvmx_gserx_rx_eie_detsts_s {
1053 u64 reserved_12_63 : 52;
1054 u64 cdrlock : 4;
1055 u64 eiests : 4;
1056 u64 eieltch : 4;
1057 } s;
1058 struct cvmx_gserx_rx_eie_detsts_s cn73xx;
1059 struct cvmx_gserx_rx_eie_detsts_s cn78xx;
1060 struct cvmx_gserx_rx_eie_detsts_s cn78xxp1;
1061 struct cvmx_gserx_rx_eie_detsts_s cnf75xx;
1062 };
1063
1064 typedef union cvmx_gserx_rx_eie_detsts cvmx_gserx_rx_eie_detsts_t;
1065
1066 /**
1067 * cvmx_gser#_refclk_sel
1068 *
1069 * This register selects the reference clock.
1070 * These registers are reset by hardware only during chip cold reset. The values of the CSR
1071 * fields in these registers do not change during chip warm or soft resets.
1072 *
1073 * Not used with GSER6, GSER7, and GSER8.
1074 */
1075 union cvmx_gserx_refclk_sel {
1076 u64 u64;
1077 struct cvmx_gserx_refclk_sel_s {
1078 u64 reserved_3_63 : 61;
1079 u64 pcie_refclk125 : 1;
1080 u64 com_clk_sel : 1;
1081 u64 use_com1 : 1;
1082 } s;
1083 struct cvmx_gserx_refclk_sel_s cn73xx;
1084 struct cvmx_gserx_refclk_sel_s cn78xx;
1085 struct cvmx_gserx_refclk_sel_s cn78xxp1;
1086 struct cvmx_gserx_refclk_sel_s cnf75xx;
1087 };
1088
1089 typedef union cvmx_gserx_refclk_sel cvmx_gserx_refclk_sel_t;
1090
1091 /**
1092 * cvmx_gser#_lane#_lbert_cfg
1093 *
1094 * These registers are reset by hardware only during chip cold reset.
1095 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1096 */
1097 union cvmx_gserx_lanex_lbert_cfg {
1098 u64 u64;
1099 struct cvmx_gserx_lanex_lbert_cfg_s {
1100 u64 reserved_16_63 : 48;
1101 u64 lbert_pg_err_insert : 1;
1102 u64 lbert_pm_sync_start : 1;
1103 u64 lbert_pg_en : 1;
1104 u64 lbert_pg_width : 2;
1105 u64 lbert_pg_mode : 4;
1106 u64 lbert_pm_en : 1;
1107 u64 lbert_pm_width : 2;
1108 u64 lbert_pm_mode : 4;
1109 } s;
1110 struct cvmx_gserx_lanex_lbert_cfg_s cn73xx;
1111 struct cvmx_gserx_lanex_lbert_cfg_s cn78xx;
1112 struct cvmx_gserx_lanex_lbert_cfg_s cn78xxp1;
1113 struct cvmx_gserx_lanex_lbert_cfg_s cnf75xx;
1114 };
1115
1116 typedef union cvmx_gserx_lanex_lbert_cfg cvmx_gserx_lanex_lbert_cfg_t;
1117
1118 /**
1119 * cvmx_gser#_lane#_misc_cfg_0
1120 *
1121 * These registers are for diagnostic use only.
1122 * These registers are reset by hardware only during chip cold reset.
1123 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1124 */
1125 union cvmx_gserx_lanex_misc_cfg_0 {
1126 u64 u64;
1127 struct cvmx_gserx_lanex_misc_cfg_0_s {
1128 u64 reserved_16_63 : 48;
1129 u64 use_pma_polarity : 1;
1130 u64 cfg_pcs_loopback : 1;
1131 u64 pcs_tx_mode_ovrrd_en : 1;
1132 u64 pcs_rx_mode_ovrrd_en : 1;
1133 u64 cfg_eie_det_cnt : 4;
1134 u64 eie_det_stl_on_time : 3;
1135 u64 eie_det_stl_off_time : 3;
1136 u64 tx_bit_order : 1;
1137 u64 rx_bit_order : 1;
1138 } s;
1139 struct cvmx_gserx_lanex_misc_cfg_0_s cn73xx;
1140 struct cvmx_gserx_lanex_misc_cfg_0_s cn78xx;
1141 struct cvmx_gserx_lanex_misc_cfg_0_s cn78xxp1;
1142 struct cvmx_gserx_lanex_misc_cfg_0_s cnf75xx;
1143 };
1144
1145 typedef union cvmx_gserx_lanex_misc_cfg_0 cvmx_gserx_lanex_misc_cfg_0_t;
1146
1147 /**
1148 * cvmx_gser#_lane_p#_mode_0
1149 *
1150 * These are the RAW PCS lane settings mode 0 registers. There is one register per
1151 * 4 lanes per GSER per GSER_LMODE_E value (0..11). Only one entry is used at any given time in a
1152 * given GSER lane - the one selected by the corresponding GSER()_LANE_MODE[LMODE].
1153 * These registers are reset by hardware only during chip cold reset.
1154 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1155 */
1156 union cvmx_gserx_lane_px_mode_0 {
1157 u64 u64;
1158 struct cvmx_gserx_lane_px_mode_0_s {
1159 u64 reserved_15_63 : 49;
1160 u64 ctle : 2;
1161 u64 pcie : 1;
1162 u64 tx_ldiv : 2;
1163 u64 rx_ldiv : 2;
1164 u64 srate : 3;
1165 u64 reserved_4_4 : 1;
1166 u64 tx_mode : 2;
1167 u64 rx_mode : 2;
1168 } s;
1169 struct cvmx_gserx_lane_px_mode_0_s cn73xx;
1170 struct cvmx_gserx_lane_px_mode_0_s cn78xx;
1171 struct cvmx_gserx_lane_px_mode_0_s cn78xxp1;
1172 struct cvmx_gserx_lane_px_mode_0_s cnf75xx;
1173 };
1174
1175 typedef union cvmx_gserx_lane_px_mode_0 cvmx_gserx_lane_px_mode_0_t;
1176
1177 /**
1178 * cvmx_gser#_lane_p#_mode_1
1179 *
1180 * These are the RAW PCS lane settings mode 1 registers. There is one register per 4 lanes,
1181 * (0..3) per GSER per GSER_LMODE_E value (0..11). Only one entry is used at any given time in a
1182 * given
1183 * GSER lane - the one selected by the corresponding GSER()_LANE_MODE[LMODE].
1184 * These registers are reset by hardware only during chip cold reset.
1185 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1186 */
1187 union cvmx_gserx_lane_px_mode_1 {
1188 u64 u64;
1189 struct cvmx_gserx_lane_px_mode_1_s {
1190 u64 reserved_16_63 : 48;
1191 u64 vma_fine_cfg_sel : 1;
1192 u64 vma_mm : 1;
1193 u64 cdr_fgain : 4;
1194 u64 ph_acc_adj : 10;
1195 } s;
1196 struct cvmx_gserx_lane_px_mode_1_s cn73xx;
1197 struct cvmx_gserx_lane_px_mode_1_s cn78xx;
1198 struct cvmx_gserx_lane_px_mode_1_s cn78xxp1;
1199 struct cvmx_gserx_lane_px_mode_1_s cnf75xx;
1200 };
1201
1202 typedef union cvmx_gserx_lane_px_mode_1 cvmx_gserx_lane_px_mode_1_t;
1203
1204 /**
1205 * cvmx_gser#_lane#_rx_loop_ctrl
1206 *
1207 * These registers are for diagnostic use only.
1208 * These registers are reset by hardware only during chip cold reset.
1209 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1210 */
1211 union cvmx_gserx_lanex_rx_loop_ctrl {
1212 u64 u64;
1213 struct cvmx_gserx_lanex_rx_loop_ctrl_s {
1214 u64 reserved_12_63 : 52;
1215 u64 fast_dll_lock : 1;
1216 u64 fast_ofst_cncl : 1;
1217 u64 cfg_rx_lctrl : 10;
1218 } s;
1219 struct cvmx_gserx_lanex_rx_loop_ctrl_s cn73xx;
1220 struct cvmx_gserx_lanex_rx_loop_ctrl_s cn78xx;
1221 struct cvmx_gserx_lanex_rx_loop_ctrl_s cn78xxp1;
1222 struct cvmx_gserx_lanex_rx_loop_ctrl_s cnf75xx;
1223 };
1224
1225 typedef union cvmx_gserx_lanex_rx_loop_ctrl cvmx_gserx_lanex_rx_loop_ctrl_t;
1226
1227 /**
1228 * cvmx_gser#_lane#_rx_valbbd_ctrl_0
1229 *
1230 * These registers are reset by hardware only during chip cold reset. The values of the CSR
1231 * fields in these registers do not change during chip warm or soft resets.
1232 */
1233 union cvmx_gserx_lanex_rx_valbbd_ctrl_0 {
1234 u64 u64;
1235 struct cvmx_gserx_lanex_rx_valbbd_ctrl_0_s {
1236 u64 reserved_14_63 : 50;
1237 u64 agc_gain : 2;
1238 u64 dfe_gain : 2;
1239 u64 dfe_c5_mval : 4;
1240 u64 dfe_c5_msgn : 1;
1241 u64 dfe_c4_mval : 4;
1242 u64 dfe_c4_msgn : 1;
1243 } s;
1244 struct cvmx_gserx_lanex_rx_valbbd_ctrl_0_s cn73xx;
1245 struct cvmx_gserx_lanex_rx_valbbd_ctrl_0_s cn78xx;
1246 struct cvmx_gserx_lanex_rx_valbbd_ctrl_0_s cn78xxp1;
1247 struct cvmx_gserx_lanex_rx_valbbd_ctrl_0_s cnf75xx;
1248 };
1249
1250 typedef union cvmx_gserx_lanex_rx_valbbd_ctrl_0 cvmx_gserx_lanex_rx_valbbd_ctrl_0_t;
1251
1252 /**
1253 * cvmx_gser#_lane#_rx_valbbd_ctrl_1
1254 *
1255 * These registers are reset by hardware only during chip cold reset. The values of the CSR
1256 * fields in these registers do not change during chip warm or soft resets.
1257 */
1258 union cvmx_gserx_lanex_rx_valbbd_ctrl_1 {
1259 u64 u64;
1260 struct cvmx_gserx_lanex_rx_valbbd_ctrl_1_s {
1261 u64 reserved_15_63 : 49;
1262 u64 dfe_c3_mval : 4;
1263 u64 dfe_c3_msgn : 1;
1264 u64 dfe_c2_mval : 4;
1265 u64 dfe_c2_msgn : 1;
1266 u64 dfe_c1_mval : 4;
1267 u64 dfe_c1_msgn : 1;
1268 } s;
1269 struct cvmx_gserx_lanex_rx_valbbd_ctrl_1_s cn73xx;
1270 struct cvmx_gserx_lanex_rx_valbbd_ctrl_1_s cn78xx;
1271 struct cvmx_gserx_lanex_rx_valbbd_ctrl_1_s cn78xxp1;
1272 struct cvmx_gserx_lanex_rx_valbbd_ctrl_1_s cnf75xx;
1273 };
1274
1275 typedef union cvmx_gserx_lanex_rx_valbbd_ctrl_1 cvmx_gserx_lanex_rx_valbbd_ctrl_1_t;
1276
1277 /**
1278 * cvmx_gser#_lane#_rx_valbbd_ctrl_2
1279 *
1280 * These registers are reset by hardware only during chip cold reset. The values of the CSR
1281 * fields in these registers do not change during chip warm or soft resets.
1282 */
1283 union cvmx_gserx_lanex_rx_valbbd_ctrl_2 {
1284 u64 u64;
1285 struct cvmx_gserx_lanex_rx_valbbd_ctrl_2_s {
1286 u64 reserved_6_63 : 58;
1287 u64 dfe_ovrd_en : 1;
1288 u64 dfe_c5_ovrd_val : 1;
1289 u64 dfe_c4_ovrd_val : 1;
1290 u64 dfe_c3_ovrd_val : 1;
1291 u64 dfe_c2_ovrd_val : 1;
1292 u64 dfe_c1_ovrd_val : 1;
1293 } s;
1294 struct cvmx_gserx_lanex_rx_valbbd_ctrl_2_s cn73xx;
1295 struct cvmx_gserx_lanex_rx_valbbd_ctrl_2_s cn78xx;
1296 struct cvmx_gserx_lanex_rx_valbbd_ctrl_2_s cn78xxp1;
1297 struct cvmx_gserx_lanex_rx_valbbd_ctrl_2_s cnf75xx;
1298 };
1299
1300 typedef union cvmx_gserx_lanex_rx_valbbd_ctrl_2 cvmx_gserx_lanex_rx_valbbd_ctrl_2_t;
1301
1302 /**
1303 * cvmx_gser#_lane_vma_fine_ctrl_0
1304 *
1305 * These registers are for diagnostic use only.
1306 * These registers are reset by hardware only during chip cold reset.
1307 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1308 */
1309 union cvmx_gserx_lane_vma_fine_ctrl_0 {
1310 u64 u64;
1311 struct cvmx_gserx_lane_vma_fine_ctrl_0_s {
1312 u64 reserved_16_63 : 48;
1313 u64 rx_sdll_iq_max_fine : 4;
1314 u64 rx_sdll_iq_min_fine : 4;
1315 u64 rx_sdll_iq_step_fine : 2;
1316 u64 vma_window_wait_fine : 3;
1317 u64 lms_wait_time_fine : 3;
1318 } s;
1319 struct cvmx_gserx_lane_vma_fine_ctrl_0_s cn73xx;
1320 struct cvmx_gserx_lane_vma_fine_ctrl_0_s cn78xx;
1321 struct cvmx_gserx_lane_vma_fine_ctrl_0_s cn78xxp1;
1322 struct cvmx_gserx_lane_vma_fine_ctrl_0_s cnf75xx;
1323 };
1324
1325 typedef union cvmx_gserx_lane_vma_fine_ctrl_0 cvmx_gserx_lane_vma_fine_ctrl_0_t;
1326
1327 /**
1328 * cvmx_gser#_lane_vma_fine_ctrl_1
1329 *
1330 * These registers are for diagnostic use only.
1331 * These registers are reset by hardware only during chip cold reset.
1332 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1333 */
1334 union cvmx_gserx_lane_vma_fine_ctrl_1 {
1335 u64 u64;
1336 struct cvmx_gserx_lane_vma_fine_ctrl_1_s {
1337 u64 reserved_10_63 : 54;
1338 u64 rx_ctle_peak_max_fine : 4;
1339 u64 rx_ctle_peak_min_fine : 4;
1340 u64 rx_ctle_peak_step_fine : 2;
1341 } s;
1342 struct cvmx_gserx_lane_vma_fine_ctrl_1_s cn73xx;
1343 struct cvmx_gserx_lane_vma_fine_ctrl_1_s cn78xx;
1344 struct cvmx_gserx_lane_vma_fine_ctrl_1_s cn78xxp1;
1345 struct cvmx_gserx_lane_vma_fine_ctrl_1_s cnf75xx;
1346 };
1347
1348 typedef union cvmx_gserx_lane_vma_fine_ctrl_1 cvmx_gserx_lane_vma_fine_ctrl_1_t;
1349
1350 /**
1351 * cvmx_gser#_lane_vma_fine_ctrl_2
1352 *
1353 * These registers are for diagnostic use only.
1354 * These registers are reset by hardware only during chip cold reset.
1355 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1356 */
1357 union cvmx_gserx_lane_vma_fine_ctrl_2 {
1358 u64 u64;
1359 struct cvmx_gserx_lane_vma_fine_ctrl_2_s {
1360 u64 reserved_10_63 : 54;
1361 u64 rx_prectle_gain_max_fine : 4;
1362 u64 rx_prectle_gain_min_fine : 4;
1363 u64 rx_prectle_gain_step_fine : 2;
1364 } s;
1365 struct cvmx_gserx_lane_vma_fine_ctrl_2_s cn73xx;
1366 struct cvmx_gserx_lane_vma_fine_ctrl_2_s cn78xx;
1367 struct cvmx_gserx_lane_vma_fine_ctrl_2_s cn78xxp1;
1368 struct cvmx_gserx_lane_vma_fine_ctrl_2_s cnf75xx;
1369 };
1370
1371 typedef union cvmx_gserx_lane_vma_fine_ctrl_2 cvmx_gserx_lane_vma_fine_ctrl_2_t;
1372
1373 /**
1374 * cvmx_gser#_lane#_pwr_ctrl
1375 *
1376 * These registers are for diagnostic use only.
1377 * These registers are reset by hardware only during chip cold reset.
1378 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1379 */
1380 union cvmx_gserx_lanex_pwr_ctrl {
1381 u64 u64;
1382 struct cvmx_gserx_lanex_pwr_ctrl_s {
1383 u64 reserved_15_63 : 49;
1384 u64 tx_sds_fifo_reset_ovrrd_en : 1;
1385 u64 tx_sds_fifo_reset_ovrrd_val : 1;
1386 u64 tx_pcs_reset_ovrrd_val : 1;
1387 u64 rx_pcs_reset_ovrrd_val : 1;
1388 u64 reserved_9_10 : 2;
1389 u64 rx_resetn_ovrrd_en : 1;
1390 u64 rx_resetn_ovrrd_val : 1;
1391 u64 rx_lctrl_ovrrd_en : 1;
1392 u64 rx_lctrl_ovrrd_val : 1;
1393 u64 tx_tristate_en_ovrrd_en : 1;
1394 u64 tx_pcs_reset_ovrrd_en : 1;
1395 u64 tx_elec_idle_ovrrd_en : 1;
1396 u64 tx_pd_ovrrd_en : 1;
1397 u64 tx_p2s_resetn_ovrrd_en : 1;
1398 } s;
1399 struct cvmx_gserx_lanex_pwr_ctrl_cn73xx {
1400 u64 reserved_15_63 : 49;
1401 u64 tx_sds_fifo_reset_ovrrd_en : 1;
1402 u64 tx_sds_fifo_reset_ovrrd_val : 1;
1403 u64 tx_pcs_reset_ovrrd_val : 1;
1404 u64 rx_pcs_reset_ovrrd_val : 1;
1405 u64 reserved_10_9 : 2;
1406 u64 rx_resetn_ovrrd_en : 1;
1407 u64 rx_resetn_ovrrd_val : 1;
1408 u64 rx_lctrl_ovrrd_en : 1;
1409 u64 rx_lctrl_ovrrd_val : 1;
1410 u64 tx_tristate_en_ovrrd_en : 1;
1411 u64 tx_pcs_reset_ovrrd_en : 1;
1412 u64 tx_elec_idle_ovrrd_en : 1;
1413 u64 tx_pd_ovrrd_en : 1;
1414 u64 tx_p2s_resetn_ovrrd_en : 1;
1415 } cn73xx;
1416 struct cvmx_gserx_lanex_pwr_ctrl_cn73xx cn78xx;
1417 struct cvmx_gserx_lanex_pwr_ctrl_s cn78xxp1;
1418 struct cvmx_gserx_lanex_pwr_ctrl_cn73xx cnf75xx;
1419 };
1420
1421 typedef union cvmx_gserx_lanex_pwr_ctrl cvmx_gserx_lanex_pwr_ctrl_t;
1422
1423 /**
1424 * cvmx_gser#_lane#_rx_cfg_0
1425 *
1426 * These registers are for diagnostic use only.
1427 * These registers are reset by hardware only during chip cold reset.
1428 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1429 */
1430 union cvmx_gserx_lanex_rx_cfg_0 {
1431 u64 u64;
1432 struct cvmx_gserx_lanex_rx_cfg_0_s {
1433 u64 reserved_16_63 : 48;
1434 u64 rx_datarate_ovrrd_en : 1;
1435 u64 reserved_14_14 : 1;
1436 u64 rx_resetn_ovrrd_val : 1;
1437 u64 pcs_sds_rx_eyemon_en : 1;
1438 u64 pcs_sds_rx_pcm_ctrl : 4;
1439 u64 rx_datarate_ovrrd_val : 2;
1440 u64 cfg_rx_pol_invert : 1;
1441 u64 rx_subblk_pd_ovrrd_val : 5;
1442 } s;
1443 struct cvmx_gserx_lanex_rx_cfg_0_cn73xx {
1444 u64 reserved_16_63 : 48;
1445 u64 rx_datarate_ovrrd_en : 1;
1446 u64 pcs_rx_tristate_enable : 1;
1447 u64 rx_resetn_ovrrd_val : 1;
1448 u64 pcs_sds_rx_eyemon_en : 1;
1449 u64 pcs_sds_rx_pcm_ctrl : 4;
1450 u64 rx_datarate_ovrrd_val : 2;
1451 u64 cfg_rx_pol_invert : 1;
1452 u64 rx_subblk_pd_ovrrd_val : 5;
1453 } cn73xx;
1454 struct cvmx_gserx_lanex_rx_cfg_0_cn78xx {
1455 u64 reserved_16_63 : 48;
1456 u64 rx_datarate_ovrrd_en : 1;
1457 u64 pcs_sds_rx_tristate_enable : 1;
1458 u64 rx_resetn_ovrrd_val : 1;
1459 u64 pcs_sds_rx_eyemon_en : 1;
1460 u64 pcs_sds_rx_pcm_ctrl : 4;
1461 u64 rx_datarate_ovrrd_val : 2;
1462 u64 cfg_rx_pol_invert : 1;
1463 u64 rx_subblk_pd_ovrrd_val : 5;
1464 } cn78xx;
1465 struct cvmx_gserx_lanex_rx_cfg_0_cn78xx cn78xxp1;
1466 struct cvmx_gserx_lanex_rx_cfg_0_cn73xx cnf75xx;
1467 };
1468
1469 typedef union cvmx_gserx_lanex_rx_cfg_0 cvmx_gserx_lanex_rx_cfg_0_t;
1470
1471 /**
1472 * cvmx_gser#_lane#_rx_cfg_1
1473 *
1474 * These registers are for diagnostic use only.
1475 * These registers are reset by hardware only during chip cold reset.
1476 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1477 */
1478 union cvmx_gserx_lanex_rx_cfg_1 {
1479 u64 u64;
1480 struct cvmx_gserx_lanex_rx_cfg_1_s {
1481 u64 reserved_16_63 : 48;
1482 u64 rx_chpd_ovrrd_val : 1;
1483 u64 pcs_sds_rx_os_men : 1;
1484 u64 eie_en_ovrrd_en : 1;
1485 u64 eie_en_ovrrd_val : 1;
1486 u64 reserved_11_11 : 1;
1487 u64 rx_pcie_mode_ovrrd_en : 1;
1488 u64 rx_pcie_mode_ovrrd_val : 1;
1489 u64 cfg_rx_dll_locken : 1;
1490 u64 pcs_sds_rx_cdr_ssc_mode : 8;
1491 } s;
1492 struct cvmx_gserx_lanex_rx_cfg_1_s cn73xx;
1493 struct cvmx_gserx_lanex_rx_cfg_1_s cn78xx;
1494 struct cvmx_gserx_lanex_rx_cfg_1_s cn78xxp1;
1495 struct cvmx_gserx_lanex_rx_cfg_1_s cnf75xx;
1496 };
1497
1498 typedef union cvmx_gserx_lanex_rx_cfg_1 cvmx_gserx_lanex_rx_cfg_1_t;
1499
1500 /**
1501 * cvmx_gser#_lane#_rx_cfg_2
1502 *
1503 * These registers are for diagnostic use only.
1504 * These registers are reset by hardware only during chip cold reset.
1505 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1506 */
1507 union cvmx_gserx_lanex_rx_cfg_2 {
1508 u64 u64;
1509 struct cvmx_gserx_lanex_rx_cfg_2_s {
1510 u64 reserved_15_63 : 49;
1511 u64 pcs_sds_rx_terminate_to_vdda : 1;
1512 u64 pcs_sds_rx_sampler_boost : 2;
1513 u64 pcs_sds_rx_sampler_boost_en : 1;
1514 u64 reserved_10_10 : 1;
1515 u64 rx_sds_rx_agc_mval : 10;
1516 } s;
1517 struct cvmx_gserx_lanex_rx_cfg_2_s cn73xx;
1518 struct cvmx_gserx_lanex_rx_cfg_2_s cn78xx;
1519 struct cvmx_gserx_lanex_rx_cfg_2_s cn78xxp1;
1520 struct cvmx_gserx_lanex_rx_cfg_2_s cnf75xx;
1521 };
1522
1523 typedef union cvmx_gserx_lanex_rx_cfg_2 cvmx_gserx_lanex_rx_cfg_2_t;
1524
1525 /**
1526 * cvmx_gser#_lane#_rx_cfg_3
1527 *
1528 * These registers are for diagnostic use only.
1529 * These registers are reset by hardware only during chip cold reset.
1530 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1531 */
1532 union cvmx_gserx_lanex_rx_cfg_3 {
1533 u64 u64;
1534 struct cvmx_gserx_lanex_rx_cfg_3_s {
1535 u64 reserved_16_63 : 48;
1536 u64 cfg_rx_errdet_ctrl : 16;
1537 } s;
1538 struct cvmx_gserx_lanex_rx_cfg_3_s cn73xx;
1539 struct cvmx_gserx_lanex_rx_cfg_3_s cn78xx;
1540 struct cvmx_gserx_lanex_rx_cfg_3_s cn78xxp1;
1541 struct cvmx_gserx_lanex_rx_cfg_3_s cnf75xx;
1542 };
1543
1544 typedef union cvmx_gserx_lanex_rx_cfg_3 cvmx_gserx_lanex_rx_cfg_3_t;
1545
1546 /**
1547 * cvmx_gser#_lane#_rx_cfg_4
1548 *
1549 * These registers are for diagnostic use only.
1550 * These registers are reset by hardware only during chip cold reset.
1551 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1552 */
1553 union cvmx_gserx_lanex_rx_cfg_4 {
1554 u64 u64;
1555 struct cvmx_gserx_lanex_rx_cfg_4_s {
1556 u64 reserved_16_63 : 48;
1557 u64 cfg_rx_errdet_ctrl : 16;
1558 } s;
1559 struct cvmx_gserx_lanex_rx_cfg_4_s cn73xx;
1560 struct cvmx_gserx_lanex_rx_cfg_4_s cn78xx;
1561 struct cvmx_gserx_lanex_rx_cfg_4_s cn78xxp1;
1562 struct cvmx_gserx_lanex_rx_cfg_4_s cnf75xx;
1563 };
1564
1565 typedef union cvmx_gserx_lanex_rx_cfg_4 cvmx_gserx_lanex_rx_cfg_4_t;
1566
1567 /**
1568 * cvmx_gser#_lane#_rx_cfg_5
1569 *
1570 * These registers are for diagnostic use only.
1571 * These registers are reset by hardware only during chip cold reset.
1572 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1573 */
1574 union cvmx_gserx_lanex_rx_cfg_5 {
1575 u64 u64;
1576 struct cvmx_gserx_lanex_rx_cfg_5_s {
1577 u64 reserved_5_63 : 59;
1578 u64 rx_agc_men_ovrrd_en : 1;
1579 u64 rx_agc_men_ovrrd_val : 1;
1580 u64 rx_widthsel_ovrrd_en : 1;
1581 u64 rx_widthsel_ovrrd_val : 2;
1582 } s;
1583 struct cvmx_gserx_lanex_rx_cfg_5_s cn73xx;
1584 struct cvmx_gserx_lanex_rx_cfg_5_s cn78xx;
1585 struct cvmx_gserx_lanex_rx_cfg_5_s cn78xxp1;
1586 struct cvmx_gserx_lanex_rx_cfg_5_s cnf75xx;
1587 };
1588
1589 typedef union cvmx_gserx_lanex_rx_cfg_5 cvmx_gserx_lanex_rx_cfg_5_t;
1590
1591 /**
1592 * cvmx_gser#_lane#_rx_ctle_ctrl
1593 *
1594 * These are the RAW PCS per-lane RX CTLE control registers.
1595 * These registers are reset by hardware only during chip cold reset. The values of the CSR
1596 * fields in these registers do not change during chip warm or soft resets.
1597 */
1598 union cvmx_gserx_lanex_rx_ctle_ctrl {
1599 u64 u64;
1600 struct cvmx_gserx_lanex_rx_ctle_ctrl_s {
1601 u64 reserved_16_63 : 48;
1602 u64 pcs_sds_rx_ctle_bias_ctrl : 2;
1603 u64 pcs_sds_rx_ctle_zero : 4;
1604 u64 rx_ctle_pole_ovrrd_en : 1;
1605 u64 rx_ctle_pole_ovrrd_val : 4;
1606 u64 pcs_sds_rx_ctle_pole_max : 2;
1607 u64 pcs_sds_rx_ctle_pole_min : 2;
1608 u64 pcs_sds_rx_ctle_pole_step : 1;
1609 } s;
1610 struct cvmx_gserx_lanex_rx_ctle_ctrl_s cn73xx;
1611 struct cvmx_gserx_lanex_rx_ctle_ctrl_s cn78xx;
1612 struct cvmx_gserx_lanex_rx_ctle_ctrl_s cn78xxp1;
1613 struct cvmx_gserx_lanex_rx_ctle_ctrl_s cnf75xx;
1614 };
1615
1616 typedef union cvmx_gserx_lanex_rx_ctle_ctrl cvmx_gserx_lanex_rx_ctle_ctrl_t;
1617
1618 /**
1619 * cvmx_gser#_lane#_rx_misc_ovrrd
1620 *
1621 * These registers are for diagnostic use only.
1622 * These registers are reset by hardware only during chip cold reset.
1623 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1624 */
1625 union cvmx_gserx_lanex_rx_misc_ovrrd {
1626 u64 u64;
1627 struct cvmx_gserx_lanex_rx_misc_ovrrd_s {
1628 u64 reserved_14_63 : 50;
1629 u64 cfg_rx_oob_clk_en_ovrrd_val : 1;
1630 u64 cfg_rx_oob_clk_en_ovrrd_en : 1;
1631 u64 cfg_rx_eie_det_ovrrd_val : 1;
1632 u64 cfg_rx_eie_det_ovrrd_en : 1;
1633 u64 cfg_rx_cdr_ctrl_ovrrd_en : 1;
1634 u64 cfg_rx_eq_eval_ovrrd_val : 1;
1635 u64 cfg_rx_eq_eval_ovrrd_en : 1;
1636 u64 reserved_6_6 : 1;
1637 u64 cfg_rx_dll_locken_ovrrd_en : 1;
1638 u64 cfg_rx_errdet_ctrl_ovrrd_en : 1;
1639 u64 reserved_1_3 : 3;
1640 u64 cfg_rxeq_eval_restore_en : 1;
1641 } s;
1642 struct cvmx_gserx_lanex_rx_misc_ovrrd_cn73xx {
1643 u64 reserved_14_63 : 50;
1644 u64 cfg_rx_oob_clk_en_ovrrd_val : 1;
1645 u64 cfg_rx_oob_clk_en_ovrrd_en : 1;
1646 u64 cfg_rx_eie_det_ovrrd_val : 1;
1647 u64 cfg_rx_eie_det_ovrrd_en : 1;
1648 u64 cfg_rx_cdr_ctrl_ovrrd_en : 1;
1649 u64 cfg_rx_eq_eval_ovrrd_val : 1;
1650 u64 cfg_rx_eq_eval_ovrrd_en : 1;
1651 u64 reserved_6_6 : 1;
1652 u64 cfg_rx_dll_locken_ovrrd_en : 1;
1653 u64 cfg_rx_errdet_ctrl_ovrrd_en : 1;
1654 u64 reserved_3_1 : 3;
1655 u64 cfg_rxeq_eval_restore_en : 1;
1656 } cn73xx;
1657 struct cvmx_gserx_lanex_rx_misc_ovrrd_cn73xx cn78xx;
1658 struct cvmx_gserx_lanex_rx_misc_ovrrd_cn78xxp1 {
1659 u64 reserved_14_63 : 50;
1660 u64 cfg_rx_oob_clk_en_ovrrd_val : 1;
1661 u64 cfg_rx_oob_clk_en_ovrrd_en : 1;
1662 u64 cfg_rx_eie_det_ovrrd_val : 1;
1663 u64 cfg_rx_eie_det_ovrrd_en : 1;
1664 u64 cfg_rx_cdr_ctrl_ovrrd_en : 1;
1665 u64 cfg_rx_eq_eval_ovrrd_val : 1;
1666 u64 cfg_rx_eq_eval_ovrrd_en : 1;
1667 u64 reserved_6_6 : 1;
1668 u64 cfg_rx_dll_locken_ovrrd_en : 1;
1669 u64 cfg_rx_errdet_ctrl_ovrrd_en : 1;
1670 u64 reserved_0_3 : 4;
1671 } cn78xxp1;
1672 struct cvmx_gserx_lanex_rx_misc_ovrrd_cn73xx cnf75xx;
1673 };
1674
1675 typedef union cvmx_gserx_lanex_rx_misc_ovrrd cvmx_gserx_lanex_rx_misc_ovrrd_t;
1676
1677 /**
1678 * cvmx_gser#_lane#_tx_cfg_0
1679 *
1680 * These registers are reset by hardware only during chip cold reset. The
1681 * values of the CSR fields in these registers do not change during chip
1682 * warm or soft resets.
1683 */
1684 union cvmx_gserx_lanex_tx_cfg_0 {
1685 u64 u64;
1686 struct cvmx_gserx_lanex_tx_cfg_0_s {
1687 u64 reserved_16_63 : 48;
1688 u64 tx_tristate_en_ovrrd_val : 1;
1689 u64 tx_chpd_ovrrd_val : 1;
1690 u64 reserved_10_13 : 4;
1691 u64 tx_resetn_ovrrd_val : 1;
1692 u64 tx_cm_mode : 1;
1693 u64 cfg_tx_swing : 5;
1694 u64 fast_rdet_mode : 1;
1695 u64 fast_tristate_mode : 1;
1696 u64 reserved_0_0 : 1;
1697 } s;
1698 struct cvmx_gserx_lanex_tx_cfg_0_cn73xx {
1699 u64 reserved_16_63 : 48;
1700 u64 tx_tristate_en_ovrrd_val : 1;
1701 u64 tx_chpd_ovrrd_val : 1;
1702 u64 reserved_13_10 : 4;
1703 u64 tx_resetn_ovrrd_val : 1;
1704 u64 tx_cm_mode : 1;
1705 u64 cfg_tx_swing : 5;
1706 u64 fast_rdet_mode : 1;
1707 u64 fast_tristate_mode : 1;
1708 u64 reserved_0_0 : 1;
1709 } cn73xx;
1710 struct cvmx_gserx_lanex_tx_cfg_0_cn73xx cn78xx;
1711 struct cvmx_gserx_lanex_tx_cfg_0_s cn78xxp1;
1712 struct cvmx_gserx_lanex_tx_cfg_0_cn73xx cnf75xx;
1713 };
1714
1715 typedef union cvmx_gserx_lanex_tx_cfg_0 cvmx_gserx_lanex_tx_cfg_0_t;
1716
1717 /**
1718 * cvmx_gser#_lane#_tx_cfg_1
1719 *
1720 * These registers are reset by hardware only during chip cold reset. The
1721 * values of the CSR fields in these registers do not change during chip
1722 * warm or soft resets.
1723 */
1724 union cvmx_gserx_lanex_tx_cfg_1 {
1725 u64 u64;
1726 struct cvmx_gserx_lanex_tx_cfg_1_s {
1727 u64 reserved_15_63 : 49;
1728 u64 tx_widthsel_ovrrd_en : 1;
1729 u64 tx_widthsel_ovrrd_val : 2;
1730 u64 tx_vboost_en_ovrrd_en : 1;
1731 u64 tx_turbo_en_ovrrd_en : 1;
1732 u64 tx_swing_ovrrd_en : 1;
1733 u64 tx_premptap_ovrrd_val : 1;
1734 u64 tx_elec_idle_ovrrd_en : 1;
1735 u64 smpl_rate_ovrrd_en : 1;
1736 u64 smpl_rate_ovrrd_val : 3;
1737 u64 tx_datarate_ovrrd_en : 1;
1738 u64 tx_datarate_ovrrd_val : 2;
1739 } s;
1740 struct cvmx_gserx_lanex_tx_cfg_1_s cn73xx;
1741 struct cvmx_gserx_lanex_tx_cfg_1_s cn78xx;
1742 struct cvmx_gserx_lanex_tx_cfg_1_s cn78xxp1;
1743 struct cvmx_gserx_lanex_tx_cfg_1_s cnf75xx;
1744 };
1745
1746 typedef union cvmx_gserx_lanex_tx_cfg_1 cvmx_gserx_lanex_tx_cfg_1_t;
1747
1748 /**
1749 * cvmx_gser#_lane#_tx_cfg_2
1750 *
1751 * These registers are for diagnostic use only. These registers are reset by hardware only during
1752 * chip cold reset. The values of the CSR fields in these registers do not change during chip
1753 * warm or soft resets.
1754 */
1755 union cvmx_gserx_lanex_tx_cfg_2 {
1756 u64 u64;
1757 struct cvmx_gserx_lanex_tx_cfg_2_s {
1758 u64 reserved_16_63 : 48;
1759 u64 pcs_sds_tx_dcc_en : 1;
1760 u64 reserved_3_14 : 12;
1761 u64 rcvr_test_ovrrd_en : 1;
1762 u64 rcvr_test_ovrrd_val : 1;
1763 u64 tx_rx_detect_dis_ovrrd_val : 1;
1764 } s;
1765 struct cvmx_gserx_lanex_tx_cfg_2_cn73xx {
1766 u64 reserved_16_63 : 48;
1767 u64 pcs_sds_tx_dcc_en : 1;
1768 u64 reserved_14_3 : 12;
1769 u64 rcvr_test_ovrrd_en : 1;
1770 u64 rcvr_test_ovrrd_val : 1;
1771 u64 tx_rx_detect_dis_ovrrd_val : 1;
1772 } cn73xx;
1773 struct cvmx_gserx_lanex_tx_cfg_2_cn73xx cn78xx;
1774 struct cvmx_gserx_lanex_tx_cfg_2_s cn78xxp1;
1775 struct cvmx_gserx_lanex_tx_cfg_2_cn73xx cnf75xx;
1776 };
1777
1778 typedef union cvmx_gserx_lanex_tx_cfg_2 cvmx_gserx_lanex_tx_cfg_2_t;
1779
1780 /**
1781 * cvmx_gser#_lane#_tx_cfg_3
1782 *
1783 * These registers are for diagnostic use only. These registers are reset by hardware only during
1784 * chip cold reset. The values of the CSR fields in these registers do not change during chip
1785 * warm or soft resets.
1786 */
1787 union cvmx_gserx_lanex_tx_cfg_3 {
1788 u64 u64;
1789 struct cvmx_gserx_lanex_tx_cfg_3_s {
1790 u64 reserved_15_63 : 49;
1791 u64 cfg_tx_vboost_en : 1;
1792 u64 reserved_7_13 : 7;
1793 u64 pcs_sds_tx_gain : 3;
1794 u64 pcs_sds_tx_srate_sel : 3;
1795 u64 cfg_tx_turbo_en : 1;
1796 } s;
1797 struct cvmx_gserx_lanex_tx_cfg_3_cn73xx {
1798 u64 reserved_15_63 : 49;
1799 u64 cfg_tx_vboost_en : 1;
1800 u64 reserved_13_7 : 7;
1801 u64 pcs_sds_tx_gain : 3;
1802 u64 pcs_sds_tx_srate_sel : 3;
1803 u64 cfg_tx_turbo_en : 1;
1804 } cn73xx;
1805 struct cvmx_gserx_lanex_tx_cfg_3_cn73xx cn78xx;
1806 struct cvmx_gserx_lanex_tx_cfg_3_s cn78xxp1;
1807 struct cvmx_gserx_lanex_tx_cfg_3_cn73xx cnf75xx;
1808 };
1809
1810 typedef union cvmx_gserx_lanex_tx_cfg_3 cvmx_gserx_lanex_tx_cfg_3_t;
1811
1812 /**
1813 * cvmx_gser#_lane#_tx_pre_emphasis
1814 *
1815 * These registers are reset by hardware only during chip cold reset. The
1816 * values of the CSR fields in these registers do not change during chip
1817 * warm or soft resets.
1818 */
1819 union cvmx_gserx_lanex_tx_pre_emphasis {
1820 u64 u64;
1821 struct cvmx_gserx_lanex_tx_pre_emphasis_s {
1822 u64 reserved_9_63 : 55;
1823 u64 cfg_tx_premptap : 9;
1824 } s;
1825 struct cvmx_gserx_lanex_tx_pre_emphasis_s cn73xx;
1826 struct cvmx_gserx_lanex_tx_pre_emphasis_s cn78xx;
1827 struct cvmx_gserx_lanex_tx_pre_emphasis_s cn78xxp1;
1828 struct cvmx_gserx_lanex_tx_pre_emphasis_s cnf75xx;
1829 };
1830
1831 typedef union cvmx_gserx_lanex_tx_pre_emphasis cvmx_gserx_lanex_tx_pre_emphasis_t;
1832
1833 /**
1834 * cvmx_gser#_lane#_pcs_ctlifc_0
1835 *
1836 * These registers are for diagnostic use only.
1837 * These registers are reset by hardware only during chip cold reset.
1838 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1839 */
1840 union cvmx_gserx_lanex_pcs_ctlifc_0 {
1841 u64 u64;
1842 struct cvmx_gserx_lanex_pcs_ctlifc_0_s {
1843 u64 reserved_14_63 : 50;
1844 u64 cfg_tx_vboost_en_ovrrd_val : 1;
1845 u64 cfg_tx_coeff_req_ovrrd_val : 1;
1846 u64 cfg_rx_cdr_coast_req_ovrrd_val : 1;
1847 u64 cfg_tx_detrx_en_req_ovrrd_val : 1;
1848 u64 cfg_soft_reset_req_ovrrd_val : 1;
1849 u64 cfg_lane_pwr_off_ovrrd_val : 1;
1850 u64 cfg_tx_mode_ovrrd_val : 2;
1851 u64 cfg_tx_pstate_req_ovrrd_val : 2;
1852 u64 cfg_lane_mode_req_ovrrd_val : 4;
1853 } s;
1854 struct cvmx_gserx_lanex_pcs_ctlifc_0_s cn73xx;
1855 struct cvmx_gserx_lanex_pcs_ctlifc_0_s cn78xx;
1856 struct cvmx_gserx_lanex_pcs_ctlifc_0_s cn78xxp1;
1857 struct cvmx_gserx_lanex_pcs_ctlifc_0_s cnf75xx;
1858 };
1859
1860 typedef union cvmx_gserx_lanex_pcs_ctlifc_0 cvmx_gserx_lanex_pcs_ctlifc_0_t;
1861
1862 /**
1863 * cvmx_gser#_lane#_pcs_ctlifc_1
1864 *
1865 * These registers are for diagnostic use only.
1866 * These registers are reset by hardware only during chip cold reset.
1867 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1868 */
1869 union cvmx_gserx_lanex_pcs_ctlifc_1 {
1870 u64 u64;
1871 struct cvmx_gserx_lanex_pcs_ctlifc_1_s {
1872 u64 reserved_9_63 : 55;
1873 u64 cfg_rx_pstate_req_ovrrd_val : 2;
1874 u64 reserved_2_6 : 5;
1875 u64 cfg_rx_mode_ovrrd_val : 2;
1876 } s;
1877 struct cvmx_gserx_lanex_pcs_ctlifc_1_cn73xx {
1878 u64 reserved_9_63 : 55;
1879 u64 cfg_rx_pstate_req_ovrrd_val : 2;
1880 u64 reserved_6_2 : 5;
1881 u64 cfg_rx_mode_ovrrd_val : 2;
1882 } cn73xx;
1883 struct cvmx_gserx_lanex_pcs_ctlifc_1_cn73xx cn78xx;
1884 struct cvmx_gserx_lanex_pcs_ctlifc_1_s cn78xxp1;
1885 struct cvmx_gserx_lanex_pcs_ctlifc_1_cn73xx cnf75xx;
1886 };
1887
1888 typedef union cvmx_gserx_lanex_pcs_ctlifc_1 cvmx_gserx_lanex_pcs_ctlifc_1_t;
1889
1890 /**
1891 * cvmx_gser#_lane#_pcs_ctlifc_2
1892 *
1893 * These registers are for diagnostic use only.
1894 * These registers are reset by hardware only during chip cold reset.
1895 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1896 */
1897 union cvmx_gserx_lanex_pcs_ctlifc_2 {
1898 u64 u64;
1899 struct cvmx_gserx_lanex_pcs_ctlifc_2_s {
1900 u64 reserved_16_63 : 48;
1901 u64 ctlifc_ovrrd_req : 1;
1902 u64 reserved_9_14 : 6;
1903 u64 cfg_tx_vboost_en_ovrrd_en : 1;
1904 u64 cfg_tx_coeff_req_ovrrd_en : 1;
1905 u64 cfg_rx_cdr_coast_req_ovrrd_en : 1;
1906 u64 cfg_tx_detrx_en_req_ovrrd_en : 1;
1907 u64 cfg_soft_reset_req_ovrrd_en : 1;
1908 u64 cfg_lane_pwr_off_ovrrd_en : 1;
1909 u64 cfg_tx_pstate_req_ovrrd_en : 1;
1910 u64 cfg_rx_pstate_req_ovrrd_en : 1;
1911 u64 cfg_lane_mode_req_ovrrd_en : 1;
1912 } s;
1913 struct cvmx_gserx_lanex_pcs_ctlifc_2_cn73xx {
1914 u64 reserved_16_63 : 48;
1915 u64 ctlifc_ovrrd_req : 1;
1916 u64 reserved_14_9 : 6;
1917 u64 cfg_tx_vboost_en_ovrrd_en : 1;
1918 u64 cfg_tx_coeff_req_ovrrd_en : 1;
1919 u64 cfg_rx_cdr_coast_req_ovrrd_en : 1;
1920 u64 cfg_tx_detrx_en_req_ovrrd_en : 1;
1921 u64 cfg_soft_reset_req_ovrrd_en : 1;
1922 u64 cfg_lane_pwr_off_ovrrd_en : 1;
1923 u64 cfg_tx_pstate_req_ovrrd_en : 1;
1924 u64 cfg_rx_pstate_req_ovrrd_en : 1;
1925 u64 cfg_lane_mode_req_ovrrd_en : 1;
1926 } cn73xx;
1927 struct cvmx_gserx_lanex_pcs_ctlifc_2_cn73xx cn78xx;
1928 struct cvmx_gserx_lanex_pcs_ctlifc_2_s cn78xxp1;
1929 struct cvmx_gserx_lanex_pcs_ctlifc_2_cn73xx cnf75xx;
1930 };
1931
1932 typedef union cvmx_gserx_lanex_pcs_ctlifc_2 cvmx_gserx_lanex_pcs_ctlifc_2_t;
1933
1934 /**
1935 * cvmx_gser#_lane_mode
1936 *
1937 * These registers are reset by hardware only during chip cold reset. The values of the CSR
1938 * fields in these registers do not change during chip warm or soft resets.
1939 */
1940 union cvmx_gserx_lane_mode {
1941 u64 u64;
1942 struct cvmx_gserx_lane_mode_s {
1943 u64 reserved_4_63 : 60;
1944 u64 lmode : 4;
1945 } s;
1946 struct cvmx_gserx_lane_mode_s cn73xx;
1947 struct cvmx_gserx_lane_mode_s cn78xx;
1948 struct cvmx_gserx_lane_mode_s cn78xxp1;
1949 struct cvmx_gserx_lane_mode_s cnf75xx;
1950 };
1951
1952 typedef union cvmx_gserx_lane_mode cvmx_gserx_lane_mode_t;
1953
1954 /**
1955 * cvmx_gser#_pll_p#_mode_0
1956 *
1957 * These are the RAW PCS PLL global settings mode 0 registers. There is one register per GSER per
1958 * GSER_LMODE_E value (0..11). Only one entry is used at any given time in a given GSER - the one
1959 * selected by the corresponding GSER()_LANE_MODE[LMODE].
1960 * These registers are reset by hardware only during chip cold reset.
1961 * The values of the CSR fields in these registers do not change during subsequent chip warm or
1962 * soft resets.
1963 */
1964 union cvmx_gserx_pll_px_mode_0 {
1965 u64 u64;
1966 struct cvmx_gserx_pll_px_mode_0_s {
1967 u64 reserved_16_63 : 48;
1968 u64 pll_icp : 4;
1969 u64 pll_rloop : 3;
1970 u64 pll_pcs_div : 9;
1971 } s;
1972 struct cvmx_gserx_pll_px_mode_0_s cn73xx;
1973 struct cvmx_gserx_pll_px_mode_0_s cn78xx;
1974 struct cvmx_gserx_pll_px_mode_0_s cn78xxp1;
1975 struct cvmx_gserx_pll_px_mode_0_s cnf75xx;
1976 };
1977
1978 typedef union cvmx_gserx_pll_px_mode_0 cvmx_gserx_pll_px_mode_0_t;
1979
1980 /**
1981 * cvmx_gser#_pll_p#_mode_1
1982 *
1983 * These are the RAW PCS PLL global settings mode 1 registers. There is one register per GSER per
1984 * GSER_LMODE_E value (0..11). Only one entry is used at any given time in a given GSER - the one
1985 * selected by the corresponding GSER()_LANE_MODE[LMODE].
1986 * These registers are reset by hardware only during chip cold reset.
1987 * The values of the CSR fields in this register do not change during subsequent chip warm or
1988 * soft resets.
1989 */
1990 union cvmx_gserx_pll_px_mode_1 {
1991 u64 u64;
1992 struct cvmx_gserx_pll_px_mode_1_s {
1993 u64 reserved_14_63 : 50;
1994 u64 pll_16p5en : 1;
1995 u64 pll_cpadj : 2;
1996 u64 pll_pcie3en : 1;
1997 u64 pll_opr : 1;
1998 u64 pll_div : 9;
1999 } s;
2000 struct cvmx_gserx_pll_px_mode_1_s cn73xx;
2001 struct cvmx_gserx_pll_px_mode_1_s cn78xx;
2002 struct cvmx_gserx_pll_px_mode_1_s cn78xxp1;
2003 struct cvmx_gserx_pll_px_mode_1_s cnf75xx;
2004 };
2005
2006 typedef union cvmx_gserx_pll_px_mode_1 cvmx_gserx_pll_px_mode_1_t;
2007
2008 /**
2009 * cvmx_gser#_pll_stat
2010 */
2011 union cvmx_gserx_pll_stat {
2012 u64 u64;
2013 struct cvmx_gserx_pll_stat_s {
2014 u64 reserved_1_63 : 63;
2015 u64 pll_lock : 1;
2016 } s;
2017 struct cvmx_gserx_pll_stat_s cn73xx;
2018 struct cvmx_gserx_pll_stat_s cn78xx;
2019 struct cvmx_gserx_pll_stat_s cn78xxp1;
2020 struct cvmx_gserx_pll_stat_s cnf75xx;
2021 };
2022
2023 typedef union cvmx_gserx_pll_stat cvmx_gserx_pll_stat_t;
2024
2025 /**
2026 * cvmx_gser#_qlm_stat
2027 */
2028 union cvmx_gserx_qlm_stat {
2029 u64 u64;
2030 struct cvmx_gserx_qlm_stat_s {
2031 u64 reserved_2_63 : 62;
2032 u64 rst_rdy : 1;
2033 u64 dcok : 1;
2034 } s;
2035 struct cvmx_gserx_qlm_stat_s cn73xx;
2036 struct cvmx_gserx_qlm_stat_s cn78xx;
2037 struct cvmx_gserx_qlm_stat_s cn78xxp1;
2038 struct cvmx_gserx_qlm_stat_s cnf75xx;
2039 };
2040
2041 typedef union cvmx_gserx_qlm_stat cvmx_gserx_qlm_stat_t;
2042
2043 /**
2044 * cvmx_gser#_slice_cfg
2045 *
2046 * These registers are for diagnostic use only.
2047 * These registers are reset by hardware only during chip cold reset.
2048 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2049 */
2050 union cvmx_gserx_slice_cfg {
2051 u64 u64;
2052 struct cvmx_gserx_slice_cfg_s {
2053 u64 reserved_12_63 : 52;
2054 u64 tx_rx_detect_lvl_enc : 4;
2055 u64 reserved_6_7 : 2;
2056 u64 pcs_sds_rx_pcie_pterm : 2;
2057 u64 pcs_sds_rx_pcie_nterm : 2;
2058 u64 pcs_sds_tx_stress_eye : 2;
2059 } s;
2060 struct cvmx_gserx_slice_cfg_cn73xx {
2061 u64 reserved_12_63 : 52;
2062 u64 tx_rx_detect_lvl_enc : 4;
2063 u64 reserved_7_6 : 2;
2064 u64 pcs_sds_rx_pcie_pterm : 2;
2065 u64 pcs_sds_rx_pcie_nterm : 2;
2066 u64 pcs_sds_tx_stress_eye : 2;
2067 } cn73xx;
2068 struct cvmx_gserx_slice_cfg_cn73xx cn78xx;
2069 struct cvmx_gserx_slice_cfg_s cn78xxp1;
2070 struct cvmx_gserx_slice_cfg_cn73xx cnf75xx;
2071 };
2072
2073 typedef union cvmx_gserx_slice_cfg cvmx_gserx_slice_cfg_t;
2074
2075 /**
2076 * cvmx_gser#_slice#_pcie1_mode
2077 *
2078 * These registers are for diagnostic use only.
2079 * These registers are reset by hardware only during chip cold reset.
2080 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2081 *
2082 * Slice 1 does not exist on GSER0, GSER1, GSER4, GSER5, GSER6, GSER7, and GSER8.
2083 */
2084 union cvmx_gserx_slicex_pcie1_mode {
2085 u64 u64;
2086 struct cvmx_gserx_slicex_pcie1_mode_s {
2087 u64 reserved_15_63 : 49;
2088 u64 slice_spare_1_0 : 2;
2089 u64 rx_ldll_isel : 2;
2090 u64 rx_sdll_isel : 2;
2091 u64 rx_pi_bwsel : 3;
2092 u64 rx_ldll_bwsel : 3;
2093 u64 rx_sdll_bwsel : 3;
2094 } s;
2095 struct cvmx_gserx_slicex_pcie1_mode_s cn73xx;
2096 struct cvmx_gserx_slicex_pcie1_mode_s cn78xx;
2097 struct cvmx_gserx_slicex_pcie1_mode_s cn78xxp1;
2098 struct cvmx_gserx_slicex_pcie1_mode_s cnf75xx;
2099 };
2100
2101 typedef union cvmx_gserx_slicex_pcie1_mode cvmx_gserx_slicex_pcie1_mode_t;
2102
2103 /**
2104 * cvmx_gser#_slice#_pcie2_mode
2105 *
2106 * These registers are for diagnostic use only.
2107 * These registers are reset by hardware only during chip cold reset.
2108 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2109 *
2110 * Slice 1 does not exist on GSER0, GSER1, GSER4, GSER5, GSER6, GSER7, and GSER8.
2111 */
2112 union cvmx_gserx_slicex_pcie2_mode {
2113 u64 u64;
2114 struct cvmx_gserx_slicex_pcie2_mode_s {
2115 u64 reserved_15_63 : 49;
2116 u64 slice_spare_1_0 : 2;
2117 u64 rx_ldll_isel : 2;
2118 u64 rx_sdll_isel : 2;
2119 u64 rx_pi_bwsel : 3;
2120 u64 rx_ldll_bwsel : 3;
2121 u64 rx_sdll_bwsel : 3;
2122 } s;
2123 struct cvmx_gserx_slicex_pcie2_mode_s cn73xx;
2124 struct cvmx_gserx_slicex_pcie2_mode_s cn78xx;
2125 struct cvmx_gserx_slicex_pcie2_mode_s cn78xxp1;
2126 struct cvmx_gserx_slicex_pcie2_mode_s cnf75xx;
2127 };
2128
2129 typedef union cvmx_gserx_slicex_pcie2_mode cvmx_gserx_slicex_pcie2_mode_t;
2130
2131 /**
2132 * cvmx_gser#_slice#_pcie3_mode
2133 *
2134 * These registers are for diagnostic use only.
2135 * These registers are reset by hardware only during chip cold reset.
2136 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2137 *
2138 * Slice 1 does not exist on GSER0, GSER1, GSER4, GSER5, GSER6, GSER7, and GSER8.
2139 */
2140 union cvmx_gserx_slicex_pcie3_mode {
2141 u64 u64;
2142 struct cvmx_gserx_slicex_pcie3_mode_s {
2143 u64 reserved_15_63 : 49;
2144 u64 slice_spare_1_0 : 2;
2145 u64 rx_ldll_isel : 2;
2146 u64 rx_sdll_isel : 2;
2147 u64 rx_pi_bwsel : 3;
2148 u64 rx_ldll_bwsel : 3;
2149 u64 rx_sdll_bwsel : 3;
2150 } s;
2151 struct cvmx_gserx_slicex_pcie3_mode_s cn73xx;
2152 struct cvmx_gserx_slicex_pcie3_mode_s cn78xx;
2153 struct cvmx_gserx_slicex_pcie3_mode_s cn78xxp1;
2154 struct cvmx_gserx_slicex_pcie3_mode_s cnf75xx;
2155 };
2156
2157 typedef union cvmx_gserx_slicex_pcie3_mode cvmx_gserx_slicex_pcie3_mode_t;
2158
2159 /**
2160 * cvmx_gser#_slice#_rx_sdll_ctrl
2161 *
2162 * These registers are for diagnostic use only.
2163 * These registers are reset by hardware only during chip cold reset.
2164 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2165 *
2166 * Slice 1 does not exist on GSER0, GSER1, GSER4, GSER5, GSER6, GSER7, and GSER8.
2167 */
2168 union cvmx_gserx_slicex_rx_sdll_ctrl {
2169 u64 u64;
2170 struct cvmx_gserx_slicex_rx_sdll_ctrl_s {
2171 u64 reserved_16_63 : 48;
2172 u64 pcs_sds_oob_clk_ctrl : 2;
2173 u64 reserved_7_13 : 7;
2174 u64 pcs_sds_rx_sdll_tune : 3;
2175 u64 pcs_sds_rx_sdll_swsel : 4;
2176 } s;
2177 struct cvmx_gserx_slicex_rx_sdll_ctrl_cn73xx {
2178 u64 reserved_16_63 : 48;
2179 u64 pcs_sds_oob_clk_ctrl : 2;
2180 u64 reserved_13_7 : 7;
2181 u64 pcs_sds_rx_sdll_tune : 3;
2182 u64 pcs_sds_rx_sdll_swsel : 4;
2183 } cn73xx;
2184 struct cvmx_gserx_slicex_rx_sdll_ctrl_cn73xx cn78xx;
2185 struct cvmx_gserx_slicex_rx_sdll_ctrl_s cn78xxp1;
2186 struct cvmx_gserx_slicex_rx_sdll_ctrl_cn73xx cnf75xx;
2187 };
2188
2189 typedef union cvmx_gserx_slicex_rx_sdll_ctrl cvmx_gserx_slicex_rx_sdll_ctrl_t;
2190
2191 #endif
2192