1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2005 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 /* 8 * TQM8349 board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_E300 1 /* E300 Family */ 18 19 /* board pre init: do not call, nothing to do */ 20 21 /* detect the number of flash banks */ 22 23 /* 24 * DDR Setup 25 */ 26 /* DDR is system memory*/ 27 #define CONFIG_SYS_SDRAM_BASE 0x00000000 28 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 29 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 30 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 31 32 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 33 34 /* 35 * FLASH on the Local Bus 36 */ 37 #undef CONFIG_SYS_FLASH_CHECKSUM 38 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 39 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 40 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 41 42 /* 43 * FLASH bank number detection 44 */ 45 46 /* 47 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 48 * Flash banks has to be determined at runtime and stored in a gloabl variable 49 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 50 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 51 * flash_info, and should be made sufficiently large to accomodate the number 52 * of banks that might actually be detected. Since most (all?) Flash related 53 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 54 * the board, it is defined as tqm834x_num_flash_banks. 55 */ 56 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 57 58 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 59 60 61 /* disable remaining mappings */ 62 #define CONFIG_SYS_BR1_PRELIM 0x00000000 63 #define CONFIG_SYS_OR1_PRELIM 0x00000000 64 65 #define CONFIG_SYS_BR2_PRELIM 0x00000000 66 #define CONFIG_SYS_OR2_PRELIM 0x00000000 67 68 #define CONFIG_SYS_BR3_PRELIM 0x00000000 69 #define CONFIG_SYS_OR3_PRELIM 0x00000000 70 71 /* 72 * Monitor config 73 */ 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75 76 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 77 # define CONFIG_SYS_RAMBOOT 78 #else 79 # undef CONFIG_SYS_RAMBOOT 80 #endif 81 82 #define CONFIG_SYS_INIT_RAM_LOCK 1 83 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 84 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 85 86 #define CONFIG_SYS_GBL_DATA_OFFSET \ 87 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 88 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 89 90 /* Reserve 384 kB = 3 sect. for Mon */ 91 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 92 /* Reserve 512 kB for malloc */ 93 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 94 95 /* 96 * Serial Port 97 */ 98 #define CONFIG_SYS_NS16550_SERIAL 99 #define CONFIG_SYS_NS16550_REG_SIZE 1 100 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 101 102 #define CONFIG_SYS_BAUDRATE_TABLE \ 103 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 104 105 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 106 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 107 108 /* 109 * I2C 110 */ 111 #define CONFIG_SYS_I2C 112 #define CONFIG_SYS_I2C_FSL 113 #define CONFIG_SYS_FSL_I2C_SPEED 400000 114 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 115 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 116 117 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 118 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 119 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 120 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 121 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 122 123 /* I2C RTC */ 124 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 125 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 126 127 /* 128 * TSEC 129 */ 130 131 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 132 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 133 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 134 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 135 136 #if defined(CONFIG_TSEC_ENET) 137 138 #define CONFIG_TSEC1 1 139 #define CONFIG_TSEC1_NAME "TSEC0" 140 #define CONFIG_TSEC2 1 141 #define CONFIG_TSEC2_NAME "TSEC1" 142 #define TSEC1_PHY_ADDR 2 143 #define TSEC2_PHY_ADDR 1 144 #define TSEC1_PHYIDX 0 145 #define TSEC2_PHYIDX 0 146 #define TSEC1_FLAGS TSEC_GIGABIT 147 #define TSEC2_FLAGS TSEC_GIGABIT 148 149 /* Options are: TSEC[0-1] */ 150 #define CONFIG_ETHPRIME "TSEC0" 151 152 #endif /* CONFIG_TSEC_ENET */ 153 154 #if defined(CONFIG_PCI) 155 156 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 157 158 /* PCI1 host bridge */ 159 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 160 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 161 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 162 #define CONFIG_SYS_PCI1_MMIO_BASE \ 163 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 164 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 165 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 166 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 167 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 168 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 169 170 171 #if !defined(CONFIG_PCI_PNP) 172 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 173 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 174 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 175 #endif 176 177 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 178 179 #endif /* CONFIG_PCI */ 180 181 /* 182 * Environment 183 */ 184 185 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 186 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 187 188 /* 189 * BOOTP options 190 */ 191 #define CONFIG_BOOTP_BOOTFILESIZE 192 193 /* 194 * Miscellaneous configurable options 195 */ 196 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 197 198 #undef CONFIG_WATCHDOG /* watchdog disabled */ 199 200 /* 201 * For booting Linux, the board info and command line data 202 * have to be in the first 256 MB of memory, since this is 203 * the maximum mapped by the Linux kernel during initialization. 204 */ 205 /* Initial Memory map for Linux */ 206 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 207 208 /* System IO Config */ 209 #define CONFIG_SYS_SICRH 0 210 #define CONFIG_SYS_SICRL SICRL_LDP_A 211 212 /* PCI */ 213 #ifdef CONFIG_PCI 214 #define CONFIG_PCI_INDIRECT_BRIDGE 215 #endif 216 217 #if defined(CONFIG_CMD_KGDB) 218 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 219 #endif 220 221 /* 222 * Environment Configuration 223 */ 224 225 /* default location for tftp and bootm */ 226 #define CONFIG_LOADADDR 400000 227 228 #define CONFIG_EXTRA_ENV_SETTINGS \ 229 "netdev=eth0\0" \ 230 "hostname=tqm834x\0" \ 231 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 232 "nfsroot=${serverip}:${rootpath}\0" \ 233 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 234 "addip=setenv bootargs ${bootargs} " \ 235 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 236 ":${hostname}:${netdev}:off panic=1\0" \ 237 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 238 "flash_nfs_old=run nfsargs addip addcons;" \ 239 "bootm ${kernel_addr}\0" \ 240 "flash_nfs=run nfsargs addip addcons;" \ 241 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 242 "flash_self_old=run ramargs addip addcons;" \ 243 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 244 "flash_self=run ramargs addip addcons;" \ 245 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 246 "net_nfs_old=tftp 400000 ${bootfile};" \ 247 "run nfsargs addip addcons;bootm\0" \ 248 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 249 "tftp ${fdt_addr_r} ${fdt_file}; " \ 250 "run nfsargs addip addcons; " \ 251 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 252 "rootpath=/opt/eldk/ppc_6xx\0" \ 253 "bootfile=tqm834x/uImage\0" \ 254 "fdtfile=tqm834x/tqm834x.dtb\0" \ 255 "kernel_addr_r=400000\0" \ 256 "fdt_addr_r=600000\0" \ 257 "ramdisk_addr_r=800000\0" \ 258 "kernel_addr=800C0000\0" \ 259 "fdt_addr=800A0000\0" \ 260 "ramdisk_addr=80300000\0" \ 261 "u-boot=tqm834x/u-boot.bin\0" \ 262 "load=tftp 200000 ${u-boot}\0" \ 263 "update=protect off 80000000 +${filesize};" \ 264 "era 80000000 +${filesize};" \ 265 "cp.b 200000 80000000 ${filesize}\0" \ 266 "upd=run load update\0" \ 267 "" 268 269 #define CONFIG_BOOTCOMMAND "run flash_self" 270 271 /* 272 * JFFS2 partitions 273 */ 274 /* mtdparts command line support */ 275 276 /* default mtd partition table */ 277 #endif /* __CONFIG_H */ 278