1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2012 Samsung Electronics.
4 * Abhilash Kesavan <a.kesavan@samsung.com>
5 */
6
7 #include <common.h>
8 #include <fdtdec.h>
9 #include <log.h>
10 #include <asm/gpio.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/sromc.h>
13
exynos5_uart_config(int peripheral)14 static void exynos5_uart_config(int peripheral)
15 {
16 int i, start, count;
17
18 switch (peripheral) {
19 case PERIPH_ID_UART0:
20 start = EXYNOS5_GPIO_A00;
21 count = 4;
22 break;
23 case PERIPH_ID_UART1:
24 start = EXYNOS5_GPIO_D00;
25 count = 4;
26 break;
27 case PERIPH_ID_UART2:
28 start = EXYNOS5_GPIO_A10;
29 count = 4;
30 break;
31 case PERIPH_ID_UART3:
32 start = EXYNOS5_GPIO_A14;
33 count = 2;
34 break;
35 default:
36 debug("%s: invalid peripheral %d", __func__, peripheral);
37 return;
38 }
39 for (i = start; i < start + count; i++) {
40 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
41 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
42 }
43 }
44
exynos5420_uart_config(int peripheral)45 static void exynos5420_uart_config(int peripheral)
46 {
47 int i, start, count;
48
49 switch (peripheral) {
50 case PERIPH_ID_UART0:
51 start = EXYNOS5420_GPIO_A00;
52 count = 4;
53 break;
54 case PERIPH_ID_UART1:
55 start = EXYNOS5420_GPIO_A04;
56 count = 4;
57 break;
58 case PERIPH_ID_UART2:
59 start = EXYNOS5420_GPIO_A10;
60 count = 4;
61 break;
62 case PERIPH_ID_UART3:
63 start = EXYNOS5420_GPIO_A14;
64 count = 2;
65 break;
66 default:
67 debug("%s: invalid peripheral %d", __func__, peripheral);
68 return;
69 }
70
71 for (i = start; i < start + count; i++) {
72 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
73 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
74 }
75 }
76
exynos5_mmc_config(int peripheral,int flags)77 static int exynos5_mmc_config(int peripheral, int flags)
78 {
79 int i, start, start_ext, gpio_func = 0;
80
81 switch (peripheral) {
82 case PERIPH_ID_SDMMC0:
83 start = EXYNOS5_GPIO_C00;
84 start_ext = EXYNOS5_GPIO_C10;
85 gpio_func = S5P_GPIO_FUNC(0x2);
86 break;
87 case PERIPH_ID_SDMMC1:
88 start = EXYNOS5_GPIO_C20;
89 start_ext = 0;
90 break;
91 case PERIPH_ID_SDMMC2:
92 start = EXYNOS5_GPIO_C30;
93 start_ext = EXYNOS5_GPIO_C43;
94 gpio_func = S5P_GPIO_FUNC(0x3);
95 break;
96 case PERIPH_ID_SDMMC3:
97 start = EXYNOS5_GPIO_C40;
98 start_ext = 0;
99 break;
100 default:
101 debug("%s: invalid peripheral %d", __func__, peripheral);
102 return -1;
103 }
104 if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
105 debug("SDMMC device %d does not support 8bit mode",
106 peripheral);
107 return -1;
108 }
109 if (flags & PINMUX_FLAG_8BIT_MODE) {
110 for (i = start_ext; i <= (start_ext + 3); i++) {
111 gpio_cfg_pin(i, gpio_func);
112 gpio_set_pull(i, S5P_GPIO_PULL_UP);
113 gpio_set_drv(i, S5P_GPIO_DRV_4X);
114 }
115 }
116 for (i = start; i < (start + 2); i++) {
117 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
118 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
119 gpio_set_drv(i, S5P_GPIO_DRV_4X);
120 }
121 for (i = (start + 3); i <= (start + 6); i++) {
122 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
123 gpio_set_pull(i, S5P_GPIO_PULL_UP);
124 gpio_set_drv(i, S5P_GPIO_DRV_4X);
125 }
126
127 return 0;
128 }
129
exynos5420_mmc_config(int peripheral,int flags)130 static int exynos5420_mmc_config(int peripheral, int flags)
131 {
132 int i, start = 0, start_ext = 0;
133
134 switch (peripheral) {
135 case PERIPH_ID_SDMMC0:
136 start = EXYNOS5420_GPIO_C00;
137 start_ext = EXYNOS5420_GPIO_C30;
138 break;
139 case PERIPH_ID_SDMMC1:
140 start = EXYNOS5420_GPIO_C10;
141 start_ext = EXYNOS5420_GPIO_D14;
142 break;
143 case PERIPH_ID_SDMMC2:
144 start = EXYNOS5420_GPIO_C20;
145 start_ext = 0;
146 break;
147 default:
148 start = 0;
149 debug("%s: invalid peripheral %d", __func__, peripheral);
150 return -1;
151 }
152
153 if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
154 debug("SDMMC device %d does not support 8bit mode",
155 peripheral);
156 return -1;
157 }
158
159 if (flags & PINMUX_FLAG_8BIT_MODE) {
160 for (i = start_ext; i <= (start_ext + 3); i++) {
161 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
162 gpio_set_pull(i, S5P_GPIO_PULL_UP);
163 gpio_set_drv(i, S5P_GPIO_DRV_4X);
164 }
165 }
166
167 for (i = start; i < (start + 3); i++) {
168 /*
169 * MMC0 is intended to be used for eMMC. The
170 * card detect pin is used as a VDDEN signal to
171 * power on the eMMC. The 5420 iROM makes
172 * this same assumption.
173 */
174 if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
175 #ifndef CONFIG_SPL_BUILD
176 gpio_request(i, "sdmmc0_vdden");
177 #endif
178 gpio_set_value(i, 1);
179 gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
180 } else {
181 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
182 }
183 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
184 gpio_set_drv(i, S5P_GPIO_DRV_4X);
185 }
186
187 for (i = (start + 3); i <= (start + 6); i++) {
188 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
189 gpio_set_pull(i, S5P_GPIO_PULL_UP);
190 gpio_set_drv(i, S5P_GPIO_DRV_4X);
191 }
192
193 return 0;
194 }
195
exynos5_sromc_config(int flags)196 static void exynos5_sromc_config(int flags)
197 {
198 int i;
199
200 /*
201 * SROM:CS1 and EBI
202 *
203 * GPY0[0] SROM_CSn[0]
204 * GPY0[1] SROM_CSn[1](2)
205 * GPY0[2] SROM_CSn[2]
206 * GPY0[3] SROM_CSn[3]
207 * GPY0[4] EBI_OEn(2)
208 * GPY0[5] EBI_EEn(2)
209 *
210 * GPY1[0] EBI_BEn[0](2)
211 * GPY1[1] EBI_BEn[1](2)
212 * GPY1[2] SROM_WAIT(2)
213 * GPY1[3] EBI_DATA_RDn(2)
214 */
215 gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
216 S5P_GPIO_FUNC(2));
217 gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
218 gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
219
220 for (i = 0; i < 4; i++)
221 gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
222
223 /*
224 * EBI: 8 Addrss Lines
225 *
226 * GPY3[0] EBI_ADDR[0](2)
227 * GPY3[1] EBI_ADDR[1](2)
228 * GPY3[2] EBI_ADDR[2](2)
229 * GPY3[3] EBI_ADDR[3](2)
230 * GPY3[4] EBI_ADDR[4](2)
231 * GPY3[5] EBI_ADDR[5](2)
232 * GPY3[6] EBI_ADDR[6](2)
233 * GPY3[7] EBI_ADDR[7](2)
234 *
235 * EBI: 16 Data Lines
236 *
237 * GPY5[0] EBI_DATA[0](2)
238 * GPY5[1] EBI_DATA[1](2)
239 * GPY5[2] EBI_DATA[2](2)
240 * GPY5[3] EBI_DATA[3](2)
241 * GPY5[4] EBI_DATA[4](2)
242 * GPY5[5] EBI_DATA[5](2)
243 * GPY5[6] EBI_DATA[6](2)
244 * GPY5[7] EBI_DATA[7](2)
245 *
246 * GPY6[0] EBI_DATA[8](2)
247 * GPY6[1] EBI_DATA[9](2)
248 * GPY6[2] EBI_DATA[10](2)
249 * GPY6[3] EBI_DATA[11](2)
250 * GPY6[4] EBI_DATA[12](2)
251 * GPY6[5] EBI_DATA[13](2)
252 * GPY6[6] EBI_DATA[14](2)
253 * GPY6[7] EBI_DATA[15](2)
254 */
255 for (i = 0; i < 8; i++) {
256 gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
257 gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
258
259 gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
260 gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
261
262 gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
263 gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
264 }
265 }
266
exynos5_i2c_config(int peripheral,int flags)267 static void exynos5_i2c_config(int peripheral, int flags)
268 {
269 int func01, func23;
270
271 /* High-Speed I2C */
272 if (flags & PINMUX_FLAG_HS_MODE) {
273 func01 = 4;
274 func23 = 4;
275 } else {
276 func01 = 2;
277 func23 = 3;
278 }
279
280 switch (peripheral) {
281 case PERIPH_ID_I2C0:
282 gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
283 gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
284 break;
285 case PERIPH_ID_I2C1:
286 gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
287 gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
288 break;
289 case PERIPH_ID_I2C2:
290 gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
291 gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
292 break;
293 case PERIPH_ID_I2C3:
294 gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
295 gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
296 break;
297 case PERIPH_ID_I2C4:
298 gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
299 gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
300 break;
301 case PERIPH_ID_I2C5:
302 gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
303 gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
304 break;
305 case PERIPH_ID_I2C6:
306 gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
307 gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
308 break;
309 case PERIPH_ID_I2C7:
310 gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
311 gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
312 break;
313 }
314 }
315
exynos5420_i2c_config(int peripheral)316 static void exynos5420_i2c_config(int peripheral)
317 {
318 switch (peripheral) {
319 case PERIPH_ID_I2C0:
320 gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
321 gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
322 break;
323 case PERIPH_ID_I2C1:
324 gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
325 gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
326 break;
327 case PERIPH_ID_I2C2:
328 gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
329 gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
330 break;
331 case PERIPH_ID_I2C3:
332 gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
333 gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
334 break;
335 case PERIPH_ID_I2C4:
336 gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
337 gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
338 break;
339 case PERIPH_ID_I2C5:
340 gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
341 gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
342 break;
343 case PERIPH_ID_I2C6:
344 gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
345 gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
346 break;
347 case PERIPH_ID_I2C7:
348 gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
349 gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
350 break;
351 case PERIPH_ID_I2C8:
352 gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
353 gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
354 break;
355 case PERIPH_ID_I2C9:
356 gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
357 gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
358 break;
359 case PERIPH_ID_I2C10:
360 gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
361 gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
362 break;
363 }
364 }
365
exynos5_i2s_config(int peripheral)366 static void exynos5_i2s_config(int peripheral)
367 {
368 int i;
369
370 switch (peripheral) {
371 case PERIPH_ID_I2S0:
372 for (i = 0; i < 5; i++)
373 gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
374 break;
375 case PERIPH_ID_I2S1:
376 for (i = 0; i < 5; i++)
377 gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
378 break;
379 }
380 }
381
exynos5420_i2s_config(int peripheral)382 static void exynos5420_i2s_config(int peripheral)
383 {
384 int i;
385
386 switch (peripheral) {
387 case PERIPH_ID_I2S0:
388 for (i = 0; i < 5; i++)
389 gpio_cfg_pin(EXYNOS5420_GPIO_Z0 + i,
390 S5P_GPIO_FUNC(0x02));
391 break;
392 }
393 }
394
395
exynos5_spi_config(int peripheral)396 void exynos5_spi_config(int peripheral)
397 {
398 int cfg = 0, pin = 0, i;
399
400 switch (peripheral) {
401 case PERIPH_ID_SPI0:
402 cfg = S5P_GPIO_FUNC(0x2);
403 pin = EXYNOS5_GPIO_A20;
404 break;
405 case PERIPH_ID_SPI1:
406 cfg = S5P_GPIO_FUNC(0x2);
407 pin = EXYNOS5_GPIO_A24;
408 break;
409 case PERIPH_ID_SPI2:
410 cfg = S5P_GPIO_FUNC(0x5);
411 pin = EXYNOS5_GPIO_B11;
412 break;
413 case PERIPH_ID_SPI3:
414 cfg = S5P_GPIO_FUNC(0x2);
415 pin = EXYNOS5_GPIO_F10;
416 break;
417 case PERIPH_ID_SPI4:
418 for (i = 0; i < 2; i++) {
419 gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
420 gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
421 }
422 break;
423 }
424 if (peripheral != PERIPH_ID_SPI4) {
425 for (i = pin; i < pin + 4; i++)
426 gpio_cfg_pin(i, cfg);
427 }
428 }
429
exynos5420_spi_config(int peripheral)430 void exynos5420_spi_config(int peripheral)
431 {
432 int cfg, pin, i;
433
434 switch (peripheral) {
435 case PERIPH_ID_SPI0:
436 pin = EXYNOS5420_GPIO_A20;
437 cfg = S5P_GPIO_FUNC(0x2);
438 break;
439 case PERIPH_ID_SPI1:
440 pin = EXYNOS5420_GPIO_A24;
441 cfg = S5P_GPIO_FUNC(0x2);
442 break;
443 case PERIPH_ID_SPI2:
444 pin = EXYNOS5420_GPIO_B11;
445 cfg = S5P_GPIO_FUNC(0x5);
446 break;
447 case PERIPH_ID_SPI3:
448 pin = EXYNOS5420_GPIO_F10;
449 cfg = S5P_GPIO_FUNC(0x2);
450 break;
451 case PERIPH_ID_SPI4:
452 cfg = 0;
453 pin = 0;
454 break;
455 default:
456 cfg = 0;
457 pin = 0;
458 debug("%s: invalid peripheral %d", __func__, peripheral);
459 return;
460 }
461
462 if (peripheral != PERIPH_ID_SPI4) {
463 for (i = pin; i < pin + 4; i++)
464 gpio_cfg_pin(i, cfg);
465 } else {
466 for (i = 0; i < 2; i++) {
467 gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
468 S5P_GPIO_FUNC(0x4));
469 gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
470 S5P_GPIO_FUNC(0x4));
471 }
472 }
473 }
474
exynos5_pinmux_config(int peripheral,int flags)475 static int exynos5_pinmux_config(int peripheral, int flags)
476 {
477 switch (peripheral) {
478 case PERIPH_ID_UART0:
479 case PERIPH_ID_UART1:
480 case PERIPH_ID_UART2:
481 case PERIPH_ID_UART3:
482 exynos5_uart_config(peripheral);
483 break;
484 case PERIPH_ID_SDMMC0:
485 case PERIPH_ID_SDMMC1:
486 case PERIPH_ID_SDMMC2:
487 case PERIPH_ID_SDMMC3:
488 return exynos5_mmc_config(peripheral, flags);
489 case PERIPH_ID_SROMC:
490 exynos5_sromc_config(flags);
491 break;
492 case PERIPH_ID_I2C0:
493 case PERIPH_ID_I2C1:
494 case PERIPH_ID_I2C2:
495 case PERIPH_ID_I2C3:
496 case PERIPH_ID_I2C4:
497 case PERIPH_ID_I2C5:
498 case PERIPH_ID_I2C6:
499 case PERIPH_ID_I2C7:
500 exynos5_i2c_config(peripheral, flags);
501 break;
502 case PERIPH_ID_I2S0:
503 case PERIPH_ID_I2S1:
504 exynos5_i2s_config(peripheral);
505 break;
506 case PERIPH_ID_SPI0:
507 case PERIPH_ID_SPI1:
508 case PERIPH_ID_SPI2:
509 case PERIPH_ID_SPI3:
510 case PERIPH_ID_SPI4:
511 exynos5_spi_config(peripheral);
512 break;
513 case PERIPH_ID_DPHPD:
514 /* Set Hotplug detect for DP */
515 gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
516
517 /*
518 * Hotplug detect should have an external pullup; disable the
519 * internal pulldown so they don't fight.
520 */
521 gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE);
522 break;
523 case PERIPH_ID_PWM0:
524 gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2));
525 break;
526 default:
527 debug("%s: invalid peripheral %d", __func__, peripheral);
528 return -1;
529 }
530
531 return 0;
532 }
533
exynos5420_pinmux_config(int peripheral,int flags)534 static int exynos5420_pinmux_config(int peripheral, int flags)
535 {
536 switch (peripheral) {
537 case PERIPH_ID_UART0:
538 case PERIPH_ID_UART1:
539 case PERIPH_ID_UART2:
540 case PERIPH_ID_UART3:
541 exynos5420_uart_config(peripheral);
542 break;
543 case PERIPH_ID_SDMMC0:
544 case PERIPH_ID_SDMMC1:
545 case PERIPH_ID_SDMMC2:
546 case PERIPH_ID_SDMMC3:
547 return exynos5420_mmc_config(peripheral, flags);
548 case PERIPH_ID_SPI0:
549 case PERIPH_ID_SPI1:
550 case PERIPH_ID_SPI2:
551 case PERIPH_ID_SPI3:
552 case PERIPH_ID_SPI4:
553 exynos5420_spi_config(peripheral);
554 break;
555 case PERIPH_ID_I2C0:
556 case PERIPH_ID_I2C1:
557 case PERIPH_ID_I2C2:
558 case PERIPH_ID_I2C3:
559 case PERIPH_ID_I2C4:
560 case PERIPH_ID_I2C5:
561 case PERIPH_ID_I2C6:
562 case PERIPH_ID_I2C7:
563 case PERIPH_ID_I2C8:
564 case PERIPH_ID_I2C9:
565 case PERIPH_ID_I2C10:
566 exynos5420_i2c_config(peripheral);
567 break;
568 case PERIPH_ID_I2S0:
569 exynos5420_i2s_config(peripheral);
570 break;
571 case PERIPH_ID_PWM0:
572 gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2));
573 break;
574 default:
575 debug("%s: invalid peripheral %d", __func__, peripheral);
576 return -1;
577 }
578
579 return 0;
580 }
581
exynos4_i2c_config(int peripheral,int flags)582 static void exynos4_i2c_config(int peripheral, int flags)
583 {
584 switch (peripheral) {
585 case PERIPH_ID_I2C0:
586 gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
587 gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
588 break;
589 case PERIPH_ID_I2C1:
590 gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
591 gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
592 break;
593 case PERIPH_ID_I2C2:
594 gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
595 gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
596 break;
597 case PERIPH_ID_I2C3:
598 gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
599 gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
600 break;
601 case PERIPH_ID_I2C4:
602 gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
603 gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
604 break;
605 case PERIPH_ID_I2C5:
606 gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
607 gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
608 break;
609 case PERIPH_ID_I2C6:
610 gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
611 gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
612 break;
613 case PERIPH_ID_I2C7:
614 gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
615 gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
616 break;
617 }
618 }
619
exynos4_mmc_config(int peripheral,int flags)620 static int exynos4_mmc_config(int peripheral, int flags)
621 {
622 int i, start = 0, start_ext = 0;
623 unsigned int func, ext_func;
624
625 switch (peripheral) {
626 case PERIPH_ID_SDMMC0:
627 start = EXYNOS4_GPIO_K00;
628 start_ext = EXYNOS4_GPIO_K13;
629 func = S5P_GPIO_FUNC(0x2);
630 ext_func = S5P_GPIO_FUNC(0x3);
631 break;
632 case PERIPH_ID_SDMMC2:
633 start = EXYNOS4_GPIO_K20;
634 start_ext = EXYNOS4_GPIO_K33;
635 func = S5P_GPIO_FUNC(0x2);
636 ext_func = S5P_GPIO_FUNC(0x3);
637 break;
638 case PERIPH_ID_SDMMC4:
639 start = EXYNOS4_GPIO_K00;
640 start_ext = EXYNOS4_GPIO_K13;
641 func = S5P_GPIO_FUNC(0x3);
642 ext_func = S5P_GPIO_FUNC(0x4);
643 break;
644 default:
645 return -1;
646 }
647 for (i = start; i < (start + 7); i++) {
648 if (i == (start + 2))
649 continue;
650 gpio_cfg_pin(i, func);
651 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
652 gpio_set_drv(i, S5P_GPIO_DRV_4X);
653 }
654 /* SDMMC2 do not use 8bit mode at exynos4 */
655 if (flags & PINMUX_FLAG_8BIT_MODE) {
656 for (i = start_ext; i < (start_ext + 4); i++) {
657 gpio_cfg_pin(i, ext_func);
658 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
659 gpio_set_drv(i, S5P_GPIO_DRV_4X);
660 }
661 }
662
663 return 0;
664 }
665
exynos4_uart_config(int peripheral)666 static void exynos4_uart_config(int peripheral)
667 {
668 int i, start, count;
669
670 switch (peripheral) {
671 case PERIPH_ID_UART0:
672 start = EXYNOS4_GPIO_A00;
673 count = 4;
674 break;
675 case PERIPH_ID_UART1:
676 start = EXYNOS4_GPIO_A04;
677 count = 4;
678 break;
679 case PERIPH_ID_UART2:
680 start = EXYNOS4_GPIO_A10;
681 count = 4;
682 break;
683 case PERIPH_ID_UART3:
684 start = EXYNOS4_GPIO_A14;
685 count = 2;
686 break;
687 default:
688 debug("%s: invalid peripheral %d", __func__, peripheral);
689 return;
690 }
691 for (i = start; i < (start + count); i++) {
692 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
693 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
694 }
695 }
696
exynos4x12_i2c_config(int peripheral,int flags)697 static void exynos4x12_i2c_config(int peripheral, int flags)
698 {
699 switch (peripheral) {
700 case PERIPH_ID_I2C0:
701 gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
702 gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
703 break;
704 case PERIPH_ID_I2C1:
705 gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
706 gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
707 break;
708 case PERIPH_ID_I2C2:
709 gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
710 gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
711 break;
712 case PERIPH_ID_I2C3:
713 gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
714 gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
715 break;
716 case PERIPH_ID_I2C4:
717 gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
718 gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
719 break;
720 case PERIPH_ID_I2C5:
721 gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
722 gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
723 break;
724 case PERIPH_ID_I2C6:
725 gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
726 gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
727 break;
728 case PERIPH_ID_I2C7:
729 gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
730 gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
731 break;
732 }
733 }
734
exynos4x12_mmc_config(int peripheral,int flags)735 static int exynos4x12_mmc_config(int peripheral, int flags)
736 {
737 int i, start = 0, start_ext = 0;
738 unsigned int func, ext_func;
739
740 switch (peripheral) {
741 case PERIPH_ID_SDMMC0:
742 start = EXYNOS4X12_GPIO_K00;
743 start_ext = EXYNOS4X12_GPIO_K13;
744 func = S5P_GPIO_FUNC(0x2);
745 ext_func = S5P_GPIO_FUNC(0x3);
746 break;
747 case PERIPH_ID_SDMMC2:
748 start = EXYNOS4X12_GPIO_K20;
749 start_ext = EXYNOS4X12_GPIO_K33;
750 func = S5P_GPIO_FUNC(0x2);
751 ext_func = S5P_GPIO_FUNC(0x3);
752 break;
753 case PERIPH_ID_SDMMC4:
754 start = EXYNOS4X12_GPIO_K00;
755 start_ext = EXYNOS4X12_GPIO_K13;
756 func = S5P_GPIO_FUNC(0x3);
757 ext_func = S5P_GPIO_FUNC(0x4);
758 break;
759 default:
760 return -1;
761 }
762 for (i = start; i < (start + 7); i++) {
763 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
764 if (i == (start + 2))
765 continue;
766 gpio_cfg_pin(i, func);
767 gpio_set_drv(i, S5P_GPIO_DRV_4X);
768 }
769 if (flags & PINMUX_FLAG_8BIT_MODE) {
770 for (i = start_ext; i < (start_ext + 4); i++) {
771 gpio_cfg_pin(i, ext_func);
772 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
773 gpio_set_drv(i, S5P_GPIO_DRV_4X);
774 }
775 }
776
777 return 0;
778 }
779
exynos4x12_uart_config(int peripheral)780 static void exynos4x12_uart_config(int peripheral)
781 {
782 int i, start, count;
783
784 switch (peripheral) {
785 case PERIPH_ID_UART0:
786 start = EXYNOS4X12_GPIO_A00;
787 count = 4;
788 break;
789 case PERIPH_ID_UART1:
790 start = EXYNOS4X12_GPIO_A04;
791 count = 4;
792 break;
793 case PERIPH_ID_UART2:
794 start = EXYNOS4X12_GPIO_A10;
795 count = 4;
796 break;
797 case PERIPH_ID_UART3:
798 start = EXYNOS4X12_GPIO_A14;
799 count = 2;
800 break;
801 default:
802 debug("%s: invalid peripheral %d", __func__, peripheral);
803 return;
804 }
805 for (i = start; i < (start + count); i++) {
806 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
807 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
808 }
809 }
810
exynos4_pinmux_config(int peripheral,int flags)811 static int exynos4_pinmux_config(int peripheral, int flags)
812 {
813 switch (peripheral) {
814 case PERIPH_ID_UART0:
815 case PERIPH_ID_UART1:
816 case PERIPH_ID_UART2:
817 case PERIPH_ID_UART3:
818 exynos4_uart_config(peripheral);
819 break;
820 case PERIPH_ID_I2C0:
821 case PERIPH_ID_I2C1:
822 case PERIPH_ID_I2C2:
823 case PERIPH_ID_I2C3:
824 case PERIPH_ID_I2C4:
825 case PERIPH_ID_I2C5:
826 case PERIPH_ID_I2C6:
827 case PERIPH_ID_I2C7:
828 exynos4_i2c_config(peripheral, flags);
829 break;
830 case PERIPH_ID_SDMMC0:
831 case PERIPH_ID_SDMMC2:
832 case PERIPH_ID_SDMMC4:
833 return exynos4_mmc_config(peripheral, flags);
834 case PERIPH_ID_SDMMC1:
835 case PERIPH_ID_SDMMC3:
836 debug("SDMMC device %d not implemented\n", peripheral);
837 return -1;
838 default:
839 debug("%s: invalid peripheral %d", __func__, peripheral);
840 return -1;
841 }
842
843 return 0;
844 }
845
exynos4x12_pinmux_config(int peripheral,int flags)846 static int exynos4x12_pinmux_config(int peripheral, int flags)
847 {
848 switch (peripheral) {
849 case PERIPH_ID_UART0:
850 case PERIPH_ID_UART1:
851 case PERIPH_ID_UART2:
852 case PERIPH_ID_UART3:
853 exynos4x12_uart_config(peripheral);
854 break;
855 case PERIPH_ID_I2C0:
856 case PERIPH_ID_I2C1:
857 case PERIPH_ID_I2C2:
858 case PERIPH_ID_I2C3:
859 case PERIPH_ID_I2C4:
860 case PERIPH_ID_I2C5:
861 case PERIPH_ID_I2C6:
862 case PERIPH_ID_I2C7:
863 exynos4x12_i2c_config(peripheral, flags);
864 break;
865 case PERIPH_ID_SDMMC0:
866 case PERIPH_ID_SDMMC2:
867 case PERIPH_ID_SDMMC4:
868 return exynos4x12_mmc_config(peripheral, flags);
869 case PERIPH_ID_SDMMC1:
870 case PERIPH_ID_SDMMC3:
871 debug("SDMMC device %d not implemented\n", peripheral);
872 return -1;
873 default:
874 debug("%s: invalid peripheral %d", __func__, peripheral);
875 return -1;
876 }
877
878 return 0;
879 }
880
exynos_pinmux_config(int peripheral,int flags)881 int exynos_pinmux_config(int peripheral, int flags)
882 {
883 if (cpu_is_exynos5()) {
884 if (proid_is_exynos542x())
885 return exynos5420_pinmux_config(peripheral, flags);
886 else if (proid_is_exynos5250())
887 return exynos5_pinmux_config(peripheral, flags);
888 } else if (cpu_is_exynos4()) {
889 if (proid_is_exynos4412())
890 return exynos4x12_pinmux_config(peripheral, flags);
891 else
892 return exynos4_pinmux_config(peripheral, flags);
893 }
894
895 debug("pinmux functionality not supported\n");
896
897 return -1;
898 }
899
900 #if CONFIG_IS_ENABLED(OF_CONTROL)
exynos4_pinmux_decode_periph_id(const void * blob,int node)901 static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
902 {
903 int err;
904 u32 cell[3];
905
906 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
907 ARRAY_SIZE(cell));
908 if (err) {
909 debug(" invalid peripheral id\n");
910 return PERIPH_ID_NONE;
911 }
912
913 return cell[1];
914 }
915
exynos5_pinmux_decode_periph_id(const void * blob,int node)916 static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
917 {
918 int err;
919 u32 cell[3];
920
921 err = fdtdec_get_int_array(blob, node, "interrupts", cell,
922 ARRAY_SIZE(cell));
923 if (err)
924 return PERIPH_ID_NONE;
925
926 return cell[1];
927 }
928
pinmux_decode_periph_id(const void * blob,int node)929 int pinmux_decode_periph_id(const void *blob, int node)
930 {
931 if (cpu_is_exynos5())
932 return exynos5_pinmux_decode_periph_id(blob, node);
933 else if (cpu_is_exynos4())
934 return exynos4_pinmux_decode_periph_id(blob, node);
935
936 return PERIPH_ID_NONE;
937 }
938 #endif
939