1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <init.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <pci.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <dm/device-internal.h>
17 #include <dm/lists.h>
18 #include <dm/uclass-internal.h>
19 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
20 #include <asm/fsp/fsp_support.h>
21 #endif
22 #include <linux/delay.h>
23 #include "pci_internal.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
pci_get_bus(int busnum,struct udevice ** busp)27 int pci_get_bus(int busnum, struct udevice **busp)
28 {
29 int ret;
30
31 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
32
33 /* Since buses may not be numbered yet try a little harder with bus 0 */
34 if (ret == -ENODEV) {
35 ret = uclass_first_device_err(UCLASS_PCI, busp);
36 if (ret)
37 return ret;
38 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
39 }
40
41 return ret;
42 }
43
pci_get_controller(struct udevice * dev)44 struct udevice *pci_get_controller(struct udevice *dev)
45 {
46 while (device_is_on_pci_bus(dev))
47 dev = dev->parent;
48
49 return dev;
50 }
51
dm_pci_get_bdf(const struct udevice * dev)52 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
53 {
54 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
55 struct udevice *bus = dev->parent;
56
57 /*
58 * This error indicates that @dev is a device on an unprobed PCI bus.
59 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
60 * will produce a bad BDF>
61 *
62 * A common cause of this problem is that this function is called in the
63 * of_to_plat() method of @dev. Accessing the PCI bus in that
64 * method is not allowed, since it has not yet been probed. To fix this,
65 * move that access to the probe() method of @dev instead.
66 */
67 if (!device_active(bus))
68 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
69 bus->name);
70 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
71 }
72
73 /**
74 * pci_get_bus_max() - returns the bus number of the last active bus
75 *
76 * @return last bus number, or -1 if no active buses
77 */
pci_get_bus_max(void)78 static int pci_get_bus_max(void)
79 {
80 struct udevice *bus;
81 struct uclass *uc;
82 int ret = -1;
83
84 ret = uclass_get(UCLASS_PCI, &uc);
85 uclass_foreach_dev(bus, uc) {
86 if (dev_seq(bus) > ret)
87 ret = dev_seq(bus);
88 }
89
90 debug("%s: ret=%d\n", __func__, ret);
91
92 return ret;
93 }
94
pci_last_busno(void)95 int pci_last_busno(void)
96 {
97 return pci_get_bus_max();
98 }
99
pci_get_ff(enum pci_size_t size)100 int pci_get_ff(enum pci_size_t size)
101 {
102 switch (size) {
103 case PCI_SIZE_8:
104 return 0xff;
105 case PCI_SIZE_16:
106 return 0xffff;
107 default:
108 return 0xffffffff;
109 }
110 }
111
pci_dev_find_ofnode(struct udevice * bus,phys_addr_t bdf,ofnode * rnode)112 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
113 ofnode *rnode)
114 {
115 struct fdt_pci_addr addr;
116 ofnode node;
117 int ret;
118
119 dev_for_each_subnode(node, bus) {
120 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
121 &addr);
122 if (ret)
123 continue;
124
125 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
126 continue;
127
128 *rnode = node;
129 break;
130 }
131 };
132
pci_bus_find_devfn(const struct udevice * bus,pci_dev_t find_devfn,struct udevice ** devp)133 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
134 struct udevice **devp)
135 {
136 struct udevice *dev;
137
138 for (device_find_first_child(bus, &dev);
139 dev;
140 device_find_next_child(&dev)) {
141 struct pci_child_plat *pplat;
142
143 pplat = dev_get_parent_plat(dev);
144 if (pplat && pplat->devfn == find_devfn) {
145 *devp = dev;
146 return 0;
147 }
148 }
149
150 return -ENODEV;
151 }
152
dm_pci_bus_find_bdf(pci_dev_t bdf,struct udevice ** devp)153 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
154 {
155 struct udevice *bus;
156 int ret;
157
158 ret = pci_get_bus(PCI_BUS(bdf), &bus);
159 if (ret)
160 return ret;
161 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
162 }
163
pci_device_matches_ids(struct udevice * dev,struct pci_device_id * ids)164 static int pci_device_matches_ids(struct udevice *dev,
165 struct pci_device_id *ids)
166 {
167 struct pci_child_plat *pplat;
168 int i;
169
170 pplat = dev_get_parent_plat(dev);
171 if (!pplat)
172 return -EINVAL;
173 for (i = 0; ids[i].vendor != 0; i++) {
174 if (pplat->vendor == ids[i].vendor &&
175 pplat->device == ids[i].device)
176 return i;
177 }
178
179 return -EINVAL;
180 }
181
pci_bus_find_devices(struct udevice * bus,struct pci_device_id * ids,int * indexp,struct udevice ** devp)182 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
183 int *indexp, struct udevice **devp)
184 {
185 struct udevice *dev;
186
187 /* Scan all devices on this bus */
188 for (device_find_first_child(bus, &dev);
189 dev;
190 device_find_next_child(&dev)) {
191 if (pci_device_matches_ids(dev, ids) >= 0) {
192 if ((*indexp)-- <= 0) {
193 *devp = dev;
194 return 0;
195 }
196 }
197 }
198
199 return -ENODEV;
200 }
201
pci_find_device_id(struct pci_device_id * ids,int index,struct udevice ** devp)202 int pci_find_device_id(struct pci_device_id *ids, int index,
203 struct udevice **devp)
204 {
205 struct udevice *bus;
206
207 /* Scan all known buses */
208 for (uclass_first_device(UCLASS_PCI, &bus);
209 bus;
210 uclass_next_device(&bus)) {
211 if (!pci_bus_find_devices(bus, ids, &index, devp))
212 return 0;
213 }
214 *devp = NULL;
215
216 return -ENODEV;
217 }
218
dm_pci_bus_find_device(struct udevice * bus,unsigned int vendor,unsigned int device,int * indexp,struct udevice ** devp)219 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
220 unsigned int device, int *indexp,
221 struct udevice **devp)
222 {
223 struct pci_child_plat *pplat;
224 struct udevice *dev;
225
226 for (device_find_first_child(bus, &dev);
227 dev;
228 device_find_next_child(&dev)) {
229 pplat = dev_get_parent_plat(dev);
230 if (pplat->vendor == vendor && pplat->device == device) {
231 if (!(*indexp)--) {
232 *devp = dev;
233 return 0;
234 }
235 }
236 }
237
238 return -ENODEV;
239 }
240
dm_pci_find_device(unsigned int vendor,unsigned int device,int index,struct udevice ** devp)241 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
242 struct udevice **devp)
243 {
244 struct udevice *bus;
245
246 /* Scan all known buses */
247 for (uclass_first_device(UCLASS_PCI, &bus);
248 bus;
249 uclass_next_device(&bus)) {
250 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
251 return device_probe(*devp);
252 }
253 *devp = NULL;
254
255 return -ENODEV;
256 }
257
dm_pci_find_class(uint find_class,int index,struct udevice ** devp)258 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
259 {
260 struct udevice *dev;
261
262 /* Scan all known buses */
263 for (pci_find_first_device(&dev);
264 dev;
265 pci_find_next_device(&dev)) {
266 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
267
268 if (pplat->class == find_class && !index--) {
269 *devp = dev;
270 return device_probe(*devp);
271 }
272 }
273 *devp = NULL;
274
275 return -ENODEV;
276 }
277
pci_bus_write_config(struct udevice * bus,pci_dev_t bdf,int offset,unsigned long value,enum pci_size_t size)278 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
279 unsigned long value, enum pci_size_t size)
280 {
281 struct dm_pci_ops *ops;
282
283 ops = pci_get_ops(bus);
284 if (!ops->write_config)
285 return -ENOSYS;
286 return ops->write_config(bus, bdf, offset, value, size);
287 }
288
pci_bus_clrset_config32(struct udevice * bus,pci_dev_t bdf,int offset,u32 clr,u32 set)289 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
290 u32 clr, u32 set)
291 {
292 ulong val;
293 int ret;
294
295 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
296 if (ret)
297 return ret;
298 val &= ~clr;
299 val |= set;
300
301 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
302 }
303
pci_write_config(pci_dev_t bdf,int offset,unsigned long value,enum pci_size_t size)304 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
305 enum pci_size_t size)
306 {
307 struct udevice *bus;
308 int ret;
309
310 ret = pci_get_bus(PCI_BUS(bdf), &bus);
311 if (ret)
312 return ret;
313
314 return pci_bus_write_config(bus, bdf, offset, value, size);
315 }
316
dm_pci_write_config(struct udevice * dev,int offset,unsigned long value,enum pci_size_t size)317 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
318 enum pci_size_t size)
319 {
320 struct udevice *bus;
321
322 for (bus = dev; device_is_on_pci_bus(bus);)
323 bus = bus->parent;
324 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
325 size);
326 }
327
pci_write_config32(pci_dev_t bdf,int offset,u32 value)328 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
329 {
330 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
331 }
332
pci_write_config16(pci_dev_t bdf,int offset,u16 value)333 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
334 {
335 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
336 }
337
pci_write_config8(pci_dev_t bdf,int offset,u8 value)338 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
339 {
340 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
341 }
342
dm_pci_write_config8(struct udevice * dev,int offset,u8 value)343 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
344 {
345 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
346 }
347
dm_pci_write_config16(struct udevice * dev,int offset,u16 value)348 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
349 {
350 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
351 }
352
dm_pci_write_config32(struct udevice * dev,int offset,u32 value)353 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
354 {
355 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
356 }
357
pci_bus_read_config(const struct udevice * bus,pci_dev_t bdf,int offset,unsigned long * valuep,enum pci_size_t size)358 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
359 unsigned long *valuep, enum pci_size_t size)
360 {
361 struct dm_pci_ops *ops;
362
363 ops = pci_get_ops(bus);
364 if (!ops->read_config)
365 return -ENOSYS;
366 return ops->read_config(bus, bdf, offset, valuep, size);
367 }
368
pci_read_config(pci_dev_t bdf,int offset,unsigned long * valuep,enum pci_size_t size)369 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
370 enum pci_size_t size)
371 {
372 struct udevice *bus;
373 int ret;
374
375 ret = pci_get_bus(PCI_BUS(bdf), &bus);
376 if (ret)
377 return ret;
378
379 return pci_bus_read_config(bus, bdf, offset, valuep, size);
380 }
381
dm_pci_read_config(const struct udevice * dev,int offset,unsigned long * valuep,enum pci_size_t size)382 int dm_pci_read_config(const struct udevice *dev, int offset,
383 unsigned long *valuep, enum pci_size_t size)
384 {
385 const struct udevice *bus;
386
387 for (bus = dev; device_is_on_pci_bus(bus);)
388 bus = bus->parent;
389 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
390 size);
391 }
392
pci_read_config32(pci_dev_t bdf,int offset,u32 * valuep)393 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
394 {
395 unsigned long value;
396 int ret;
397
398 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
399 if (ret)
400 return ret;
401 *valuep = value;
402
403 return 0;
404 }
405
pci_read_config16(pci_dev_t bdf,int offset,u16 * valuep)406 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
407 {
408 unsigned long value;
409 int ret;
410
411 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
412 if (ret)
413 return ret;
414 *valuep = value;
415
416 return 0;
417 }
418
pci_read_config8(pci_dev_t bdf,int offset,u8 * valuep)419 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
420 {
421 unsigned long value;
422 int ret;
423
424 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
425 if (ret)
426 return ret;
427 *valuep = value;
428
429 return 0;
430 }
431
dm_pci_read_config8(const struct udevice * dev,int offset,u8 * valuep)432 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
433 {
434 unsigned long value;
435 int ret;
436
437 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
438 if (ret)
439 return ret;
440 *valuep = value;
441
442 return 0;
443 }
444
dm_pci_read_config16(const struct udevice * dev,int offset,u16 * valuep)445 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
446 {
447 unsigned long value;
448 int ret;
449
450 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
451 if (ret)
452 return ret;
453 *valuep = value;
454
455 return 0;
456 }
457
dm_pci_read_config32(const struct udevice * dev,int offset,u32 * valuep)458 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
459 {
460 unsigned long value;
461 int ret;
462
463 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
464 if (ret)
465 return ret;
466 *valuep = value;
467
468 return 0;
469 }
470
dm_pci_clrset_config8(struct udevice * dev,int offset,u32 clr,u32 set)471 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
472 {
473 u8 val;
474 int ret;
475
476 ret = dm_pci_read_config8(dev, offset, &val);
477 if (ret)
478 return ret;
479 val &= ~clr;
480 val |= set;
481
482 return dm_pci_write_config8(dev, offset, val);
483 }
484
dm_pci_clrset_config16(struct udevice * dev,int offset,u32 clr,u32 set)485 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
486 {
487 u16 val;
488 int ret;
489
490 ret = dm_pci_read_config16(dev, offset, &val);
491 if (ret)
492 return ret;
493 val &= ~clr;
494 val |= set;
495
496 return dm_pci_write_config16(dev, offset, val);
497 }
498
dm_pci_clrset_config32(struct udevice * dev,int offset,u32 clr,u32 set)499 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
500 {
501 u32 val;
502 int ret;
503
504 ret = dm_pci_read_config32(dev, offset, &val);
505 if (ret)
506 return ret;
507 val &= ~clr;
508 val |= set;
509
510 return dm_pci_write_config32(dev, offset, val);
511 }
512
set_vga_bridge_bits(struct udevice * dev)513 static void set_vga_bridge_bits(struct udevice *dev)
514 {
515 struct udevice *parent = dev->parent;
516 u16 bc;
517
518 while (dev_seq(parent) != 0) {
519 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
520 bc |= PCI_BRIDGE_CTL_VGA;
521 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
522 parent = parent->parent;
523 }
524 }
525
pci_auto_config_devices(struct udevice * bus)526 int pci_auto_config_devices(struct udevice *bus)
527 {
528 struct pci_controller *hose = dev_get_uclass_priv(bus);
529 struct pci_child_plat *pplat;
530 unsigned int sub_bus;
531 struct udevice *dev;
532 int ret;
533
534 sub_bus = dev_seq(bus);
535 debug("%s: start\n", __func__);
536 pciauto_config_init(hose);
537 for (ret = device_find_first_child(bus, &dev);
538 !ret && dev;
539 ret = device_find_next_child(&dev)) {
540 unsigned int max_bus;
541 int ret;
542
543 debug("%s: device %s\n", __func__, dev->name);
544 if (dev_has_ofnode(dev) &&
545 dev_read_bool(dev, "pci,no-autoconfig"))
546 continue;
547 ret = dm_pciauto_config_device(dev);
548 if (ret < 0)
549 return log_msg_ret("auto", ret);
550 max_bus = ret;
551 sub_bus = max(sub_bus, max_bus);
552
553 pplat = dev_get_parent_plat(dev);
554 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
555 set_vga_bridge_bits(dev);
556 }
557 debug("%s: done\n", __func__);
558
559 return log_msg_ret("sub", sub_bus);
560 }
561
pci_generic_mmap_write_config(const struct udevice * bus,int (* addr_f)(const struct udevice * bus,pci_dev_t bdf,uint offset,void ** addrp),pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)562 int pci_generic_mmap_write_config(
563 const struct udevice *bus,
564 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
565 void **addrp),
566 pci_dev_t bdf,
567 uint offset,
568 ulong value,
569 enum pci_size_t size)
570 {
571 void *address;
572
573 if (addr_f(bus, bdf, offset, &address) < 0)
574 return 0;
575
576 switch (size) {
577 case PCI_SIZE_8:
578 writeb(value, address);
579 return 0;
580 case PCI_SIZE_16:
581 writew(value, address);
582 return 0;
583 case PCI_SIZE_32:
584 writel(value, address);
585 return 0;
586 default:
587 return -EINVAL;
588 }
589 }
590
pci_generic_mmap_read_config(const struct udevice * bus,int (* addr_f)(const struct udevice * bus,pci_dev_t bdf,uint offset,void ** addrp),pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)591 int pci_generic_mmap_read_config(
592 const struct udevice *bus,
593 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
594 void **addrp),
595 pci_dev_t bdf,
596 uint offset,
597 ulong *valuep,
598 enum pci_size_t size)
599 {
600 void *address;
601
602 if (addr_f(bus, bdf, offset, &address) < 0) {
603 *valuep = pci_get_ff(size);
604 return 0;
605 }
606
607 switch (size) {
608 case PCI_SIZE_8:
609 *valuep = readb(address);
610 return 0;
611 case PCI_SIZE_16:
612 *valuep = readw(address);
613 return 0;
614 case PCI_SIZE_32:
615 *valuep = readl(address);
616 return 0;
617 default:
618 return -EINVAL;
619 }
620 }
621
dm_pci_hose_probe_bus(struct udevice * bus)622 int dm_pci_hose_probe_bus(struct udevice *bus)
623 {
624 int sub_bus;
625 int ret;
626 int ea_pos;
627 u8 reg;
628
629 debug("%s\n", __func__);
630
631 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
632 if (ea_pos) {
633 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
634 ®);
635 sub_bus = reg;
636 } else {
637 sub_bus = pci_get_bus_max() + 1;
638 }
639 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
640 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
641
642 ret = device_probe(bus);
643 if (ret) {
644 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
645 ret);
646 return log_msg_ret("probe", ret);
647 }
648
649 if (!ea_pos)
650 sub_bus = pci_get_bus_max();
651
652 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
653
654 return sub_bus;
655 }
656
657 /**
658 * pci_match_one_device - Tell if a PCI device structure has a matching
659 * PCI device id structure
660 * @id: single PCI device id structure to match
661 * @find: the PCI device id structure to match against
662 *
663 * Returns true if the finding pci_device_id structure matched or false if
664 * there is no match.
665 */
pci_match_one_id(const struct pci_device_id * id,const struct pci_device_id * find)666 static bool pci_match_one_id(const struct pci_device_id *id,
667 const struct pci_device_id *find)
668 {
669 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
670 (id->device == PCI_ANY_ID || id->device == find->device) &&
671 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
672 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
673 !((id->class ^ find->class) & id->class_mask))
674 return true;
675
676 return false;
677 }
678
679 /**
680 * pci_find_and_bind_driver() - Find and bind the right PCI driver
681 *
682 * This only looks at certain fields in the descriptor.
683 *
684 * @parent: Parent bus
685 * @find_id: Specification of the driver to find
686 * @bdf: Bus/device/function addreess - see PCI_BDF()
687 * @devp: Returns a pointer to the device created
688 * @return 0 if OK, -EPERM if the device is not needed before relocation and
689 * therefore was not created, other -ve value on error
690 */
pci_find_and_bind_driver(struct udevice * parent,struct pci_device_id * find_id,pci_dev_t bdf,struct udevice ** devp)691 static int pci_find_and_bind_driver(struct udevice *parent,
692 struct pci_device_id *find_id,
693 pci_dev_t bdf, struct udevice **devp)
694 {
695 struct pci_driver_entry *start, *entry;
696 ofnode node = ofnode_null();
697 const char *drv;
698 int n_ents;
699 int ret;
700 char name[30], *str;
701 bool bridge;
702
703 *devp = NULL;
704
705 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
706 find_id->vendor, find_id->device);
707
708 /* Determine optional OF node */
709 if (ofnode_valid(dev_ofnode(parent)))
710 pci_dev_find_ofnode(parent, bdf, &node);
711
712 if (ofnode_valid(node) && !ofnode_is_available(node)) {
713 debug("%s: Ignoring disabled device\n", __func__);
714 return log_msg_ret("dis", -EPERM);
715 }
716
717 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
718 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
719 for (entry = start; entry != start + n_ents; entry++) {
720 const struct pci_device_id *id;
721 struct udevice *dev;
722 const struct driver *drv;
723
724 for (id = entry->match;
725 id->vendor || id->subvendor || id->class_mask;
726 id++) {
727 if (!pci_match_one_id(id, find_id))
728 continue;
729
730 drv = entry->driver;
731
732 /*
733 * In the pre-relocation phase, we only bind devices
734 * whose driver has the DM_FLAG_PRE_RELOC set, to save
735 * precious memory space as on some platforms as that
736 * space is pretty limited (ie: using Cache As RAM).
737 */
738 if (!(gd->flags & GD_FLG_RELOC) &&
739 !(drv->flags & DM_FLAG_PRE_RELOC))
740 return log_msg_ret("pre", -EPERM);
741
742 /*
743 * We could pass the descriptor to the driver as
744 * plat (instead of NULL) and allow its bind()
745 * method to return -ENOENT if it doesn't support this
746 * device. That way we could continue the search to
747 * find another driver. For now this doesn't seem
748 * necesssary, so just bind the first match.
749 */
750 ret = device_bind(parent, drv, drv->name, NULL, node,
751 &dev);
752 if (ret)
753 goto error;
754 debug("%s: Match found: %s\n", __func__, drv->name);
755 dev->driver_data = id->driver_data;
756 *devp = dev;
757 return 0;
758 }
759 }
760
761 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
762 /*
763 * In the pre-relocation phase, we only bind bridge devices to save
764 * precious memory space as on some platforms as that space is pretty
765 * limited (ie: using Cache As RAM).
766 */
767 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
768 return log_msg_ret("notbr", -EPERM);
769
770 /* Bind a generic driver so that the device can be used */
771 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
772 PCI_FUNC(bdf));
773 str = strdup(name);
774 if (!str)
775 return -ENOMEM;
776 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
777
778 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
779 if (ret) {
780 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
781 free(str);
782 return ret;
783 }
784 debug("%s: No match found: bound generic driver instead\n", __func__);
785
786 return 0;
787
788 error:
789 debug("%s: No match found: error %d\n", __func__, ret);
790 return ret;
791 }
792
board_pci_fixup_dev(struct udevice * bus,struct udevice * dev)793 __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
794 {
795 }
796
pci_bind_bus_devices(struct udevice * bus)797 int pci_bind_bus_devices(struct udevice *bus)
798 {
799 ulong vendor, device;
800 ulong header_type;
801 pci_dev_t bdf, end;
802 bool found_multi;
803 int ari_off;
804 int ret;
805
806 found_multi = false;
807 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
808 PCI_MAX_PCI_FUNCTIONS - 1);
809 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
810 bdf += PCI_BDF(0, 0, 1)) {
811 struct pci_child_plat *pplat;
812 struct udevice *dev;
813 ulong class;
814
815 if (!PCI_FUNC(bdf))
816 found_multi = false;
817 if (PCI_FUNC(bdf) && !found_multi)
818 continue;
819
820 /* Check only the first access, we don't expect problems */
821 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
822 PCI_SIZE_16);
823 if (ret)
824 goto error;
825
826 if (vendor == 0xffff || vendor == 0x0000)
827 continue;
828
829 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
830 &header_type, PCI_SIZE_8);
831
832 if (!PCI_FUNC(bdf))
833 found_multi = header_type & 0x80;
834
835 debug("%s: bus %d/%s: found device %x, function %d", __func__,
836 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
837 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
838 PCI_SIZE_16);
839 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
840 PCI_SIZE_32);
841 class >>= 8;
842
843 /* Find this device in the device tree */
844 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
845 debug(": find ret=%d\n", ret);
846
847 /* If nothing in the device tree, bind a device */
848 if (ret == -ENODEV) {
849 struct pci_device_id find_id;
850 ulong val;
851
852 memset(&find_id, '\0', sizeof(find_id));
853 find_id.vendor = vendor;
854 find_id.device = device;
855 find_id.class = class;
856 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
857 pci_bus_read_config(bus, bdf,
858 PCI_SUBSYSTEM_VENDOR_ID,
859 &val, PCI_SIZE_32);
860 find_id.subvendor = val & 0xffff;
861 find_id.subdevice = val >> 16;
862 }
863 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
864 &dev);
865 }
866 if (ret == -EPERM)
867 continue;
868 else if (ret)
869 return ret;
870
871 /* Update the platform data */
872 pplat = dev_get_parent_plat(dev);
873 pplat->devfn = PCI_MASK_BUS(bdf);
874 pplat->vendor = vendor;
875 pplat->device = device;
876 pplat->class = class;
877
878 if (IS_ENABLED(CONFIG_PCI_ARID)) {
879 ari_off = dm_pci_find_ext_capability(dev,
880 PCI_EXT_CAP_ID_ARI);
881 if (ari_off) {
882 u16 ari_cap;
883
884 /*
885 * Read Next Function number in ARI Cap
886 * Register
887 */
888 dm_pci_read_config16(dev, ari_off + 4,
889 &ari_cap);
890 /*
891 * Update next scan on this function number,
892 * subtract 1 in BDF to satisfy loop increment.
893 */
894 if (ari_cap & 0xff00) {
895 bdf = PCI_BDF(PCI_BUS(bdf),
896 PCI_DEV(ari_cap),
897 PCI_FUNC(ari_cap));
898 bdf = bdf - 0x100;
899 }
900 }
901 }
902
903 board_pci_fixup_dev(bus, dev);
904 }
905
906 return 0;
907 error:
908 printf("Cannot read bus configuration: %d\n", ret);
909
910 return ret;
911 }
912
decode_regions(struct pci_controller * hose,ofnode parent_node,ofnode node)913 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
914 ofnode node)
915 {
916 int pci_addr_cells, addr_cells, size_cells;
917 int cells_per_record;
918 struct bd_info *bd;
919 const u32 *prop;
920 int max_regions;
921 int len;
922 int i;
923
924 prop = ofnode_get_property(node, "ranges", &len);
925 if (!prop) {
926 debug("%s: Cannot decode regions\n", __func__);
927 return;
928 }
929
930 pci_addr_cells = ofnode_read_simple_addr_cells(node);
931 addr_cells = ofnode_read_simple_addr_cells(parent_node);
932 size_cells = ofnode_read_simple_size_cells(node);
933
934 /* PCI addresses are always 3-cells */
935 len /= sizeof(u32);
936 cells_per_record = pci_addr_cells + addr_cells + size_cells;
937 hose->region_count = 0;
938 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
939 cells_per_record);
940
941 /* Dynamically allocate the regions array */
942 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
943 hose->regions = (struct pci_region *)
944 calloc(1, max_regions * sizeof(struct pci_region));
945
946 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
947 u64 pci_addr, addr, size;
948 int space_code;
949 u32 flags;
950 int type;
951 int pos;
952
953 if (len < cells_per_record)
954 break;
955 flags = fdt32_to_cpu(prop[0]);
956 space_code = (flags >> 24) & 3;
957 pci_addr = fdtdec_get_number(prop + 1, 2);
958 prop += pci_addr_cells;
959 addr = fdtdec_get_number(prop, addr_cells);
960 prop += addr_cells;
961 size = fdtdec_get_number(prop, size_cells);
962 prop += size_cells;
963 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
964 __func__, hose->region_count, pci_addr, addr, size, space_code);
965 if (space_code & 2) {
966 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
967 PCI_REGION_MEM;
968 } else if (space_code & 1) {
969 type = PCI_REGION_IO;
970 } else {
971 continue;
972 }
973
974 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
975 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
976 debug(" - beyond the 32-bit boundary, ignoring\n");
977 continue;
978 }
979
980 pos = -1;
981 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
982 for (i = 0; i < hose->region_count; i++) {
983 if (hose->regions[i].flags == type)
984 pos = i;
985 }
986 }
987
988 if (pos == -1)
989 pos = hose->region_count++;
990 debug(" - type=%d, pos=%d\n", type, pos);
991 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
992 }
993
994 /* Add a region for our local memory */
995 bd = gd->bd;
996 if (!bd)
997 return;
998
999 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
1000 if (bd->bi_dram[i].size) {
1001 pci_set_region(hose->regions + hose->region_count++,
1002 bd->bi_dram[i].start,
1003 bd->bi_dram[i].start,
1004 bd->bi_dram[i].size,
1005 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1006 }
1007 }
1008
1009 return;
1010 }
1011
pci_uclass_pre_probe(struct udevice * bus)1012 static int pci_uclass_pre_probe(struct udevice *bus)
1013 {
1014 struct pci_controller *hose;
1015 struct uclass *uc;
1016 int ret;
1017
1018 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
1019 bus->parent->name);
1020 hose = dev_get_uclass_priv(bus);
1021
1022 /*
1023 * Set the sequence number, if device_bind() doesn't. We want control
1024 * of this so that numbers are allocated as devices are probed. That
1025 * ensures that sub-bus numbered is correct (sub-buses must get numbers
1026 * higher than their parents)
1027 */
1028 if (dev_seq(bus) == -1) {
1029 ret = uclass_get(UCLASS_PCI, &uc);
1030 if (ret)
1031 return ret;
1032 bus->seq_ = uclass_find_next_free_seq(uc);
1033 }
1034
1035 /* For bridges, use the top-level PCI controller */
1036 if (!device_is_on_pci_bus(bus)) {
1037 hose->ctlr = bus;
1038 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
1039 } else {
1040 struct pci_controller *parent_hose;
1041
1042 parent_hose = dev_get_uclass_priv(bus->parent);
1043 hose->ctlr = parent_hose->bus;
1044 }
1045
1046 hose->bus = bus;
1047 hose->first_busno = dev_seq(bus);
1048 hose->last_busno = dev_seq(bus);
1049 if (dev_has_ofnode(bus)) {
1050 hose->skip_auto_config_until_reloc =
1051 dev_read_bool(bus,
1052 "u-boot,skip-auto-config-until-reloc");
1053 }
1054
1055 return 0;
1056 }
1057
pci_uclass_post_probe(struct udevice * bus)1058 static int pci_uclass_post_probe(struct udevice *bus)
1059 {
1060 struct pci_controller *hose = dev_get_uclass_priv(bus);
1061 int ret;
1062
1063 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
1064 ret = pci_bind_bus_devices(bus);
1065 if (ret)
1066 return log_msg_ret("bind", ret);
1067
1068 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1069 (!hose->skip_auto_config_until_reloc ||
1070 (gd->flags & GD_FLG_RELOC))) {
1071 ret = pci_auto_config_devices(bus);
1072 if (ret < 0)
1073 return log_msg_ret("cfg", ret);
1074 }
1075
1076 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1077 /*
1078 * Per Intel FSP specification, we should call FSP notify API to
1079 * inform FSP that PCI enumeration has been done so that FSP will
1080 * do any necessary initialization as required by the chipset's
1081 * BIOS Writer's Guide (BWG).
1082 *
1083 * Unfortunately we have to put this call here as with driver model,
1084 * the enumeration is all done on a lazy basis as needed, so until
1085 * something is touched on PCI it won't happen.
1086 *
1087 * Note we only call this 1) after U-Boot is relocated, and 2)
1088 * root bus has finished probing.
1089 */
1090 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
1091 ret = fsp_init_phase_pci();
1092 if (ret)
1093 return log_msg_ret("fsp", ret);
1094 }
1095 #endif
1096
1097 return 0;
1098 }
1099
pci_uclass_child_post_bind(struct udevice * dev)1100 static int pci_uclass_child_post_bind(struct udevice *dev)
1101 {
1102 struct pci_child_plat *pplat;
1103
1104 if (!dev_has_ofnode(dev))
1105 return 0;
1106
1107 pplat = dev_get_parent_plat(dev);
1108
1109 /* Extract vendor id and device id if available */
1110 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1111
1112 /* Extract the devfn from fdt_pci_addr */
1113 pplat->devfn = pci_get_devfn(dev);
1114
1115 return 0;
1116 }
1117
pci_bridge_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)1118 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1119 uint offset, ulong *valuep,
1120 enum pci_size_t size)
1121 {
1122 struct pci_controller *hose = dev_get_uclass_priv(bus);
1123
1124 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1125 }
1126
pci_bridge_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)1127 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1128 uint offset, ulong value,
1129 enum pci_size_t size)
1130 {
1131 struct pci_controller *hose = dev_get_uclass_priv(bus);
1132
1133 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1134 }
1135
skip_to_next_device(struct udevice * bus,struct udevice ** devp)1136 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1137 {
1138 struct udevice *dev;
1139 int ret = 0;
1140
1141 /*
1142 * Scan through all the PCI controllers. On x86 there will only be one
1143 * but that is not necessarily true on other hardware.
1144 */
1145 do {
1146 device_find_first_child(bus, &dev);
1147 if (dev) {
1148 *devp = dev;
1149 return 0;
1150 }
1151 ret = uclass_next_device(&bus);
1152 if (ret)
1153 return ret;
1154 } while (bus);
1155
1156 return 0;
1157 }
1158
pci_find_next_device(struct udevice ** devp)1159 int pci_find_next_device(struct udevice **devp)
1160 {
1161 struct udevice *child = *devp;
1162 struct udevice *bus = child->parent;
1163 int ret;
1164
1165 /* First try all the siblings */
1166 *devp = NULL;
1167 while (child) {
1168 device_find_next_child(&child);
1169 if (child) {
1170 *devp = child;
1171 return 0;
1172 }
1173 }
1174
1175 /* We ran out of siblings. Try the next bus */
1176 ret = uclass_next_device(&bus);
1177 if (ret)
1178 return ret;
1179
1180 return bus ? skip_to_next_device(bus, devp) : 0;
1181 }
1182
pci_find_first_device(struct udevice ** devp)1183 int pci_find_first_device(struct udevice **devp)
1184 {
1185 struct udevice *bus;
1186 int ret;
1187
1188 *devp = NULL;
1189 ret = uclass_first_device(UCLASS_PCI, &bus);
1190 if (ret)
1191 return ret;
1192
1193 return skip_to_next_device(bus, devp);
1194 }
1195
pci_conv_32_to_size(ulong value,uint offset,enum pci_size_t size)1196 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1197 {
1198 switch (size) {
1199 case PCI_SIZE_8:
1200 return (value >> ((offset & 3) * 8)) & 0xff;
1201 case PCI_SIZE_16:
1202 return (value >> ((offset & 2) * 8)) & 0xffff;
1203 default:
1204 return value;
1205 }
1206 }
1207
pci_conv_size_to_32(ulong old,ulong value,uint offset,enum pci_size_t size)1208 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1209 enum pci_size_t size)
1210 {
1211 uint off_mask;
1212 uint val_mask, shift;
1213 ulong ldata, mask;
1214
1215 switch (size) {
1216 case PCI_SIZE_8:
1217 off_mask = 3;
1218 val_mask = 0xff;
1219 break;
1220 case PCI_SIZE_16:
1221 off_mask = 2;
1222 val_mask = 0xffff;
1223 break;
1224 default:
1225 return value;
1226 }
1227 shift = (offset & off_mask) * 8;
1228 ldata = (value & val_mask) << shift;
1229 mask = val_mask << shift;
1230 value = (old & ~mask) | ldata;
1231
1232 return value;
1233 }
1234
pci_get_dma_regions(struct udevice * dev,struct pci_region * memp,int index)1235 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1236 {
1237 int pci_addr_cells, addr_cells, size_cells;
1238 int cells_per_record;
1239 const u32 *prop;
1240 int len;
1241 int i = 0;
1242
1243 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1244 if (!prop) {
1245 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1246 dev->name);
1247 return -EINVAL;
1248 }
1249
1250 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1251 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1252 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1253
1254 /* PCI addresses are always 3-cells */
1255 len /= sizeof(u32);
1256 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1257 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1258 cells_per_record);
1259
1260 while (len) {
1261 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1262 prop += pci_addr_cells;
1263 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1264 prop += addr_cells;
1265 memp->size = fdtdec_get_number(prop, size_cells);
1266 prop += size_cells;
1267
1268 if (i == index)
1269 return 0;
1270 i++;
1271 len -= cells_per_record;
1272 }
1273
1274 return -EINVAL;
1275 }
1276
pci_get_regions(struct udevice * dev,struct pci_region ** iop,struct pci_region ** memp,struct pci_region ** prefp)1277 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1278 struct pci_region **memp, struct pci_region **prefp)
1279 {
1280 struct udevice *bus = pci_get_controller(dev);
1281 struct pci_controller *hose = dev_get_uclass_priv(bus);
1282 int i;
1283
1284 *iop = NULL;
1285 *memp = NULL;
1286 *prefp = NULL;
1287 for (i = 0; i < hose->region_count; i++) {
1288 switch (hose->regions[i].flags) {
1289 case PCI_REGION_IO:
1290 if (!*iop || (*iop)->size < hose->regions[i].size)
1291 *iop = hose->regions + i;
1292 break;
1293 case PCI_REGION_MEM:
1294 if (!*memp || (*memp)->size < hose->regions[i].size)
1295 *memp = hose->regions + i;
1296 break;
1297 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1298 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1299 *prefp = hose->regions + i;
1300 break;
1301 }
1302 }
1303
1304 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1305 }
1306
dm_pci_read_bar32(const struct udevice * dev,int barnum)1307 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1308 {
1309 u32 addr;
1310 int bar;
1311
1312 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1313 dm_pci_read_config32(dev, bar, &addr);
1314
1315 /*
1316 * If we get an invalid address, return this so that comparisons with
1317 * FDT_ADDR_T_NONE work correctly
1318 */
1319 if (addr == 0xffffffff)
1320 return addr;
1321 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1322 return addr & PCI_BASE_ADDRESS_IO_MASK;
1323 else
1324 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1325 }
1326
dm_pci_write_bar32(struct udevice * dev,int barnum,u32 addr)1327 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1328 {
1329 int bar;
1330
1331 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1332 dm_pci_write_config32(dev, bar, addr);
1333 }
1334
_dm_pci_bus_to_phys(struct udevice * ctlr,pci_addr_t bus_addr,unsigned long flags,unsigned long skip_mask,phys_addr_t * pa)1335 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1336 pci_addr_t bus_addr, unsigned long flags,
1337 unsigned long skip_mask, phys_addr_t *pa)
1338 {
1339 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1340 struct pci_region *res;
1341 int i;
1342
1343 if (hose->region_count == 0) {
1344 *pa = bus_addr;
1345 return 0;
1346 }
1347
1348 for (i = 0; i < hose->region_count; i++) {
1349 res = &hose->regions[i];
1350
1351 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1352 continue;
1353
1354 if (res->flags & skip_mask)
1355 continue;
1356
1357 if (bus_addr >= res->bus_start &&
1358 (bus_addr - res->bus_start) < res->size) {
1359 *pa = (bus_addr - res->bus_start + res->phys_start);
1360 return 0;
1361 }
1362 }
1363
1364 return 1;
1365 }
1366
dm_pci_bus_to_phys(struct udevice * dev,pci_addr_t bus_addr,unsigned long flags)1367 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1368 unsigned long flags)
1369 {
1370 phys_addr_t phys_addr = 0;
1371 struct udevice *ctlr;
1372 int ret;
1373
1374 /* The root controller has the region information */
1375 ctlr = pci_get_controller(dev);
1376
1377 /*
1378 * if PCI_REGION_MEM is set we do a two pass search with preference
1379 * on matches that don't have PCI_REGION_SYS_MEMORY set
1380 */
1381 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1382 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1383 flags, PCI_REGION_SYS_MEMORY,
1384 &phys_addr);
1385 if (!ret)
1386 return phys_addr;
1387 }
1388
1389 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1390
1391 if (ret)
1392 puts("pci_hose_bus_to_phys: invalid physical address\n");
1393
1394 return phys_addr;
1395 }
1396
_dm_pci_phys_to_bus(struct udevice * dev,phys_addr_t phys_addr,unsigned long flags,unsigned long skip_mask,pci_addr_t * ba)1397 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1398 unsigned long flags, unsigned long skip_mask,
1399 pci_addr_t *ba)
1400 {
1401 struct pci_region *res;
1402 struct udevice *ctlr;
1403 pci_addr_t bus_addr;
1404 int i;
1405 struct pci_controller *hose;
1406
1407 /* The root controller has the region information */
1408 ctlr = pci_get_controller(dev);
1409 hose = dev_get_uclass_priv(ctlr);
1410
1411 if (hose->region_count == 0) {
1412 *ba = phys_addr;
1413 return 0;
1414 }
1415
1416 for (i = 0; i < hose->region_count; i++) {
1417 res = &hose->regions[i];
1418
1419 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1420 continue;
1421
1422 if (res->flags & skip_mask)
1423 continue;
1424
1425 bus_addr = phys_addr - res->phys_start + res->bus_start;
1426
1427 if (bus_addr >= res->bus_start &&
1428 (bus_addr - res->bus_start) < res->size) {
1429 *ba = bus_addr;
1430 return 0;
1431 }
1432 }
1433
1434 return 1;
1435 }
1436
dm_pci_phys_to_bus(struct udevice * dev,phys_addr_t phys_addr,unsigned long flags)1437 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1438 unsigned long flags)
1439 {
1440 pci_addr_t bus_addr = 0;
1441 int ret;
1442
1443 /*
1444 * if PCI_REGION_MEM is set we do a two pass search with preference
1445 * on matches that don't have PCI_REGION_SYS_MEMORY set
1446 */
1447 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1448 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1449 PCI_REGION_SYS_MEMORY, &bus_addr);
1450 if (!ret)
1451 return bus_addr;
1452 }
1453
1454 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1455
1456 if (ret)
1457 puts("pci_hose_phys_to_bus: invalid physical address\n");
1458
1459 return bus_addr;
1460 }
1461
dm_pci_map_ea_virt(struct udevice * dev,int ea_off,struct pci_child_plat * pdata)1462 static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1463 struct pci_child_plat *pdata)
1464 {
1465 phys_addr_t addr = 0;
1466
1467 /*
1468 * In the case of a Virtual Function device using BAR
1469 * base and size, add offset for VFn BAR(1, 2, 3...n)
1470 */
1471 if (pdata->is_virtfn) {
1472 size_t sz;
1473 u32 ea_entry;
1474
1475 /* MaxOffset, 1st DW */
1476 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1477 sz = ea_entry & PCI_EA_FIELD_MASK;
1478 /* Fill up lower 2 bits */
1479 sz |= (~PCI_EA_FIELD_MASK);
1480
1481 if (ea_entry & PCI_EA_IS_64) {
1482 /* MaxOffset 2nd DW */
1483 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1484 sz |= ((u64)ea_entry) << 32;
1485 }
1486
1487 addr = (pdata->virtid - 1) * (sz + 1);
1488 }
1489
1490 return addr;
1491 }
1492
dm_pci_map_ea_bar(struct udevice * dev,int bar,int flags,int ea_off,struct pci_child_plat * pdata)1493 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1494 int ea_off, struct pci_child_plat *pdata)
1495 {
1496 int ea_cnt, i, entry_size;
1497 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1498 u32 ea_entry;
1499 phys_addr_t addr;
1500
1501 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1502 /*
1503 * In the case of a Virtual Function device, device is
1504 * Physical function, so pdata will point to required VF
1505 * specific data.
1506 */
1507 if (pdata->is_virtfn)
1508 bar_id += PCI_EA_BEI_VF_BAR0;
1509 }
1510
1511 /* EA capability structure header */
1512 dm_pci_read_config32(dev, ea_off, &ea_entry);
1513 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1514 ea_off += PCI_EA_FIRST_ENT;
1515
1516 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1517 /* Entry header */
1518 dm_pci_read_config32(dev, ea_off, &ea_entry);
1519 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1520
1521 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1522 continue;
1523
1524 /* Base address, 1st DW */
1525 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1526 addr = ea_entry & PCI_EA_FIELD_MASK;
1527 if (ea_entry & PCI_EA_IS_64) {
1528 /* Base address, 2nd DW, skip over 4B MaxOffset */
1529 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1530 addr |= ((u64)ea_entry) << 32;
1531 }
1532
1533 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1534 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1535
1536 /* size ignored for now */
1537 return map_physmem(addr, 0, flags);
1538 }
1539
1540 return 0;
1541 }
1542
dm_pci_map_bar(struct udevice * dev,int bar,int flags)1543 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1544 {
1545 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
1546 struct udevice *udev = dev;
1547 pci_addr_t pci_bus_addr;
1548 u32 bar_response;
1549 int ea_off;
1550
1551 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1552 /*
1553 * In case of Virtual Function devices, use PF udevice
1554 * as EA capability is defined in Physical Function
1555 */
1556 if (pdata->is_virtfn)
1557 udev = pdata->pfdev;
1558 }
1559
1560 /*
1561 * if the function supports Enhanced Allocation use that instead of
1562 * BARs
1563 * Incase of virtual functions, pdata will help read VF BEI
1564 * and EA entry size.
1565 */
1566 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1567 if (ea_off)
1568 return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
1569
1570 /* read BAR address */
1571 dm_pci_read_config32(udev, bar, &bar_response);
1572 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1573
1574 /*
1575 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1576 * isn't actually used on any platform because U-Boot assumes a static
1577 * linear mapping. In the future, this could read the BAR size
1578 * and pass that as the size if needed.
1579 */
1580 return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1581 }
1582
_dm_pci_find_next_capability(struct udevice * dev,u8 pos,int cap)1583 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1584 {
1585 int ttl = PCI_FIND_CAP_TTL;
1586 u8 id;
1587 u16 ent;
1588
1589 dm_pci_read_config8(dev, pos, &pos);
1590
1591 while (ttl--) {
1592 if (pos < PCI_STD_HEADER_SIZEOF)
1593 break;
1594 pos &= ~3;
1595 dm_pci_read_config16(dev, pos, &ent);
1596
1597 id = ent & 0xff;
1598 if (id == 0xff)
1599 break;
1600 if (id == cap)
1601 return pos;
1602 pos = (ent >> 8);
1603 }
1604
1605 return 0;
1606 }
1607
dm_pci_find_next_capability(struct udevice * dev,u8 start,int cap)1608 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1609 {
1610 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1611 cap);
1612 }
1613
dm_pci_find_capability(struct udevice * dev,int cap)1614 int dm_pci_find_capability(struct udevice *dev, int cap)
1615 {
1616 u16 status;
1617 u8 header_type;
1618 u8 pos;
1619
1620 dm_pci_read_config16(dev, PCI_STATUS, &status);
1621 if (!(status & PCI_STATUS_CAP_LIST))
1622 return 0;
1623
1624 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1625 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1626 pos = PCI_CB_CAPABILITY_LIST;
1627 else
1628 pos = PCI_CAPABILITY_LIST;
1629
1630 return _dm_pci_find_next_capability(dev, pos, cap);
1631 }
1632
dm_pci_find_next_ext_capability(struct udevice * dev,int start,int cap)1633 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1634 {
1635 u32 header;
1636 int ttl;
1637 int pos = PCI_CFG_SPACE_SIZE;
1638
1639 /* minimum 8 bytes per capability */
1640 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1641
1642 if (start)
1643 pos = start;
1644
1645 dm_pci_read_config32(dev, pos, &header);
1646 /*
1647 * If we have no capabilities, this is indicated by cap ID,
1648 * cap version and next pointer all being 0.
1649 */
1650 if (header == 0)
1651 return 0;
1652
1653 while (ttl--) {
1654 if (PCI_EXT_CAP_ID(header) == cap)
1655 return pos;
1656
1657 pos = PCI_EXT_CAP_NEXT(header);
1658 if (pos < PCI_CFG_SPACE_SIZE)
1659 break;
1660
1661 dm_pci_read_config32(dev, pos, &header);
1662 }
1663
1664 return 0;
1665 }
1666
dm_pci_find_ext_capability(struct udevice * dev,int cap)1667 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1668 {
1669 return dm_pci_find_next_ext_capability(dev, 0, cap);
1670 }
1671
dm_pci_flr(struct udevice * dev)1672 int dm_pci_flr(struct udevice *dev)
1673 {
1674 int pcie_off;
1675 u32 cap;
1676
1677 /* look for PCI Express Capability */
1678 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1679 if (!pcie_off)
1680 return -ENOENT;
1681
1682 /* check FLR capability */
1683 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1684 if (!(cap & PCI_EXP_DEVCAP_FLR))
1685 return -ENOENT;
1686
1687 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1688 PCI_EXP_DEVCTL_BCR_FLR);
1689
1690 /* wait 100ms, per PCI spec */
1691 mdelay(100);
1692
1693 return 0;
1694 }
1695
1696 #if defined(CONFIG_PCI_SRIOV)
pci_sriov_init(struct udevice * pdev,int vf_en)1697 int pci_sriov_init(struct udevice *pdev, int vf_en)
1698 {
1699 u16 vendor, device;
1700 struct udevice *bus;
1701 struct udevice *dev;
1702 pci_dev_t bdf;
1703 u16 ctrl;
1704 u16 num_vfs;
1705 u16 total_vf;
1706 u16 vf_offset;
1707 u16 vf_stride;
1708 int vf, ret;
1709 int pos;
1710
1711 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1712 if (!pos) {
1713 debug("Error: SRIOV capability not found\n");
1714 return -ENOENT;
1715 }
1716
1717 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1718
1719 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1720 if (vf_en > total_vf)
1721 vf_en = total_vf;
1722 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1723
1724 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1725 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1726
1727 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1728 if (num_vfs > vf_en)
1729 num_vfs = vf_en;
1730
1731 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1732 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1733
1734 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1735 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1736
1737 bdf = dm_pci_get_bdf(pdev);
1738
1739 pci_get_bus(PCI_BUS(bdf), &bus);
1740
1741 if (!bus)
1742 return -ENODEV;
1743
1744 bdf += PCI_BDF(0, 0, vf_offset);
1745
1746 for (vf = 0; vf < num_vfs; vf++) {
1747 struct pci_child_plat *pplat;
1748 ulong class;
1749
1750 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1751 &class, PCI_SIZE_16);
1752
1753 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1754 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1755
1756 /* Find this device in the device tree */
1757 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1758
1759 if (ret == -ENODEV) {
1760 struct pci_device_id find_id;
1761
1762 memset(&find_id, '\0', sizeof(find_id));
1763 find_id.vendor = vendor;
1764 find_id.device = device;
1765 find_id.class = class;
1766
1767 ret = pci_find_and_bind_driver(bus, &find_id,
1768 bdf, &dev);
1769
1770 if (ret)
1771 return ret;
1772 }
1773
1774 /* Update the platform data */
1775 pplat = dev_get_parent_plat(dev);
1776 pplat->devfn = PCI_MASK_BUS(bdf);
1777 pplat->vendor = vendor;
1778 pplat->device = device;
1779 pplat->class = class;
1780 pplat->is_virtfn = true;
1781 pplat->pfdev = pdev;
1782 pplat->virtid = vf * vf_stride + vf_offset;
1783
1784 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1785 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
1786 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1787 bdf += PCI_BDF(0, 0, vf_stride);
1788 }
1789
1790 return 0;
1791 }
1792
pci_sriov_get_totalvfs(struct udevice * pdev)1793 int pci_sriov_get_totalvfs(struct udevice *pdev)
1794 {
1795 u16 total_vf;
1796 int pos;
1797
1798 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1799 if (!pos) {
1800 debug("Error: SRIOV capability not found\n");
1801 return -ENOENT;
1802 }
1803
1804 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1805
1806 return total_vf;
1807 }
1808 #endif /* SRIOV */
1809
1810 UCLASS_DRIVER(pci) = {
1811 .id = UCLASS_PCI,
1812 .name = "pci",
1813 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
1814 .post_bind = dm_scan_fdt_dev,
1815 .pre_probe = pci_uclass_pre_probe,
1816 .post_probe = pci_uclass_post_probe,
1817 .child_post_bind = pci_uclass_child_post_bind,
1818 .per_device_auto = sizeof(struct pci_controller),
1819 .per_child_plat_auto = sizeof(struct pci_child_plat),
1820 };
1821
1822 static const struct dm_pci_ops pci_bridge_ops = {
1823 .read_config = pci_bridge_read_config,
1824 .write_config = pci_bridge_write_config,
1825 };
1826
1827 static const struct udevice_id pci_bridge_ids[] = {
1828 { .compatible = "pci-bridge" },
1829 { }
1830 };
1831
1832 U_BOOT_DRIVER(pci_bridge_drv) = {
1833 .name = "pci_bridge_drv",
1834 .id = UCLASS_PCI,
1835 .of_match = pci_bridge_ids,
1836 .ops = &pci_bridge_ops,
1837 };
1838
1839 UCLASS_DRIVER(pci_generic) = {
1840 .id = UCLASS_PCI_GENERIC,
1841 .name = "pci_generic",
1842 };
1843
1844 static const struct udevice_id pci_generic_ids[] = {
1845 { .compatible = "pci-generic" },
1846 { }
1847 };
1848
1849 U_BOOT_DRIVER(pci_generic_drv) = {
1850 .name = "pci_generic_drv",
1851 .id = UCLASS_PCI_GENERIC,
1852 .of_match = pci_generic_ids,
1853 };
1854
pci_init(void)1855 int pci_init(void)
1856 {
1857 struct udevice *bus;
1858
1859 /*
1860 * Enumerate all known controller devices. Enumeration has the side-
1861 * effect of probing them, so PCIe devices will be enumerated too.
1862 */
1863 for (uclass_first_device_check(UCLASS_PCI, &bus);
1864 bus;
1865 uclass_next_device_check(&bus)) {
1866 ;
1867 }
1868
1869 return 0;
1870 }
1871