1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Nexell
4 * Hyunseok, Jung <hsjung@nexell.co.kr>
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <asm/global_data.h>
12 #include <asm/sections.h>
13 #include <asm/io.h>
14 #include <asm/arch/nexell.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/reset.h>
17 #include <asm/arch/tieoff.h>
18 #include <cpu_func.h>
19 #include <linux/delay.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #ifndef CONFIG_ARCH_CPU_INIT
24 #error must be define the macro "CONFIG_ARCH_CPU_INIT"
25 #endif
26
s_init(void)27 void s_init(void)
28 {
29 }
30
cpu_soc_init(void)31 static void cpu_soc_init(void)
32 {
33 /*
34 * NOTE> ALIVE Power Gate must enable for Alive register access.
35 * must be clear wfi jump address
36 */
37 writel(1, ALIVEPWRGATEREG);
38 writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
39
40 /* write 0xf0 on alive scratchpad reg for boot success check */
41 writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
42
43 /* set l2 cache tieoff */
44 nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1);
45 nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
46 }
47
48 #ifdef CONFIG_PL011_SERIAL
serial_device_init(void)49 static void serial_device_init(void)
50 {
51 char dev[10];
52 int id;
53
54 sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
55 id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
56
57 struct clk *clk = clk_get((const char *)dev);
58
59 /* reset control: Low active ___|--- */
60 nx_rstcon_setrst(id, RSTCON_ASSERT);
61 udelay(10);
62 nx_rstcon_setrst(id, RSTCON_NEGATE);
63 udelay(10);
64
65 /* set clock */
66 clk_disable(clk);
67 clk_set_rate(clk, CONFIG_PL011_CLOCK);
68 clk_enable(clk);
69 }
70 #endif
71
arch_cpu_init(void)72 int arch_cpu_init(void)
73 {
74 flush_dcache_all();
75 cpu_soc_init();
76 clk_init();
77
78 if (IS_ENABLED(CONFIG_PL011_SERIAL))
79 serial_device_init();
80
81 return 0;
82 }
83
84 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)85 int print_cpuinfo(void)
86 {
87 return 0;
88 }
89 #endif
90
reset_cpu(void)91 void reset_cpu(void)
92 {
93 void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
94 const u32 sw_rst_enb_bitpos = 3;
95 const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos;
96 const u32 sw_rst_bitpos = 12;
97 const u32 sw_rst_mask = 1 << sw_rst_bitpos;
98 int pwrcont = 0x224;
99 int pwrmode = 0x228;
100 u32 read_value;
101
102 read_value = readl((void *)(clkpwr_reg + pwrcont));
103
104 read_value &= ~sw_rst_enb_mask;
105 read_value |= 1 << sw_rst_enb_bitpos;
106
107 writel(read_value, (void *)(clkpwr_reg + pwrcont));
108 writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode));
109 }
110
enable_caches(void)111 void enable_caches(void)
112 {
113 /* Enable D-cache. I-cache is already enabled in start.S */
114 dcache_enable();
115 }
116
117 #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)118 int arch_misc_init(void)
119 {
120 return 0;
121 }
122 #endif /* CONFIG_ARCH_MISC_INIT */
123