1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * tegra_ahub.h - Definitions for Tegra124 audio hub driver 4 * Taken from dc tegra_ahub.h 5 * 6 * Copyright 2018 Google LLC 7 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 8 */ 9 10 #ifndef _TEGRA_AHUB_H_ 11 #define _TEGRA_AHUB_H_ 12 13 /* 14 * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio 15 * transmitted by a particular TX CIF. 16 */ 17 struct xbar_regs { 18 u32 apbif_rx0; /* AUDIO_APBIF_RX0, offset 0x00 */ 19 u32 apbif_rx1; /* AUDIO_APBIF_RX1, offset 0x04 */ 20 u32 apbif_rx2; /* AUDIO_APBIF_RX2, offset 0x08 */ 21 u32 apbif_rx3; /* AUDIO_APBIF_RX3, offset 0x0C */ 22 23 u32 i2s0_rx0; /* AUDIO_I2S0_RX0, offset 0x10 */ 24 u32 i2s1_rx0; /* AUDIO_I2S1_RX0, offset 0x14 */ 25 u32 i2s2_rx0; /* AUDIO_I2S2_RX0, offset 0x18 */ 26 u32 i2s3_rx0; /* AUDIO_I2S3_RX0, offset 0x1C */ 27 u32 i2s4_rx0; /* AUDIO_I2S4_RX0, offset 0x20 */ 28 29 u32 dam0_rx0; /* AUDIO_DAM0_RX0, offset 0x24 */ 30 u32 dam0_rx1; /* AUDIO_DAM0_RX1, offset 0x28 */ 31 u32 dam1_rx0; /* AUDIO_DAM1_RX0, offset 0x2C */ 32 u32 dam1_rx1; /* AUDIO_DAM1_RX1, offset 0x30 */ 33 u32 dam2_rx0; /* AUDIO_DAM2_RX0, offset 0x34 */ 34 u32 dam2_rx1; /* AUDIO_DAM2_RX1, offset 0x38 */ 35 36 u32 spdif_rx0; /* AUDIO_SPDIF_RX0, offset 0x3C */ 37 u32 spdif_rx1; /* AUDIO_SPDIF_RX1, offset 0x40 */ 38 39 u32 apbif_rx4; /* AUDIO_APBIF_RX4, offset 0x44 */ 40 u32 apbif_rx5; /* AUDIO_APBIF_RX4, offset 0x48 */ 41 u32 apbif_rx6; /* AUDIO_APBIF_RX4, offset 0x4C */ 42 u32 apbif_rx7; /* AUDIO_APBIF_RX4, offset 0x50 */ 43 u32 apbif_rx8; /* AUDIO_APBIF_RX4, offset 0x54 */ 44 u32 apbif_rx9; /* AUDIO_APBIF_RX4, offset 0x58 */ 45 46 u32 amx0_rx0; /* AUDIO_AMX0_RX0, offset 0x5C */ 47 u32 amx0_rx1; /* AUDIO_AMX0_RX1, offset 0x60 */ 48 u32 amx0_rx2; /* AUDIO_AMX0_RX2, offset 0x64 */ 49 u32 amx0_rx3; /* AUDIO_AMX0_RX3, offset 0x68 */ 50 51 u32 adx0_rx0; /* AUDIO_ADX0_RX0, offset 0x6C */ 52 }; 53 54 struct apbif_regs { 55 u32 channel0_ctrl; /* APBIF_CHANNEL0_CTRL */ 56 u32 channel0_clr; /* APBIF_CHANNEL0_CLEAR */ 57 u32 channel0_stat; /* APBIF_CHANNEL0_STATUS */ 58 u32 channel0_txfifo; /* APBIF_CHANNEL0_TXFIFO */ 59 u32 channel0_rxfifo; /* APBIF_CHANNEL0_RXFIFO */ 60 u32 channel0_cif_tx0_ctrl; /* APBIF_AUDIOCIF_TX0_CTRL */ 61 u32 channel0_cif_rx0_ctrl; /* APBIF_AUDIOCIF_RX0_CTRL */ 62 u32 channel0_reserved0; /* RESERVED, offset 0x1C */ 63 /* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ 64 /* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ 65 /* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ 66 u32 reserved123[3 * 8]; 67 u32 config_link_ctrl; /* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */ 68 u32 misc_ctrl; /* APBIF_MISC_CTRL_0, offset 0x84 */ 69 u32 apbdma_live_stat; /* APBIF_APBDMA_LIVE_STATUS_0 */ 70 u32 i2s_live_stat; /* APBIF_I2S_LIVE_STATUS_0 */ 71 u32 dam0_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ 72 u32 dam1_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ 73 u32 dam2_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ 74 u32 spdif_live_stat; /* APBIF_SPDIF_LIVE_STATUS_0 */ 75 u32 i2s_int_mask; /* APBIF_I2S_INT_MASK_0, offset B0 */ 76 u32 dam_int_mask; /* APBIF_DAM_INT_MASK_0 */ 77 u32 reserved_int_mask; /* RESERVED, offset 0xB8 */ 78 u32 spdif_int_mask; /* APBIF_SPDIF_INT_MASK_0 */ 79 u32 apbif_int_mask; /* APBIF_APBIF_INT_MASK_0, off C0 */ 80 u32 reserved2_int_mask; /* RESERVED, offset 0xC4 */ 81 u32 i2s_int_stat; /* APBIF_I2S_INT_STATUS_0, offset C8 */ 82 u32 dam_int_stat; /* APBIF_DAM_INT_STATUS_0 */ 83 u32 reserved_int_stat; /* RESERVED, offset 0xD0 */ 84 u32 spdif_int_stat; /* APBIF_SPDIF_INT_STATUS_0 */ 85 u32 apbif_int_stat; /* APBIF_APBIF_INT_STATUS_0 */ 86 u32 reserved2_int_stat; /* RESERVED, offset 0xDC */ 87 u32 i2s_int_src; /* APBIF_I2S_INT_SOURCE_0, offset E0 */ 88 u32 dam_int_src; /* APBIF_DAM_INT_SOURCE_0 */ 89 u32 reserved_int_src; /* RESERVED, offset 0xE8 */ 90 u32 spdif_int_src; /* APBIF_SPDIF_INT_SOURCE_0 */ 91 u32 apbif_int_src; /* APBIF_APBIF_INT_SOURCE_0, off F0 */ 92 u32 reserved2_int_src; /* RESERVED, offset 0xF4 */ 93 u32 i2s_int_set; /* APBIF_I2S_INT_SET_0, offset 0xF8 */ 94 u32 dam_int_set; /* APBIF_DAM_INT_SET_0, offset 0xFC */ 95 u32 spdif_int_set; /* APBIF_SPDIF_INT_SET_0, off 0x100 */ 96 u32 apbif_int_set; /* APBIF_APBIF_INT_SET_0, off 0x104 */ 97 }; 98 99 /* 100 * Tegra AHUB Registers Definition 101 */ 102 enum { 103 TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT = 24, 104 TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US = 0x3f, 105 TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK = 106 TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << 107 TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT, 108 109 /* Channel count minus 1 */ 110 TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT = 20, 111 TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US = 0xf, 112 TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK = 113 TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << 114 TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT, 115 116 /* Channel count minus 1 */ 117 TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT = 16, 118 TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US = 0xf, 119 TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK = 120 TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << 121 TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT, 122 123 TEGRA_AUDIOCIF_BITS_4 = 0, 124 TEGRA_AUDIOCIF_BITS_8 = 1, 125 TEGRA_AUDIOCIF_BITS_12 = 2, 126 TEGRA_AUDIOCIF_BITS_16 = 3, 127 TEGRA_AUDIOCIF_BITS_20 = 4, 128 TEGRA_AUDIOCIF_BITS_24 = 5, 129 TEGRA_AUDIOCIF_BITS_28 = 6, 130 TEGRA_AUDIOCIF_BITS_32 = 7, 131 132 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT = 12, 133 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_MASK = 134 7 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 135 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_4 = 136 TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 137 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_8 = 138 TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 139 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_12 = 140 TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 141 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_16 = 142 TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 143 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_20 = 144 TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 145 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_24 = 146 TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 147 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_28 = 148 TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 149 TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_32 = 150 TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, 151 152 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT = 8, 153 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_MASK = 154 7 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 155 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_4 = 156 TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 157 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_8 = 158 TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 159 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_12 = 160 TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 161 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_16 = 162 TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 163 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_20 = 164 TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 165 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_24 = 166 TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 167 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_28 = 168 TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 169 TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_32 = 170 TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, 171 172 TEGRA_AUDIOCIF_EXPAND_ZERO = 0, 173 TEGRA_AUDIOCIF_EXPAND_ONE = 1, 174 TEGRA_AUDIOCIF_EXPAND_LFSR = 2, 175 176 TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT = 6, 177 TEGRA_AUDIOCIF_CTRL_EXPAND_MASK = 3 << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, 178 TEGRA_AUDIOCIF_CTRL_EXPAND_ZERO = 179 TEGRA_AUDIOCIF_EXPAND_ZERO << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, 180 TEGRA_AUDIOCIF_CTRL_EXPAND_ONE = 181 TEGRA_AUDIOCIF_EXPAND_ONE << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, 182 TEGRA_AUDIOCIF_CTRL_EXPAND_LFSR = 183 TEGRA_AUDIOCIF_EXPAND_LFSR << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, 184 185 TEGRA_AUDIOCIF_STEREO_CONV_CH0 = 0, 186 TEGRA_AUDIOCIF_STEREO_CONV_CH1 = 1, 187 TEGRA_AUDIOCIF_STEREO_CONV_AVG = 2, 188 189 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT = 4, 190 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_MASK = 191 3 << TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, 192 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH0 = 193 TEGRA_AUDIOCIF_STEREO_CONV_CH0 << 194 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, 195 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH1 = 196 TEGRA_AUDIOCIF_STEREO_CONV_CH1 << 197 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, 198 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_AVG = 199 TEGRA_AUDIOCIF_STEREO_CONV_AVG << 200 TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, 201 202 TEGRA_AUDIOCIF_CTRL_REPLICATE = 3, 203 204 TEGRA_AUDIOCIF_DIRECTION_TX = 0, 205 TEGRA_AUDIOCIF_DIRECTION_RX = 1, 206 207 TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT = 2, 208 TEGRA_AUDIOCIF_CTRL_DIRECTION_MASK = 209 1 << TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, 210 TEGRA_AUDIOCIF_CTRL_DIRECTION_TX = 211 TEGRA_AUDIOCIF_DIRECTION_TX << 212 TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, 213 TEGRA_AUDIOCIF_CTRL_DIRECTION_RX = 214 TEGRA_AUDIOCIF_DIRECTION_RX << 215 TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, 216 217 TEGRA_AUDIOCIF_TRUNCATE_ROUND = 0, 218 TEGRA_AUDIOCIF_TRUNCATE_CHOP = 1, 219 220 TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT = 1, 221 TEGRA_AUDIOCIF_CTRL_TRUNCATE_MASK = 222 1 << TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, 223 TEGRA_AUDIOCIF_CTRL_TRUNCATE_ROUND = 224 TEGRA_AUDIOCIF_TRUNCATE_ROUND << 225 TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, 226 TEGRA_AUDIOCIF_CTRL_TRUNCATE_CHOP = 227 TEGRA_AUDIOCIF_TRUNCATE_CHOP << 228 TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, 229 230 TEGRA_AUDIOCIF_MONO_CONV_ZERO = 0, 231 TEGRA_AUDIOCIF_MONO_CONV_COPY = 1, 232 233 TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT = 0, 234 TEGRA_AUDIOCIF_CTRL_MONO_CONV_MASK = 235 1 << TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, 236 TEGRA_AUDIOCIF_CTRL_MONO_CONV_ZERO = 237 TEGRA_AUDIOCIF_MONO_CONV_ZERO << 238 TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, 239 TEGRA_AUDIOCIF_CTRL_MONO_CONV_COPY = 240 TEGRA_AUDIOCIF_MONO_CONV_COPY << 241 TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, 242 243 /* Registers within TEGRA_AUDIO_CLUSTER_BASE */ 244 245 TEGRA_AHUB_CHANNEL_CTRL = 0x0, 246 TEGRA_AHUB_CHANNEL_CTRL_STRIDE = 0x20, 247 TEGRA_AHUB_CHANNEL_CTRL_COUNT = 4, 248 TEGRA_AHUB_CHANNEL_CTRL_TX_EN = 1 << 31, 249 TEGRA_AHUB_CHANNEL_CTRL_RX_EN = 1 << 30, 250 TEGRA_AHUB_CHANNEL_CTRL_LOOPBACK = 1 << 29, 251 252 TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT = 16, 253 TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US = 0xff, 254 TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK = 255 TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << 256 TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT, 257 258 TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT = 8, 259 TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US = 0xff, 260 TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK = 261 TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << 262 TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT, 263 264 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN = 1 << 6, 265 266 TEGRA_PACK_8_4 = 2, 267 TEGRA_PACK_16 = 3, 268 269 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT = 4, 270 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US = 3, 271 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK = 272 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << 273 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, 274 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_8_4 = 275 TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, 276 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 = 277 TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, 278 279 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_EN = 1 << 2, 280 281 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT = 0, 282 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US = 3, 283 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK = 284 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << 285 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, 286 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_8_4 = 287 TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, 288 TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_16 = 289 TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, 290 291 /* TEGRA_AHUB_CHANNEL_CLEAR */ 292 293 TEGRA_AHUB_CHANNEL_CLEAR = 0x4, 294 TEGRA_AHUB_CHANNEL_CLEAR_STRIDE = 0x20, 295 TEGRA_AHUB_CHANNEL_CLEAR_COUNT = 4, 296 TEGRA_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET = 1 << 31, 297 TEGRA_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET = 1 << 30, 298 299 TEGRA_AHUB_CHANNEL_STATUS = 0x8, 300 TEGRA_AHUB_CHANNEL_STATUS_STRIDE = 0x20, 301 TEGRA_AHUB_CHANNEL_STATUS_COUNT = 4, 302 TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT = 24, 303 TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US = 0xff, 304 TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK = 305 TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << 306 TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT, 307 TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT = 16, 308 TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US = 0xff, 309 TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK = 310 TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << 311 TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT, 312 TEGRA_AHUB_CHANNEL_STATUS_TX_TRIG = 1 << 1, 313 TEGRA_AHUB_CHANNEL_STATUS_RX_TRIG = 1 << 0, 314 315 TEGRA_AHUB_CHANNEL_TXFIFO = 0xc, 316 TEGRA_AHUB_CHANNEL_TXFIFO_STRIDE = 0x20, 317 TEGRA_AHUB_CHANNEL_TXFIFO_COUNT = 4, 318 319 TEGRA_AHUB_CHANNEL_RXFIFO = 0x10, 320 TEGRA_AHUB_CHANNEL_RXFIFO_STRIDE = 0x20, 321 TEGRA_AHUB_CHANNEL_RXFIFO_COUNT = 4, 322 323 TEGRA_AHUB_CIF_TX_CTRL = 0x14, 324 TEGRA_AHUB_CIF_TX_CTRL_STRIDE = 0x20, 325 TEGRA_AHUB_CIF_TX_CTRL_COUNT = 4, 326 /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ 327 328 TEGRA_AHUB_CIF_RX_CTRL = 0x18, 329 TEGRA_AHUB_CIF_RX_CTRL_STRIDE = 0x20, 330 TEGRA_AHUB_CIF_RX_CTRL_COUNT = 4, 331 /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ 332 333 TEGRA_AHUB_CONFIG_LINK_CTRL = 0x80, 334 TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT = 28, 335 TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US = 0xf, 336 TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK = 337 TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << 338 TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT, 339 TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT = 16, 340 TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US = 0xfff, 341 TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK = 342 TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << 343 TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT, 344 TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT = 4, 345 TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US = 0xfff, 346 TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK = 347 TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << 348 TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT, 349 TEGRA_AHUB_CONFIG_LINK_CTRL_CG_EN = 1 << 2, 350 TEGRA_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR = 1 << 1, 351 TEGRA_AHUB_CONFIG_LINK_CTRL_SOFT_RESET = 1 << 0, 352 353 TEGRA_AHUB_MISC_CTRL = 0x84, 354 TEGRA_AHUB_MISC_CTRL_AUDIO_ACTIVE = 1 << 31, 355 TEGRA_AHUB_MISC_CTRL_AUDIO_CG_EN = 1 << 8, 356 TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT = 0, 357 TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK = 358 0x1f << TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT, 359 360 TEGRA_AHUB_APBDMA_LIVE_STATUS = 0x88, 361 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL = 1 << 31, 362 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL = 1 << 30, 363 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL = 1 << 29, 364 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL = 1 << 28, 365 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL = 1 << 27, 366 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL = 1 << 26, 367 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL = 1 << 25, 368 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL = 1 << 24, 369 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY = 1 << 23, 370 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY = 1 << 22, 371 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY = 1 << 21, 372 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY = 1 << 20, 373 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY = 1 << 19, 374 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY = 1 << 18, 375 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY = 1 << 17, 376 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY = 1 << 16, 377 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL = 1 << 15, 378 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL = 1 << 14, 379 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL = 1 << 13, 380 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL = 1 << 12, 381 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL = 1 << 11, 382 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL = 1 << 10, 383 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL = 1 << 9, 384 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL = 1 << 8, 385 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY = 1 << 7, 386 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY = 1 << 6, 387 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY = 1 << 5, 388 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY = 1 << 4, 389 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY = 1 << 3, 390 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY = 1 << 2, 391 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY = 1 << 1, 392 TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY = 1 << 0, 393 394 TEGRA_AHUB_I2S_LIVE_STATUS = 0x8c, 395 TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL = 1 << 29, 396 TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL = 1 << 28, 397 TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL = 1 << 27, 398 TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL = 1 << 26, 399 TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL = 1 << 25, 400 TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL = 1 << 24, 401 TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL = 1 << 23, 402 TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL = 1 << 22, 403 TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL = 1 << 21, 404 TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL = 1 << 20, 405 TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED = 1 << 19, 406 TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED = 1 << 18, 407 TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED = 1 << 17, 408 TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED = 1 << 16, 409 TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED = 1 << 15, 410 TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED = 1 << 14, 411 TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED = 1 << 13, 412 TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED = 1 << 12, 413 TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED = 1 << 11, 414 TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED = 1 << 10, 415 TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY = 1 << 9, 416 TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY = 1 << 8, 417 TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY = 1 << 7, 418 TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY = 1 << 6, 419 TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY = 1 << 5, 420 TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY = 1 << 4, 421 TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY = 1 << 3, 422 TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY = 1 << 2, 423 TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY = 1 << 1, 424 TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY = 1 << 0, 425 426 TEGRA_AHUB_DAM_LIVE_STATUS = 0x90, 427 TEGRA_AHUB_DAM_LIVE_STATUS_STRIDE = 0x8, 428 TEGRA_AHUB_DAM_LIVE_STATUS_COUNT = 3, 429 TEGRA_AHUB_DAM_LIVE_STATUS_TX_ENABLED = 1 << 26, 430 TEGRA_AHUB_DAM_LIVE_STATUS_RX1_ENABLED = 1 << 25, 431 TEGRA_AHUB_DAM_LIVE_STATUS_RX0_ENABLED = 1 << 24, 432 TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL = 1 << 15, 433 TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL = 1 << 9, 434 TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL = 1 << 8, 435 TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY = 1 << 7, 436 TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY = 1 << 1, 437 TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY = 1 << 0, 438 439 TEGRA_AHUB_SPDIF_LIVE_STATUS = 0xa8, 440 TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED = 1 << 11, 441 TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED = 1 << 10, 442 TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED = 1 << 9, 443 TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED = 1 << 8, 444 TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL = 1 << 7, 445 TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL = 1 << 6, 446 TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL = 1 << 5, 447 TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL = 1 << 4, 448 TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY = 1 << 3, 449 TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY = 1 << 2, 450 TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY = 1 << 1, 451 TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY = 1 << 0, 452 453 TEGRA_AHUB_I2S_INT_MASK = 0xb0, 454 TEGRA_AHUB_DAM_INT_MASK = 0xb4, 455 TEGRA_AHUB_SPDIF_INT_MASK = 0xbc, 456 TEGRA_AHUB_APBIF_INT_MASK = 0xc0, 457 TEGRA_AHUB_I2S_INT_STATUS = 0xc8, 458 TEGRA_AHUB_DAM_INT_STATUS = 0xcc, 459 TEGRA_AHUB_SPDIF_INT_STATUS = 0xd4, 460 TEGRA_AHUB_APBIF_INT_STATUS = 0xd8, 461 TEGRA_AHUB_I2S_INT_SOURCE = 0xe0, 462 TEGRA_AHUB_DAM_INT_SOURCE = 0xe4, 463 TEGRA_AHUB_SPDIF_INT_SOURCE = 0xec, 464 TEGRA_AHUB_APBIF_INT_SOURCE = 0xf0, 465 TEGRA_AHUB_I2S_INT_SET = 0xf8, 466 TEGRA_AHUB_DAM_INT_SET = 0xfc, 467 TEGRA_AHUB_SPDIF_INT_SET = 0x100, 468 TEGRA_AHUB_APBIF_INT_SET = 0x104, 469 470 TEGRA_AHUB_AUDIO_RX = 0x0, 471 TEGRA_AHUB_AUDIO_RX_STRIDE = 0x4, 472 TEGRA_AHUB_AUDIO_RX_COUNT = 17, 473 }; 474 475 #endif /* _TEGRA_I2C_H_ */ 476