1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8 #ifndef _MTMIPS_MC_H_ 9 #define _MTMIPS_MC_H_ 10 11 #define MEMCTL_SDRAM_CFG0_REG 0x00 12 #define DIS_CLK_GT 0x80000000 13 #define CLK_SLEW_S 29 14 #define CLK_SLEW_M 0x60000000 15 #define TWR 0x10000000 16 #define TMRD_S 24 17 #define TMRD_M 0xf000000 18 #define TRFC_S 20 19 #define TRFC_M 0xf00000 20 #define TCAS_S 16 21 #define TCAS_M 0x30000 22 #define TRAS_S 12 23 #define TRAS_M 0xf000 24 #define TRCD_S 8 25 #define TRCD_M 0x300 26 #define TRC_S 4 27 #define TRC_M 0xf0 28 #define TRP_S 0 29 #define TRP_M 0x03 30 31 #define MEMCTL_SDRAM_CFG1_REG 0x04 32 #define SDRAM_INIT_START 0x80000000 33 #define SDRAM_INIT_DONE 0x40000000 34 #define RBC_MAPPING 0x20000000 35 #define PWR_DOWN_EN 0x10000000 36 #define PWR_DOWN_MODE 0x8000000 37 #define SDRAM_WIDTH 0x1000000 38 #define NUMCOLS_S 20 39 #define NUMCOLS_M 0x300000 40 #define NUMROWS_S 16 41 #define NUMROWS_M 0x30000 42 #define TREFR_S 0 43 #define TREFR_M 0xffff 44 45 #define MEMCTL_DDR_SELF_REFRESH_REG 0x10 46 #define ODT_SRC_SEL_S 24 47 #define ODT_SRC_SEL_M 0xf000000 48 #define ODT_OFF_DLY_S 20 49 #define ODT_OFF_DLY_M 0xf00000 50 #define ODT_ON_DLY_S 16 51 #define ODT_ON_DLY_M 0xf0000 52 #define SR_AUTO_EN 0x10 53 #define SRACK_B 0x02 54 #define SRREQ_B 0x01 55 56 #define MEMCTL_PWR_SAVE_CNT_REG 0x14 57 #define PD_CNT_S 24 58 #define PD_CNT_M 0xff000000 59 #define SR_TAR_CNT_S 0 60 #define SR_TAR_CNT_M 0xffffff 61 62 #define MEMCTL_DLL_DBG_REG 0x20 63 #define TDC_STABLE_S 12 64 #define TDC_STABLE_M 0x3f000 65 #define MST_DLY_SEL_S 4 66 #define MST_DLY_SEL_M 0xff0 67 #define CURR_STATE_S 1 68 #define CURR_STATE_M 0x06 69 #define ADLL_LOCK_DONE 0x01 70 71 #define MEMCTL_DDR_CFG0_REG 0x40 72 #define T_RRD_S 28 73 #define T_RRD_M 0xf0000000 74 #define T_RAS_S 23 75 #define T_RAS_M 0xf800000 76 #define T_RP_S 19 77 #define T_RP_M 0x780000 78 #define T_RFC_S 13 79 #define T_RFC_M 0x7e000 80 #define T_REFI_S 0 81 #define T_REFI_M 0x1fff 82 83 #define MEMCTL_DDR_CFG1_REG 0x44 84 #define T_WTR_S 28 85 #define T_WTR_M 0xf0000000 86 #define T_RTP_S 24 87 #define T_RTP_M 0xf000000 88 #define USER_DATA_WIDTH 0x200000 89 #define IND_SDRAM_SIZE_S 18 90 #define IND_SDRAM_SIZE_M 0x1c0000 91 #define IND_SDRAM_SIZE_8MB 1 92 #define IND_SDRAM_SIZE_16MB 2 93 #define IND_SDRAM_SIZE_32MB 3 94 #define IND_SDRAM_SIZE_64MB 4 95 #define IND_SDRAM_SIZE_128MB 5 96 #define IND_SDRAM_SIZE_256MB 6 97 #define IND_SDRAM_WIDTH_S 16 98 #define IND_SDRAM_WIDTH_M 0x30000 99 #define IND_SDRAM_WIDTH_8BIT 1 100 #define IND_SDRAM_WIDTH_16BIT 2 101 #define EXT_BANK_S 14 102 #define EXT_BANK_M 0xc000 103 #define TOTAL_SDRAM_WIDTH_S 12 104 #define TOTAL_SDRAM_WIDTH_M 0x3000 105 #define T_WR_S 8 106 #define T_WR_M 0xf00 107 #define T_MRD_S 4 108 #define T_MRD_M 0xf0 109 #define T_RCD_S 0 110 #define T_RCD_M 0x0f 111 112 #define MEMCTL_DDR_CFG2_REG 0x48 113 #define REGE 0x80000000 114 #define DDR2_MODE 0x40000000 115 #define DQS0_GATING_WINDOW_S 28 116 #define DQS0_GATING_WINDOW_M 0x30000000 117 #define DQS1_GATING_WINDOW_S 26 118 #define DQS1_GATING_WINDOW_M 0xc000000 119 #define PD 0x1000 120 #define WR_S 9 121 #define WR_M 0xe00 122 #define DLLRESET 0x100 123 #define TESTMODE 0x80 124 #define CAS_LATENCY_S 4 125 #define CAS_LATENCY_M 0x70 126 #define BURST_TYPE 0x08 127 #define BURST_LENGTH_S 0 128 #define BURST_LENGTH_M 0x07 129 130 #define MEMCTL_DDR_CFG3_REG 0x4c 131 #define Q_OFF 0x1000 132 #define RDOS 0x800 133 #define DIS_DIFF_DQS 0x400 134 #define OCD_S 7 135 #define OCD_M 0x380 136 #define RTT1 0x40 137 #define ADDITIVE_LATENCY_S 3 138 #define ADDITIVE_LATENCY_M 0x38 139 #define RTT0 0x04 140 #define DS 0x02 141 #define DLL 0x01 142 143 #define MEMCTL_DDR_CFG4_REG 0x50 144 #define FAW_S 0 145 #define FAW_M 0x0f 146 147 #define MEMCTL_DDR_DQ_DLY_REG 0x60 148 #define DQ1_DELAY_SEL_S 24 149 #define DQ1_DELAY_SEL_M 0xff000000 150 #define DQ0_DELAY_SEL_S 16 151 #define DQ0_DELAY_SEL_M 0xff0000 152 #define DQ1_DELAY_COARSE_TUNING_S 12 153 #define DQ1_DELAY_COARSE_TUNING_M 0xf000 154 #define DQ1_DELAY_FINE_TUNING_S 8 155 #define DQ1_DELAY_FINE_TUNING_M 0xf00 156 #define DQ0_DELAY_COARSE_TUNING_S 4 157 #define DQ0_DELAY_COARSE_TUNING_M 0xf0 158 #define DQ0_DELAY_FINE_TUNING_S 0 159 #define DQ0_DELAY_FINE_TUNING_M 0x0f 160 161 #define MEMCTL_DDR_DQS_DLY_REG 0x64 162 #define DQS1_DELAY_SEL_S 24 163 #define DQS1_DELAY_SEL_M 0xff000000 164 #define DQS0_DELAY_SEL_S 16 165 #define DQS0_DELAY_SEL_M 0xff0000 166 #define DQS1_DELAY_COARSE_TUNING_S 12 167 #define DQS1_DELAY_COARSE_TUNING_M 0xf000 168 #define DQS1_DELAY_FINE_TUNING_S 8 169 #define DQS1_DELAY_FINE_TUNING_M 0xf00 170 #define DQS0_DELAY_COARSE_TUNING_S 4 171 #define DQS0_DELAY_COARSE_TUNING_M 0xf0 172 #define DQS0_DELAY_FINE_TUNING_S 0 173 #define DQS0_DELAY_FINE_TUNING_M 0x0f 174 175 #define MEMCTL_DDR_DLL_SLV_REG 0x68 176 #define DLL_SLV_UPDATE_MODE 0x100 177 #define DQS_DLY_SEL_EN 0x80 178 #define DQ_DLY_SEL_EN 0x01 179 180 #endif /* _MTMIPS_MC_H_ */ 181