1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 *
10 * (C) Copyright 2003
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
13 *
14 * (C) Copyright 2004
15 * ARM Ltd.
16 * Philippe Robin, <philippe.robin@arm.com>
17 *
18 * (C) Copyright 2011
19 * Linaro
20 * Linus Walleij <linus.walleij@linaro.org>
21 */
22 #include <common.h>
23 #include <init.h>
24 #include <log.h>
25 #include <pci.h>
26 #include <asm/io.h>
27 #include <linux/bug.h>
28 #include <linux/delay.h>
29 #include "integrator-sc.h"
30 #include "pci_v3.h"
31
32 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
33 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
34
35 /*
36 * These are in the physical addresses on the CPU side, i.e.
37 * where we read and write stuff - you don't want to try to
38 * move these around
39 */
40 #define PHYS_PCI_MEM_BASE 0x40000000
41 #define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
42 #define PHYS_PCI_CONFIG_BASE 0x61000000
43 #define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
44 #define SZ_256M 0x10000000
45
46 /*
47 * These are in the PCI BUS address space
48 * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
49 * we follow the example of the kernel, because that is the address
50 * range that devices actually use - what would they be doing at
51 * 0x40000000?
52 */
53 #define PCI_BUS_NONMEM_START 0x00000000
54 #define PCI_BUS_NONMEM_SIZE SZ_256M
55
56 #define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
57 #define PCI_BUS_PREMEM_SIZE SZ_256M
58
59 #if PCI_BUS_NONMEM_START & 0x000fffff
60 #error PCI_BUS_NONMEM_START must be megabyte aligned
61 #endif
62 #if PCI_BUS_PREMEM_START & 0x000fffff
63 #error PCI_BUS_PREMEM_START must be megabyte aligned
64 #endif
65
66 /*
67 * Initialize PCI Devices, report devices found.
68 */
69
70 #ifndef CONFIG_PCI_PNP
71 #define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */
72 #define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */
73 static struct pci_config_table pci_integrator_config_table[] = {
74 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
75 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
76 PCI_ENET0_MEMADDR,
77 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
78 { }
79 };
80 #endif /* CONFIG_PCI_PNP */
81
82 /* V3 access routines */
83 #define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
84 #define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
85
86 #define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
87 #define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
88
89 #define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
90 #define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
91
v3_open_config_window(pci_dev_t bdf,int offset)92 static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
93 {
94 unsigned int address, mapaddress;
95 unsigned int busnr = PCI_BUS(bdf);
96 unsigned int devfn = PCI_FUNC(bdf);
97
98 /*
99 * Trap out illegal values
100 */
101 if (offset > 255)
102 BUG();
103 if (busnr > 255)
104 BUG();
105 if (devfn > 255)
106 BUG();
107
108 if (busnr == 0) {
109 /*
110 * Linux calls the thing U-Boot calls "DEV" "SLOT"
111 * instead, but it's the same 5 bits
112 */
113 int slot = PCI_DEV(bdf);
114
115 /*
116 * local bus segment so need a type 0 config cycle
117 *
118 * build the PCI configuration "address" with one-hot in
119 * A31-A11
120 *
121 * mapaddress:
122 * 3:1 = config cycle (101)
123 * 0 = PCI A1 & A0 are 0 (0)
124 */
125 address = PCI_FUNC(bdf) << 8;
126 mapaddress = V3_LB_MAP_TYPE_CONFIG;
127
128 if (slot > 12)
129 /*
130 * high order bits are handled by the MAP register
131 */
132 mapaddress |= 1 << (slot - 5);
133 else
134 /*
135 * low order bits handled directly in the address
136 */
137 address |= 1 << (slot + 11);
138 } else {
139 /*
140 * not the local bus segment so need a type 1 config cycle
141 *
142 * address:
143 * 23:16 = bus number
144 * 15:11 = slot number (7:3 of devfn)
145 * 10:8 = func number (2:0 of devfn)
146 *
147 * mapaddress:
148 * 3:1 = config cycle (101)
149 * 0 = PCI A1 & A0 from host bus (1)
150 */
151 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
152 address = (busnr << 16) | (devfn << 8);
153 }
154
155 /*
156 * Set up base0 to see all 512Mbytes of memory space (not
157 * prefetchable), this frees up base1 for re-use by
158 * configuration memory
159 */
160 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
161 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
162
163 /*
164 * Set up base1/map1 to point into configuration space.
165 */
166 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
167 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
168 v3_writew(V3_LB_MAP1, mapaddress);
169
170 return PHYS_PCI_CONFIG_BASE + address + offset;
171 }
172
v3_close_config_window(void)173 static void v3_close_config_window(void)
174 {
175 /*
176 * Reassign base1 for use by prefetchable PCI memory
177 */
178 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
179 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
180 V3_LB_BASE_ENABLE);
181 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
182 V3_LB_MAP_TYPE_MEM_MULTIPLE);
183
184 /*
185 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
186 */
187 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
188 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
189 }
190
pci_integrator_read_byte(struct pci_controller * hose,pci_dev_t bdf,int offset,unsigned char * val)191 static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
192 int offset, unsigned char *val)
193 {
194 unsigned long addr;
195
196 addr = v3_open_config_window(bdf, offset);
197 *val = __raw_readb(addr);
198 v3_close_config_window();
199 return 0;
200 }
201
pci_integrator_read__word(struct pci_controller * hose,pci_dev_t bdf,int offset,unsigned short * val)202 static int pci_integrator_read__word(struct pci_controller *hose,
203 pci_dev_t bdf, int offset,
204 unsigned short *val)
205 {
206 unsigned long addr;
207
208 addr = v3_open_config_window(bdf, offset);
209 *val = __raw_readw(addr);
210 v3_close_config_window();
211 return 0;
212 }
213
pci_integrator_read_dword(struct pci_controller * hose,pci_dev_t bdf,int offset,unsigned int * val)214 static int pci_integrator_read_dword(struct pci_controller *hose,
215 pci_dev_t bdf, int offset,
216 unsigned int *val)
217 {
218 unsigned long addr;
219
220 addr = v3_open_config_window(bdf, offset);
221 *val = __raw_readl(addr);
222 v3_close_config_window();
223 return 0;
224 }
225
pci_integrator_write_byte(struct pci_controller * hose,pci_dev_t bdf,int offset,unsigned char val)226 static int pci_integrator_write_byte(struct pci_controller *hose,
227 pci_dev_t bdf, int offset,
228 unsigned char val)
229 {
230 unsigned long addr;
231
232 addr = v3_open_config_window(bdf, offset);
233 __raw_writeb((u8)val, addr);
234 __raw_readb(addr);
235 v3_close_config_window();
236 return 0;
237 }
238
pci_integrator_write_word(struct pci_controller * hose,pci_dev_t bdf,int offset,unsigned short val)239 static int pci_integrator_write_word(struct pci_controller *hose,
240 pci_dev_t bdf, int offset,
241 unsigned short val)
242 {
243 unsigned long addr;
244
245 addr = v3_open_config_window(bdf, offset);
246 __raw_writew((u8)val, addr);
247 __raw_readw(addr);
248 v3_close_config_window();
249 return 0;
250 }
251
pci_integrator_write_dword(struct pci_controller * hose,pci_dev_t bdf,int offset,unsigned int val)252 static int pci_integrator_write_dword(struct pci_controller *hose,
253 pci_dev_t bdf, int offset,
254 unsigned int val)
255 {
256 unsigned long addr;
257
258 addr = v3_open_config_window(bdf, offset);
259 __raw_writel((u8)val, addr);
260 __raw_readl(addr);
261 v3_close_config_window();
262 return 0;
263 }
264
265 struct pci_controller integrator_hose = {
266 #ifndef CONFIG_PCI_PNP
267 config_table: pci_integrator_config_table,
268 #endif
269 };
270
pci_init_board(void)271 void pci_init_board(void)
272 {
273 struct pci_controller *hose = &integrator_hose;
274 u16 val;
275
276 /* setting this register will take the V3 out of reset */
277 __raw_writel(SC_PCI_PCIEN, SC_PCI);
278
279 /* Wait for 230 ms (from spec) before accessing any V3 registers */
280 mdelay(230);
281
282 /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
283 v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
284
285 /* Wait for the mailbox to settle */
286 do {
287 v3_writeb(V3_MAIL_DATA, 0xAA);
288 v3_writeb(V3_MAIL_DATA + 4, 0x55);
289 } while (v3_readb(V3_MAIL_DATA) != 0xAA ||
290 v3_readb(V3_MAIL_DATA + 4) != 0x55);
291
292 /* Make sure that V3 register access is not locked, if it is, unlock it */
293 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
294 v3_writew(V3_SYSTEM, 0xA05F);
295
296 /*
297 * Ensure that the slave accesses from PCI are disabled while we
298 * setup memory windows
299 */
300 val = v3_readw(V3_PCI_CMD);
301 val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
302 v3_writew(V3_PCI_CMD, val);
303
304 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
305 val = v3_readw(V3_SYSTEM);
306 val &= ~V3_SYSTEM_M_RST_OUT;
307 v3_writew(V3_SYSTEM, val);
308
309 /* Make all accesses from PCI space retry until we're ready for them */
310 val = v3_readw(V3_PCI_CFG);
311 val |= V3_PCI_CFG_M_RETRY_EN;
312 v3_writew(V3_PCI_CFG, val);
313
314 /*
315 * Set up any V3 PCI Configuration Registers that we absolutely have to.
316 * LB_CFG controls Local Bus protocol.
317 * Enable LocalBus byte strobes for READ accesses too.
318 * set bit 7 BE_IMODE and bit 6 BE_OMODE
319 */
320 val = v3_readw(V3_LB_CFG);
321 val |= 0x0C0;
322 v3_writew(V3_LB_CFG, val);
323
324 /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
325 val = v3_readw(V3_PCI_CMD);
326 val |= V3_COMMAND_M_MASTER_EN;
327 v3_writew(V3_PCI_CMD, val);
328
329 /*
330 * PCI_MAP0 controls where the PCI to CPU memory window is on
331 * Local Bus
332 */
333 v3_writel(V3_PCI_MAP0,
334 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
335 V3_PCI_MAP_M_REG_EN |
336 V3_PCI_MAP_M_ENABLE));
337
338 /* PCI_BASE0 is the PCI address of the start of the window */
339 v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
340
341 /* PCI_MAP1 is LOCAL address of the start of the window */
342 v3_writel(V3_PCI_MAP1,
343 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
344 V3_PCI_MAP_M_REG_EN |
345 V3_PCI_MAP_M_ENABLE));
346
347 /* PCI_BASE1 is the PCI address of the start of the window */
348 v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
349
350 /*
351 * Set up memory the windows from local bus memory into PCI
352 * configuration, I/O and Memory regions.
353 * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
354 */
355 v3_writew(V3_LB_BASE2,
356 v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
357 v3_writew(V3_LB_MAP2, 0);
358
359 /* PCI Configuration, use LB_BASE1/LB_MAP1. */
360
361 /*
362 * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
363 * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
364 */
365 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
366 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
367 v3_writew(V3_LB_MAP0,
368 v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
369
370 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
371 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
372 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
373 V3_LB_BASE_ENABLE);
374 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
375 V3_LB_MAP_TYPE_MEM_MULTIPLE);
376
377 /* Dump PCI to local address space mappings */
378 debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
379 debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
380 debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
381 debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
382 debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
383 debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
384 debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
385
386 /*
387 * Allow accesses to PCI Configuration space and set up A1, A0 for
388 * type 1 config cycles
389 */
390 val = v3_readw(V3_PCI_CFG);
391 val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
392 val |= V3_PCI_CFG_M_AD_LOW0;
393 v3_writew(V3_PCI_CFG, val);
394
395 /* now we can allow incoming PCI MEMORY accesses */
396 val = v3_readw(V3_PCI_CMD);
397 val |= V3_COMMAND_M_MEM_EN;
398 v3_writew(V3_PCI_CMD, val);
399
400 /*
401 * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
402 * now initialise.
403 */
404 val = v3_readw(V3_SYSTEM);
405 val |= V3_SYSTEM_M_RST_OUT;
406 v3_writew(V3_SYSTEM, val);
407
408 /* Lock the V3 system register so that no one else can play with it */
409 val = v3_readw(V3_SYSTEM);
410 val |= V3_SYSTEM_M_LOCK;
411 v3_writew(V3_SYSTEM, val);
412
413 /*
414 * Configure and register the PCI hose
415 */
416 hose->first_busno = 0;
417 hose->last_busno = 0xff;
418
419 /* System memory space, window 0 256 MB non-prefetchable */
420 pci_set_region(hose->regions + 0,
421 PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
422 SZ_256M,
423 PCI_REGION_MEM);
424
425 /* System memory space, window 1 256 MB prefetchable */
426 pci_set_region(hose->regions + 1,
427 PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
428 SZ_256M,
429 PCI_REGION_MEM |
430 PCI_REGION_PREFETCH);
431
432 /* PCI I/O space */
433 pci_set_region(hose->regions + 2,
434 0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
435 PCI_REGION_IO);
436
437 /* PCI Memory - config space */
438 pci_set_region(hose->regions + 3,
439 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
440 PCI_REGION_MEM);
441 /* PCI V3 regs */
442 pci_set_region(hose->regions + 4,
443 0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
444 PCI_REGION_MEM);
445
446 hose->region_count = 5;
447
448 pci_set_ops(hose,
449 pci_integrator_read_byte,
450 pci_integrator_read__word,
451 pci_integrator_read_dword,
452 pci_integrator_write_byte,
453 pci_integrator_write_word,
454 pci_integrator_write_dword);
455
456 pci_register_hose(hose);
457
458 pciauto_config_init(hose);
459 pciauto_config_device(hose, 0);
460
461 hose->last_busno = pci_hose_scan(hose);
462 }
463