1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Marvell / Cavium Inc. EVB CN7300 4 */ 5 6/dts-v1/; 7 8#include "mrvl,cn73xx.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 model = "cavium,ebb7304"; 13 compatible = "cavium,ebb7304"; 14 15 aliases { 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 serial0 = &uart0; 19 spi0 = &spi; 20 }; 21 22 regulators { 23 compatible = "simple-bus"; 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 /* Power on GPIO 8, active high */ 28 reg_mmc_3v3: regulator@0 { 29 compatible = "regulator-fixed"; 30 reg = <0>; 31 regulator-name = "mmc-3v3"; 32 regulator-min-microvolt = <3300000>; 33 regulator-max-microvolt = <3300000>; 34 gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; 35 enable-active-high; 36 }; 37 }; 38 39 chosen { 40 stdout-path = &uart0; 41 }; 42}; 43 44&bootbus { 45 /* 46 * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000) 47 * as the initial size is too small for the 8MiB flash device 48 */ 49 ranges = <0 0 0 0x1f400000 0xc00000>, 50 <1 0 0x10000 0x10000000 0>, 51 <2 0 0x10000 0x20000000 0>, 52 <3 0 0x10000 0x30000000 0>, 53 <4 0 0 0x1d020000 0x10000>, 54 <5 0 0x10000 0x50000000 0>, 55 <6 0 0x10000 0x60000000 0>, 56 <7 0 0x10000 0x70000000 0>; 57 58 cavium,cs-config@0 { 59 compatible = "cavium,octeon-3860-bootbus-config"; 60 cavium,cs-index = <0>; 61 cavium,t-adr = <10>; 62 cavium,t-ce = <50>; 63 cavium,t-oe = <50>; 64 cavium,t-we = <35>; 65 cavium,t-rd-hld = <25>; 66 cavium,t-wr-hld = <35>; 67 cavium,t-pause = <0>; 68 cavium,t-wait = <50>; 69 cavium,t-page = <30>; 70 cavium,t-rd-dly = <0>; 71 cavium,page-mode = <1>; 72 cavium,pages = <8>; 73 cavium,bus-width = <8>; 74 }; 75 76 cavium,cs-config@4 { 77 compatible = "cavium,octeon-3860-bootbus-config"; 78 cavium,cs-index = <4>; 79 cavium,t-adr = <10>; 80 cavium,t-ce = <10>; 81 cavium,t-oe = <160>; 82 cavium,t-we = <100>; 83 cavium,t-rd-hld = <10>; 84 cavium,t-wr-hld = <0>; 85 cavium,t-pause = <50>; 86 cavium,t-wait = <50>; 87 cavium,t-page = <10>; 88 cavium,t-rd-dly = <10>; 89 cavium,pages = <0>; 90 cavium,bus-width = <8>; 91 }; 92 93 flash0: nor@0,0 { 94 compatible = "cfi-flash"; 95 reg = <0 0 0x800000>; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 partition@0 { 99 label = "bootloader"; 100 reg = <0 0x340000>; 101 read-only; 102 }; 103 partition@300000 { 104 label = "storage"; 105 reg = <0x340000 0x4be000>; 106 }; 107 partition@7fe000 { 108 label = "environment"; 109 reg = <0x7fe000 0x2000>; 110 read-only; 111 }; 112 }; 113}; 114 115&i2c0 { 116 u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ 117 clock-frequency = <100000>; 118 119 rtc@68 { 120 compatible = "dallas,ds1337"; 121 reg = <0x68>; 122 }; 123 124 tlv-eeprom@56 { 125 compatible = "atmel,24c256", "microchip,24lc256"; 126 reg = <0x56>; 127 pagesize = <64>; 128 }; 129}; 130 131&i2c1 { 132 u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ 133 clock-frequency = <100000>; 134}; 135 136&spi { 137 flash@0 { 138 compatible = "micron,n25q128a11", "jedec,spi-nor"; 139 spi-max-frequency = <2000000>; 140 reg = <0>; 141 }; 142}; 143 144/* USB 0 */ 145&usb0 { 146 status = "okay"; 147 /* 148 * Power is specified by three parts: 149 * 1) GPIO handle (must be &gpio) 150 * 2) GPIO pin number 151 * 3) Active high (0) or active low (1) 152 */ 153 power = <&gpio 20 0>; 154}; 155 156/* USB 1 */ 157&usb1 { 158 status = "okay"; 159 /* 160 * Power is specified by three parts: 161 * 1) GPIO handle (must be &gpio) 162 * 2) GPIO pin number 163 * 3) Active high (0) or active low (1) 164 */ 165 power = <&gpio 21 0>; 166}; 167 168&mmc { 169 status = "okay"; 170 171 /* The board has two MMC slots 172 * If both are occupied, the speed must be reduced, 173 * as extra data-line load increases slew time, 174 * and dat-skew adjustment does not help significantly. 175 */ 176 mmc0: mmc-slot@0 { 177 compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot"; 178 reg = <0>; 179 vqmmc-supply = <®_mmc_3v3>; 180 voltage-ranges = <3300 3300>; 181 //spi-max-frequency = <52000000>; // just one 182 spi-max-frequency = <37000000>; // both slots 183 /* bus width can be 1, 4 or 8 */ 184 bus-width = <8>; /* new std property */ 185 cavium,bus-max-width = <8>; /* custom property */ 186 wp-gpios = <&gpio 22 0>; /* active high */ 187 cd-gpios = <&gpio 23 1>; /* active low */ 188 }; 189 190 mmc1: mmc-slot@1 { 191 compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot"; 192 reg = <1>; 193 vqmmc-supply = <®_mmc_3v3>; 194 voltage-ranges = <3300 3300>; 195 //spi-max-frequency = <52000000>; // just one 196 spi-max-frequency = <37000000>; // both slots 197 /* bus width can be 1, 4 or 8 */ 198 bus-width = <8>; /* new std property */ 199 cavium,bus-max-width = <8>; /* custom property */ 200 wp-gpios = <&gpio 24 0>; /* active high */ 201 cd-gpios = <&gpio 25 1>; /* active low */ 202 }; 203}; 204