1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 *
7 * Author: Tor Krill tor@excito.com
8 */
9
10 #include <common.h>
11 #include <env.h>
12 #include <log.h>
13 #include <pci.h>
14 #include <usb.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <linux/delay.h>
18 #include <usb/ehci-ci.h>
19 #include <hwconfig.h>
20 #include <fsl_usb.h>
21 #include <fdt_support.h>
22 #include <dm.h>
23
24 #include "ehci.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
29 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
30 #endif
31
32 #if CONFIG_IS_ENABLED(DM_USB)
33 struct ehci_fsl_priv {
34 struct ehci_ctrl ehci;
35 fdt_addr_t hcd_base;
36 char *phy_type;
37 };
38 #endif
39
40 static void set_txfifothresh(struct usb_ehci *, u32);
41 #if CONFIG_IS_ENABLED(DM_USB)
42 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
43 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
44 #else
45 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
46 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
47 #endif
48
49 /* Check USB PHY clock valid */
usb_phy_clk_valid(struct usb_ehci * ehci)50 static int usb_phy_clk_valid(struct usb_ehci *ehci)
51 {
52 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
53 in_be32(&ehci->prictrl))) {
54 printf("USB PHY clock invalid!\n");
55 return 0;
56 } else {
57 return 1;
58 }
59 }
60
61 #if CONFIG_IS_ENABLED(DM_USB)
ehci_fsl_of_to_plat(struct udevice * dev)62 static int ehci_fsl_of_to_plat(struct udevice *dev)
63 {
64 struct ehci_fsl_priv *priv = dev_get_priv(dev);
65 const void *prop;
66
67 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
68 NULL);
69 if (prop) {
70 priv->phy_type = (char *)prop;
71 debug("phy_type %s\n", priv->phy_type);
72 }
73
74 return 0;
75 }
76
ehci_fsl_init_after_reset(struct ehci_ctrl * ctrl)77 static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
78 {
79 struct usb_ehci *ehci = NULL;
80 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
81 ehci);
82 #ifdef CONFIG_PPC
83 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
84 #else
85 ehci = (struct usb_ehci *)priv->hcd_base;
86 #endif
87
88 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
89 return -ENXIO;
90
91 return 0;
92 }
93
94 static const struct ehci_ops fsl_ehci_ops = {
95 .init_after_reset = ehci_fsl_init_after_reset,
96 };
97
ehci_fsl_probe(struct udevice * dev)98 static int ehci_fsl_probe(struct udevice *dev)
99 {
100 struct ehci_fsl_priv *priv = dev_get_priv(dev);
101 struct usb_ehci *ehci = NULL;
102 struct ehci_hccr *hccr;
103 struct ehci_hcor *hcor;
104 struct ehci_ctrl *ehci_ctrl = &priv->ehci;
105
106 /*
107 * Get the base address for EHCI controller from the device node
108 */
109 priv->hcd_base = dev_read_addr(dev);
110 if (priv->hcd_base == FDT_ADDR_T_NONE) {
111 debug("Can't get the EHCI register base address\n");
112 return -ENXIO;
113 }
114 #ifdef CONFIG_PPC
115 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
116 #else
117 ehci = (struct usb_ehci *)priv->hcd_base;
118 #endif
119 hccr = (struct ehci_hccr *)(&ehci->caplength);
120 hcor = (struct ehci_hcor *)
121 ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
122
123 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
124
125 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
126 return -ENXIO;
127
128 debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
129 (void *)hccr, (void *)hcor,
130 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
131
132 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
133 }
134
135 static const struct udevice_id ehci_usb_ids[] = {
136 { .compatible = "fsl-usb2-mph", },
137 { .compatible = "fsl-usb2-dr", },
138 { }
139 };
140
141 U_BOOT_DRIVER(ehci_fsl) = {
142 .name = "ehci_fsl",
143 .id = UCLASS_USB,
144 .of_match = ehci_usb_ids,
145 .of_to_plat = ehci_fsl_of_to_plat,
146 .probe = ehci_fsl_probe,
147 .remove = ehci_deregister,
148 .ops = &ehci_usb_ops,
149 .plat_auto = sizeof(struct usb_plat),
150 .priv_auto = sizeof(struct ehci_fsl_priv),
151 .flags = DM_FLAG_ALLOC_PRIV_DMA,
152 };
153 #else
154 /*
155 * Create the appropriate control structures to manage
156 * a new EHCI host controller.
157 *
158 * Excerpts from linux ehci fsl driver.
159 */
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)160 int ehci_hcd_init(int index, enum usb_init_type init,
161 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
162 {
163 struct ehci_ctrl *ehci_ctrl = container_of(hccr,
164 struct ehci_ctrl, hccr);
165 struct usb_ehci *ehci = NULL;
166
167 switch (index) {
168 case 0:
169 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
170 break;
171 case 1:
172 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
173 break;
174 default:
175 printf("ERROR: wrong controller index!!\n");
176 return -EINVAL;
177 };
178
179 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
180 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
181 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
182
183 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
184
185 return ehci_fsl_init(index, ehci, *hccr, *hcor);
186 }
187
188 /*
189 * Destroy the appropriate control structures corresponding
190 * the the EHCI host controller.
191 */
ehci_hcd_stop(int index)192 int ehci_hcd_stop(int index)
193 {
194 return 0;
195 }
196 #endif
197
198 #if CONFIG_IS_ENABLED(DM_USB)
ehci_fsl_init(struct ehci_fsl_priv * priv,struct usb_ehci * ehci,struct ehci_hccr * hccr,struct ehci_hcor * hcor)199 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
200 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
201 #else
202 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
203 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
204 #endif
205 {
206 const char *phy_type = NULL;
207 #if !CONFIG_IS_ENABLED(DM_USB)
208 size_t len;
209 char current_usb_controller[5];
210 #endif
211 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
212 char usb_phy[5];
213
214 usb_phy[0] = '\0';
215 #endif
216 if (has_erratum_a007075()) {
217 /*
218 * A 5ms delay is needed after applying soft-reset to the
219 * controller to let external ULPI phy come out of reset.
220 * This delay needs to be added before re-initializing
221 * the controller after soft-resetting completes
222 */
223 mdelay(5);
224 }
225
226 /* Set to Host mode */
227 setbits_le32(&ehci->usbmode, CM_HOST);
228
229 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
230 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
231
232 /* Init phy */
233 #if CONFIG_IS_ENABLED(DM_USB)
234 if (priv->phy_type)
235 phy_type = priv->phy_type;
236 #else
237 memset(current_usb_controller, '\0', 5);
238 snprintf(current_usb_controller, sizeof(current_usb_controller),
239 "usb%d", index+1);
240
241 if (hwconfig_sub(current_usb_controller, "phy_type"))
242 phy_type = hwconfig_subarg(current_usb_controller,
243 "phy_type", &len);
244 #endif
245 else
246 phy_type = env_get("usb_phy_type");
247
248 if (!phy_type) {
249 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
250 /* if none specified assume internal UTMI */
251 strcpy(usb_phy, "utmi");
252 phy_type = usb_phy;
253 #else
254 printf("WARNING: USB phy type not defined !!\n");
255 return -1;
256 #endif
257 }
258
259 if (!strncmp(phy_type, "utmi", 4)) {
260 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
261 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
262 PHY_CLK_SEL_UTMI);
263 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
264 UTMI_PHY_EN);
265 udelay(1000); /* delay required for PHY Clk to appear */
266 #endif
267 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
268 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
269 USB_EN);
270 } else {
271 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
272 PHY_CLK_SEL_ULPI);
273 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
274 CONTROL_REGISTER_W1C_MASK, USB_EN);
275 udelay(1000); /* delay required for PHY Clk to appear */
276 if (!usb_phy_clk_valid(ehci))
277 return -EINVAL;
278 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
279 }
280
281 out_be32(&ehci->prictrl, 0x0000000c);
282 out_be32(&ehci->age_cnt_limit, 0x00000040);
283 out_be32(&ehci->sictrl, 0x00000001);
284
285 in_le32(&ehci->usbmode);
286
287 if (has_erratum_a007798())
288 set_txfifothresh(ehci, TXFIFOTHRESH);
289
290 if (has_erratum_a004477()) {
291 /*
292 * When reset is issued while any ULPI transaction is ongoing
293 * then it may result to corruption of ULPI Function Control
294 * Register which eventually causes phy clock to enter low
295 * power mode which stops the clock. Thus delay is required
296 * before reset to let ongoing ULPI transaction complete.
297 */
298 udelay(1);
299 }
300 return 0;
301 }
302
303 /*
304 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
305 * to counter DDR latencies in writing data into Tx buffer.
306 * This prevents Tx buffer from getting underrun
307 */
set_txfifothresh(struct usb_ehci * ehci,u32 txfifo_thresh)308 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
309 {
310 u32 cmd;
311 cmd = ehci_readl(&ehci->txfilltuning);
312 cmd &= ~TXFIFO_THRESH_MASK;
313 cmd |= TXFIFO_THRESH(txfifo_thresh);
314 ehci_writel(&ehci->txfilltuning, cmd);
315 }
316