1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2015,2016 Freescale Semiconductor, Inc.
4  *
5  * FSL USB HOST xHCI Controller
6  *
7  * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
8  */
9 
10 #include <common.h>
11 #include <log.h>
12 #include <usb.h>
13 #include <linux/errno.h>
14 #include <linux/compat.h>
15 #include <linux/usb/xhci-fsl.h>
16 #include <linux/usb/dwc3.h>
17 #include <usb/xhci.h>
18 #include <fsl_errata.h>
19 #include <fsl_usb.h>
20 #include <dm.h>
21 
22 /* Declare global data pointer */
23 #if !CONFIG_IS_ENABLED(DM_USB)
24 static struct fsl_xhci fsl_xhci;
25 unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
26 #else
27 struct xhci_fsl_priv {
28 	struct xhci_ctrl xhci;
29 	fdt_addr_t hcd_base;
30 	struct fsl_xhci ctx;
31 };
32 #endif
33 
__board_usb_init(int index,enum usb_init_type init)34 __weak int __board_usb_init(int index, enum usb_init_type init)
35 {
36 	return 0;
37 }
38 
erratum_a008751(void)39 static int erratum_a008751(void)
40 {
41 #if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
42 					defined(CONFIG_TARGET_LS2080AQDS)
43 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
44 	writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
45 	return 0;
46 #endif
47 	return 1;
48 }
49 
fsl_apply_xhci_errata(void)50 static void fsl_apply_xhci_errata(void)
51 {
52 	int ret;
53 	if (has_erratum_a008751()) {
54 		ret = erratum_a008751();
55 		if (ret != 0)
56 			puts("Failed to apply erratum a008751\n");
57 	}
58 }
59 
fsl_xhci_set_beat_burst_length(struct dwc3 * dwc3_reg)60 static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
61 {
62 	clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
63 			USB3_ENABLE_BEAT_BURST);
64 	setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
65 }
66 
fsl_xhci_core_init(struct fsl_xhci * fsl_xhci)67 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
68 {
69 	int ret = 0;
70 
71 	ret = dwc3_core_init(fsl_xhci->dwc3_reg);
72 	if (ret) {
73 		debug("%s:failed to initialize core\n", __func__);
74 		return ret;
75 	}
76 
77 	/* We are hard-coding DWC3 core to Host Mode */
78 	dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
79 
80 	/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
81 	dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
82 
83 	/* Change beat burst and outstanding pipelined transfers requests */
84 	fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
85 
86 	/*
87 	 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
88 	 * reliably support Rx Detect in P3 mode(P3 is the default
89 	 * setting). Therefore, some USB3.0 devices may not be detected
90 	 * reliably in Super Speed mode. So, USB controller to configure
91 	 * USB in P2 mode whenever the Receive Detect feature is required.
92 	 * whenever the Receive Detect feature is required.
93 	 */
94 	if (has_erratum_a010151())
95 		clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
96 				DWC3_GUSB3PIPECTL_DISRXDETP3,
97 				DWC3_GUSB3PIPECTL_DISRXDETP3);
98 
99 	return ret;
100 }
101 
fsl_xhci_core_exit(struct fsl_xhci * fsl_xhci)102 static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
103 {
104 	/*
105 	 * Currently fsl socs do not support PHY shutdown from
106 	 * sw. But this support may be added in future socs.
107 	 */
108 	return 0;
109 }
110 
111 #if CONFIG_IS_ENABLED(DM_USB)
xhci_fsl_probe(struct udevice * dev)112 static int xhci_fsl_probe(struct udevice *dev)
113 {
114 	struct xhci_fsl_priv *priv = dev_get_priv(dev);
115 	struct xhci_hccr *hccr;
116 	struct xhci_hcor *hcor;
117 
118 	int ret = 0;
119 
120 	/*
121 	 * Get the base address for XHCI controller from the device node
122 	 */
123 	priv->hcd_base = dev_read_addr(dev);
124 	if (priv->hcd_base == FDT_ADDR_T_NONE) {
125 		debug("Can't get the XHCI register base address\n");
126 		return -ENXIO;
127 	}
128 	priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;
129 	priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +
130 			  DWC3_REG_OFFSET);
131 
132 	fsl_apply_xhci_errata();
133 
134 	ret = fsl_xhci_core_init(&priv->ctx);
135 	if (ret < 0) {
136 		puts("Failed to initialize xhci\n");
137 		return ret;
138 	}
139 
140 	hccr = (struct xhci_hccr *)(priv->ctx.hcd);
141 	hcor = (struct xhci_hcor *)((uintptr_t) hccr
142 				+ HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
143 
144 	debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",
145 	      (uintptr_t)hccr, (uintptr_t)hcor,
146 	      (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
147 
148 	return xhci_register(dev, hccr, hcor);
149 }
150 
xhci_fsl_remove(struct udevice * dev)151 static int xhci_fsl_remove(struct udevice *dev)
152 {
153 	struct xhci_fsl_priv *priv = dev_get_priv(dev);
154 
155 	fsl_xhci_core_exit(&priv->ctx);
156 
157 	return xhci_deregister(dev);
158 }
159 
160 static const struct udevice_id xhci_usb_ids[] = {
161 	{ .compatible = "fsl,layerscape-dwc3", },
162 	{ }
163 };
164 
165 U_BOOT_DRIVER(xhci_fsl) = {
166 	.name	= "xhci_fsl",
167 	.id	= UCLASS_USB,
168 	.of_match = xhci_usb_ids,
169 	.probe = xhci_fsl_probe,
170 	.remove = xhci_fsl_remove,
171 	.ops	= &xhci_usb_ops,
172 	.plat_auto	= sizeof(struct usb_plat),
173 	.priv_auto	= sizeof(struct xhci_fsl_priv),
174 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
175 };
176 #else
xhci_hcd_init(int index,struct xhci_hccr ** hccr,struct xhci_hcor ** hcor)177 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
178 {
179 	struct fsl_xhci *ctx = &fsl_xhci;
180 	int ret = 0;
181 
182 	ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
183 	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
184 
185 	ret = board_usb_init(index, USB_INIT_HOST);
186 	if (ret != 0) {
187 		puts("Failed to initialize board for USB\n");
188 		return ret;
189 	}
190 
191 	fsl_apply_xhci_errata();
192 
193 	ret = fsl_xhci_core_init(ctx);
194 	if (ret < 0) {
195 		puts("Failed to initialize xhci\n");
196 		return ret;
197 	}
198 
199 	*hccr = (struct xhci_hccr *)ctx->hcd;
200 	*hcor = (struct xhci_hcor *)((uintptr_t) *hccr
201 				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
202 
203 	debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
204 	      (uintptr_t)*hccr, (uintptr_t)*hcor,
205 	      (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
206 
207 	return ret;
208 }
209 
xhci_hcd_stop(int index)210 void xhci_hcd_stop(int index)
211 {
212 	struct fsl_xhci *ctx = &fsl_xhci;
213 
214 	fsl_xhci_core_exit(ctx);
215 }
216 #endif
217