1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2008,2010 Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
7 */
8
9 #ifndef _MMC_H_
10 #define _MMC_H_
11
12 #include <linux/bitops.h>
13 #include <linux/list.h>
14 #include <linux/sizes.h>
15 #include <linux/compiler.h>
16 #include <linux/dma-direction.h>
17 #include <part.h>
18
19 struct bd_info;
20
21 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
22 #define MMC_SUPPORTS_TUNING
23 #endif
24 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
25 #define MMC_SUPPORTS_TUNING
26 #endif
27
28 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
29 #define SD_VERSION_SD (1U << 31)
30 #define MMC_VERSION_MMC (1U << 30)
31
32 #define MAKE_SDMMC_VERSION(a, b, c) \
33 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
34 #define MAKE_SD_VERSION(a, b, c) \
35 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
36 #define MAKE_MMC_VERSION(a, b, c) \
37 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
38
39 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
40 (((u32)(x) >> 16) & 0xff)
41 #define EXTRACT_SDMMC_MINOR_VERSION(x) \
42 (((u32)(x) >> 8) & 0xff)
43 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
44 ((u32)(x) & 0xff)
45
46 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
47 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
48 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
49 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
50
51 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
52 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
53 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
54 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
55 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
56 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
57 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
58 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
59 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
60 #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
61 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
62 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
63 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
64 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
65
66 #define MMC_CAP(mode) (1 << mode)
67 #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
68 #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
69 #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
70 #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
71 #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
72 #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
73
74 #define MMC_CAP_NONREMOVABLE BIT(14)
75 #define MMC_CAP_NEEDS_POLL BIT(15)
76 #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
77
78 #define MMC_MODE_8BIT BIT(30)
79 #define MMC_MODE_4BIT BIT(29)
80 #define MMC_MODE_1BIT BIT(28)
81 #define MMC_MODE_SPI BIT(27)
82
83
84 #define SD_DATA_4BIT 0x00040000
85
86 #define IS_SD(x) ((x)->version & SD_VERSION_SD)
87 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
88
89 #define MMC_DATA_READ 1
90 #define MMC_DATA_WRITE 2
91
92 #define MMC_CMD_GO_IDLE_STATE 0
93 #define MMC_CMD_SEND_OP_COND 1
94 #define MMC_CMD_ALL_SEND_CID 2
95 #define MMC_CMD_SET_RELATIVE_ADDR 3
96 #define MMC_CMD_SET_DSR 4
97 #define MMC_CMD_SWITCH 6
98 #define MMC_CMD_SELECT_CARD 7
99 #define MMC_CMD_SEND_EXT_CSD 8
100 #define MMC_CMD_SEND_CSD 9
101 #define MMC_CMD_SEND_CID 10
102 #define MMC_CMD_STOP_TRANSMISSION 12
103 #define MMC_CMD_SEND_STATUS 13
104 #define MMC_CMD_SET_BLOCKLEN 16
105 #define MMC_CMD_READ_SINGLE_BLOCK 17
106 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
107 #define MMC_CMD_SEND_TUNING_BLOCK 19
108 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
109 #define MMC_CMD_SET_BLOCK_COUNT 23
110 #define MMC_CMD_WRITE_SINGLE_BLOCK 24
111 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
112 #define MMC_CMD_ERASE_GROUP_START 35
113 #define MMC_CMD_ERASE_GROUP_END 36
114 #define MMC_CMD_ERASE 38
115 #define MMC_CMD_APP_CMD 55
116 #define MMC_CMD_SPI_READ_OCR 58
117 #define MMC_CMD_SPI_CRC_ON_OFF 59
118 #define MMC_CMD_RES_MAN 62
119
120 #define MMC_CMD62_ARG1 0xefac62ec
121 #define MMC_CMD62_ARG2 0xcbaea7
122
123
124 #define SD_CMD_SEND_RELATIVE_ADDR 3
125 #define SD_CMD_SWITCH_FUNC 6
126 #define SD_CMD_SEND_IF_COND 8
127 #define SD_CMD_SWITCH_UHS18V 11
128
129 #define SD_CMD_APP_SET_BUS_WIDTH 6
130 #define SD_CMD_APP_SD_STATUS 13
131 #define SD_CMD_ERASE_WR_BLK_START 32
132 #define SD_CMD_ERASE_WR_BLK_END 33
133 #define SD_CMD_APP_SEND_OP_COND 41
134 #define SD_CMD_APP_SEND_SCR 51
135
mmc_is_tuning_cmd(uint cmdidx)136 static inline bool mmc_is_tuning_cmd(uint cmdidx)
137 {
138 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
139 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
140 return true;
141 return false;
142 }
143
144 /* SCR definitions in different words */
145 #define SD_HIGHSPEED_BUSY 0x00020000
146 #define SD_HIGHSPEED_SUPPORTED 0x00020000
147
148 #define UHS_SDR12_BUS_SPEED 0
149 #define HIGH_SPEED_BUS_SPEED 1
150 #define UHS_SDR25_BUS_SPEED 1
151 #define UHS_SDR50_BUS_SPEED 2
152 #define UHS_SDR104_BUS_SPEED 3
153 #define UHS_DDR50_BUS_SPEED 4
154
155 #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
156 #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
157 #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
158 #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
159 #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
160
161 #define OCR_BUSY 0x80000000
162 #define OCR_HCS 0x40000000
163 #define OCR_S18R 0x1000000
164 #define OCR_VOLTAGE_MASK 0x007FFF80
165 #define OCR_ACCESS_MODE 0x60000000
166
167 #define MMC_ERASE_ARG 0x00000000
168 #define MMC_SECURE_ERASE_ARG 0x80000000
169 #define MMC_TRIM_ARG 0x00000001
170 #define MMC_DISCARD_ARG 0x00000003
171 #define MMC_SECURE_TRIM1_ARG 0x80000001
172 #define MMC_SECURE_TRIM2_ARG 0x80008000
173
174 #define MMC_STATUS_MASK (~0x0206BF7F)
175 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
176 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
177 #define MMC_STATUS_CURR_STATE (0xf << 9)
178 #define MMC_STATUS_ERROR (1 << 19)
179
180 #define MMC_STATE_PRG (7 << 9)
181 #define MMC_STATE_TRANS (4 << 9)
182
183 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
184 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
185 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
186 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
187 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
188 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
189 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
190 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
191 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
192 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
193 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
194 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
195 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
196 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
197 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
198 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
199 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
200
201 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
202 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
203 addressed by index which are
204 1 in value field */
205 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
206 addressed by index, which are
207 1 in value field */
208 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
209
210 #define SD_SWITCH_CHECK 0
211 #define SD_SWITCH_SWITCH 1
212
213 /*
214 * EXT_CSD fields
215 */
216 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
217 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
218 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
219 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
220 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
221 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
222 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
223 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
224 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
225 #define EXT_CSD_WR_REL_PARAM 166 /* R */
226 #define EXT_CSD_WR_REL_SET 167 /* R/W */
227 #define EXT_CSD_RPMB_MULT 168 /* RO */
228 #define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */
229 #define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
230 #define EXT_CSD_BOOT_WP_STATUS 174 /* R */
231 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
232 #define EXT_CSD_BOOT_BUS_WIDTH 177
233 #define EXT_CSD_PART_CONF 179 /* R/W */
234 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
235 #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
236 #define EXT_CSD_HS_TIMING 185 /* R/W */
237 #define EXT_CSD_REV 192 /* RO */
238 #define EXT_CSD_CARD_TYPE 196 /* RO */
239 #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
240 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
241 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
242 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
243 #define EXT_CSD_BOOT_MULT 226 /* RO */
244 #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
245 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
246
247 /*
248 * EXT_CSD field definitions
249 */
250
251 #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
252 #define EXT_CSD_CMD_SET_SECURE (1 << 1)
253 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
254
255 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
256 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
257 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
258 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
259 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
260 | EXT_CSD_CARD_TYPE_DDR_1_2V)
261
262 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
263 /* SDR mode @1.8V I/O */
264 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
265 /* SDR mode @1.2V I/O */
266 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
267 EXT_CSD_CARD_TYPE_HS200_1_2V)
268 #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
269 #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
270 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
271 EXT_CSD_CARD_TYPE_HS400_1_2V)
272
273 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
274 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
275 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
276 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
277 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
278 #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
279 #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
280
281 #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
282 #define EXT_CSD_TIMING_HS 1 /* HS */
283 #define EXT_CSD_TIMING_HS200 2 /* HS200 */
284 #define EXT_CSD_TIMING_HS400 3 /* HS400 */
285 #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
286
287 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
288 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
289 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
290 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
291
292 #define EXT_CSD_BOOT_ACK(x) (x << 6)
293 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
294 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
295
296 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
297 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
298 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
299
300 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
301 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
302 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
303
304 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
305
306 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
307 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
308
309 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
310
311 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
312 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
313
314 #define R1_ILLEGAL_COMMAND (1 << 22)
315 #define R1_APP_CMD (1 << 5)
316
317 #define MMC_RSP_PRESENT (1 << 0)
318 #define MMC_RSP_136 (1 << 1) /* 136 bit response */
319 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
320 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
321 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
322
323 #define MMC_RSP_NONE (0)
324 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
325 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
326 MMC_RSP_BUSY)
327 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
328 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
329 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
330 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
331 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
332 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
333
334 #define MMCPART_NOAVAILABLE (0xff)
335 #define PART_ACCESS_MASK (0x7)
336 #define PART_SUPPORT (0x1)
337 #define ENHNCD_SUPPORT (0x2)
338 #define PART_ENH_ATTRIB (0x1f)
339
340 #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
341 #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
342 #define MMC_QUIRK_RETRY_APP_CMD BIT(2)
343
344 enum mmc_voltage {
345 MMC_SIGNAL_VOLTAGE_000 = 0,
346 MMC_SIGNAL_VOLTAGE_120 = 1,
347 MMC_SIGNAL_VOLTAGE_180 = 2,
348 MMC_SIGNAL_VOLTAGE_330 = 4,
349 };
350
351 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
352 MMC_SIGNAL_VOLTAGE_180 |\
353 MMC_SIGNAL_VOLTAGE_330)
354
355 /* Maximum block size for MMC */
356 #define MMC_MAX_BLOCK_LEN 512
357
358 /* The number of MMC physical partitions. These consist of:
359 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
360 */
361 #define MMC_NUM_BOOT_PARTITION 2
362 #define MMC_PART_RPMB 3 /* RPMB partition number */
363
364 /* timing specification used */
365 #define MMC_TIMING_LEGACY 0
366 #define MMC_TIMING_MMC_HS 1
367 #define MMC_TIMING_SD_HS 2
368 #define MMC_TIMING_UHS_SDR12 3
369 #define MMC_TIMING_UHS_SDR25 4
370 #define MMC_TIMING_UHS_SDR50 5
371 #define MMC_TIMING_UHS_SDR104 6
372 #define MMC_TIMING_UHS_DDR50 7
373 #define MMC_TIMING_MMC_DDR52 8
374 #define MMC_TIMING_MMC_HS200 9
375 #define MMC_TIMING_MMC_HS400 10
376
377 /* Driver model support */
378
379 /**
380 * struct mmc_uclass_priv - Holds information about a device used by the uclass
381 */
382 struct mmc_uclass_priv {
383 struct mmc *mmc;
384 };
385
386 /**
387 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
388 *
389 * Provided that the device is already probed and ready for use, this value
390 * will be available.
391 *
392 * @dev: Device
393 * @return associated mmc struct pointer if available, else NULL
394 */
395 struct mmc *mmc_get_mmc_dev(const struct udevice *dev);
396
397 /* End of driver model support */
398
399 struct mmc_cid {
400 unsigned long psn;
401 unsigned short oid;
402 unsigned char mid;
403 unsigned char prv;
404 unsigned char mdt;
405 char pnm[7];
406 };
407
408 struct mmc_cmd {
409 ushort cmdidx;
410 uint resp_type;
411 uint cmdarg;
412 uint response[4];
413 };
414
415 struct mmc_data {
416 union {
417 char *dest;
418 const char *src; /* src buffers don't get written to */
419 };
420 uint flags;
421 uint blocks;
422 uint blocksize;
423 };
424
425 /* forward decl. */
426 struct mmc;
427
428 #if CONFIG_IS_ENABLED(DM_MMC)
429 struct dm_mmc_ops {
430 /**
431 * deferred_probe() - Some configurations that need to be deferred
432 * to just before enumerating the device
433 *
434 * @dev: Device to init
435 * @return 0 if Ok, -ve if error
436 */
437 int (*deferred_probe)(struct udevice *dev);
438 /**
439 * reinit() - Re-initialization to clear old configuration for
440 * mmc rescan.
441 *
442 * @dev: Device to reinit
443 * @return 0 if Ok, -ve if error
444 */
445 int (*reinit)(struct udevice *dev);
446 /**
447 * send_cmd() - Send a command to the MMC device
448 *
449 * @dev: Device to receive the command
450 * @cmd: Command to send
451 * @data: Additional data to send/receive
452 * @return 0 if OK, -ve on error
453 */
454 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
455 struct mmc_data *data);
456
457 /**
458 * set_ios() - Set the I/O speed/width for an MMC device
459 *
460 * @dev: Device to update
461 * @return 0 if OK, -ve on error
462 */
463 int (*set_ios)(struct udevice *dev);
464
465 /**
466 * get_cd() - See whether a card is present
467 *
468 * @dev: Device to check
469 * @return 0 if not present, 1 if present, -ve on error
470 */
471 int (*get_cd)(struct udevice *dev);
472
473 /**
474 * get_wp() - See whether a card has write-protect enabled
475 *
476 * @dev: Device to check
477 * @return 0 if write-enabled, 1 if write-protected, -ve on error
478 */
479 int (*get_wp)(struct udevice *dev);
480
481 #ifdef MMC_SUPPORTS_TUNING
482 /**
483 * execute_tuning() - Start the tuning process
484 *
485 * @dev: Device to start the tuning
486 * @opcode: Command opcode to send
487 * @return 0 if OK, -ve on error
488 */
489 int (*execute_tuning)(struct udevice *dev, uint opcode);
490 #endif
491
492 /**
493 * wait_dat0() - wait until dat0 is in the target state
494 * (CLK must be running during the wait)
495 *
496 * @dev: Device to check
497 * @state: target state
498 * @timeout_us: timeout in us
499 * @return 0 if dat0 is in the target state, -ve on error
500 */
501 int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
502
503 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
504 /* set_enhanced_strobe() - set HS400 enhanced strobe */
505 int (*set_enhanced_strobe)(struct udevice *dev);
506 #endif
507
508 /**
509 * host_power_cycle - host specific tasks in power cycle sequence
510 * Called between mmc_power_off() and
511 * mmc_power_on()
512 *
513 * @dev: Device to check
514 * @return 0 if not present, 1 if present, -ve on error
515 */
516 int (*host_power_cycle)(struct udevice *dev);
517
518 /**
519 * get_b_max - get maximum length of single transfer
520 * Called before reading blocks from the card,
521 * useful for system which have e.g. DMA limits
522 * on various memory ranges.
523 *
524 * @dev: Device to check
525 * @dst: Destination buffer in memory
526 * @blkcnt: Total number of blocks in this transfer
527 * @return maximum number of blocks for this transfer
528 */
529 int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
530
531 /**
532 * hs400_prepare_ddr - prepare to switch to DDR mode
533 *
534 * @dev: Device to check
535 * @return 0 if success, -ve on error
536 */
537 int (*hs400_prepare_ddr)(struct udevice *dev);
538 };
539
540 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
541
542 /* Transition functions for compatibility */
543 int mmc_set_ios(struct mmc *mmc);
544 int mmc_getcd(struct mmc *mmc);
545 int mmc_getwp(struct mmc *mmc);
546 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
547 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
548 int mmc_set_enhanced_strobe(struct mmc *mmc);
549 int mmc_host_power_cycle(struct mmc *mmc);
550 int mmc_deferred_probe(struct mmc *mmc);
551 int mmc_reinit(struct mmc *mmc);
552 int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
553 int mmc_hs400_prepare_ddr(struct mmc *mmc);
554 #else
555 struct mmc_ops {
556 int (*send_cmd)(struct mmc *mmc,
557 struct mmc_cmd *cmd, struct mmc_data *data);
558 int (*set_ios)(struct mmc *mmc);
559 int (*init)(struct mmc *mmc);
560 int (*getcd)(struct mmc *mmc);
561 int (*getwp)(struct mmc *mmc);
562 int (*host_power_cycle)(struct mmc *mmc);
563 int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
564 };
565
mmc_hs400_prepare_ddr(struct mmc * mmc)566 static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
567 {
568 return 0;
569 }
570 #endif
571
572 struct mmc_config {
573 const char *name;
574 #if !CONFIG_IS_ENABLED(DM_MMC)
575 const struct mmc_ops *ops;
576 #endif
577 uint host_caps;
578 uint voltages;
579 uint f_min;
580 uint f_max;
581 uint b_max;
582 unsigned char part_type;
583 #ifdef CONFIG_MMC_PWRSEQ
584 struct udevice *pwr_dev;
585 #endif
586 };
587
588 struct sd_ssr {
589 unsigned int au; /* In sectors */
590 unsigned int erase_timeout; /* In milliseconds */
591 unsigned int erase_offset; /* In milliseconds */
592 };
593
594 enum bus_mode {
595 MMC_LEGACY,
596 MMC_HS,
597 SD_HS,
598 MMC_HS_52,
599 MMC_DDR_52,
600 UHS_SDR12,
601 UHS_SDR25,
602 UHS_SDR50,
603 UHS_DDR50,
604 UHS_SDR104,
605 MMC_HS_200,
606 MMC_HS_400,
607 MMC_HS_400_ES,
608 MMC_MODES_END
609 };
610
611 const char *mmc_mode_name(enum bus_mode mode);
612 void mmc_dump_capabilities(const char *text, uint caps);
613
mmc_is_mode_ddr(enum bus_mode mode)614 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
615 {
616 if (mode == MMC_DDR_52)
617 return true;
618 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
619 else if (mode == UHS_DDR50)
620 return true;
621 #endif
622 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
623 else if (mode == MMC_HS_400)
624 return true;
625 #endif
626 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
627 else if (mode == MMC_HS_400_ES)
628 return true;
629 #endif
630 else
631 return false;
632 }
633
634 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
635 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
636 MMC_CAP(UHS_DDR50))
637
supports_uhs(uint caps)638 static inline bool supports_uhs(uint caps)
639 {
640 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
641 return (caps & UHS_CAPS) ? true : false;
642 #else
643 return false;
644 #endif
645 }
646
647 /*
648 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
649 * with mmc_get_mmc_dev().
650 *
651 * TODO struct mmc should be in mmc_private but it's hard to fix right now
652 */
653 struct mmc {
654 #if !CONFIG_IS_ENABLED(BLK)
655 struct list_head link;
656 #endif
657 const struct mmc_config *cfg; /* provided configuration */
658 uint version;
659 void *priv;
660 uint has_init;
661 int high_capacity;
662 bool clk_disable; /* true if the clock can be turned off */
663 uint bus_width;
664 uint clock;
665 uint saved_clock;
666 enum mmc_voltage signal_voltage;
667 uint card_caps;
668 uint host_caps;
669 uint ocr;
670 uint dsr;
671 uint dsr_imp;
672 uint scr[2];
673 uint csd[4];
674 uint cid[4];
675 ushort rca;
676 u8 part_support;
677 u8 part_attr;
678 u8 wr_rel_set;
679 u8 part_config;
680 u8 gen_cmd6_time; /* units: 10 ms */
681 u8 part_switch_time; /* units: 10 ms */
682 uint tran_speed;
683 uint legacy_speed; /* speed for the legacy mode provided by the card */
684 uint read_bl_len;
685 #if CONFIG_IS_ENABLED(MMC_WRITE)
686 uint write_bl_len;
687 uint erase_grp_size; /* in 512-byte sectors */
688 #endif
689 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
690 uint hc_wp_grp_size; /* in 512-byte sectors */
691 #endif
692 #if CONFIG_IS_ENABLED(MMC_WRITE)
693 struct sd_ssr ssr; /* SD status register */
694 #endif
695 u64 capacity;
696 u64 capacity_user;
697 u64 capacity_boot;
698 u64 capacity_rpmb;
699 u64 capacity_gp[4];
700 #ifndef CONFIG_SPL_BUILD
701 u64 enh_user_start;
702 u64 enh_user_size;
703 #endif
704 #if !CONFIG_IS_ENABLED(BLK)
705 struct blk_desc block_dev;
706 #endif
707 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
708 char init_in_progress; /* 1 if we have done mmc_start_init() */
709 char preinit; /* start init as early as possible */
710 int ddr_mode;
711 #if CONFIG_IS_ENABLED(DM_MMC)
712 struct udevice *dev; /* Device for this MMC controller */
713 #if CONFIG_IS_ENABLED(DM_REGULATOR)
714 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
715 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
716 #endif
717 #endif
718 u8 *ext_csd;
719 u32 cardtype; /* cardtype read from the MMC */
720 enum mmc_voltage current_voltage;
721 enum bus_mode selected_mode; /* mode currently used */
722 enum bus_mode best_mode; /* best mode is the supported mode with the
723 * highest bandwidth. It may not always be the
724 * operating mode due to limitations when
725 * accessing the boot partitions
726 */
727 u32 quirks;
728 u8 hs400_tuning;
729 };
730
731 #if CONFIG_IS_ENABLED(DM_MMC)
732 #define mmc_to_dev(_mmc) _mmc->dev
733 #else
734 #define mmc_to_dev(_mmc) NULL
735 #endif
736
737 struct mmc_hwpart_conf {
738 struct {
739 uint enh_start; /* in 512-byte sectors */
740 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
741 unsigned wr_rel_change : 1;
742 unsigned wr_rel_set : 1;
743 } user;
744 struct {
745 uint size; /* in 512-byte sectors */
746 unsigned enhanced : 1;
747 unsigned wr_rel_change : 1;
748 unsigned wr_rel_set : 1;
749 } gp_part[4];
750 };
751
752 enum mmc_hwpart_conf_mode {
753 MMC_HWPART_CONF_CHECK,
754 MMC_HWPART_CONF_SET,
755 MMC_HWPART_CONF_COMPLETE,
756 };
757
758 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
759
760 /**
761 * mmc_bind() - Set up a new MMC device ready for probing
762 *
763 * A child block device is bound with the IF_TYPE_MMC interface type. This
764 * allows the device to be used with CONFIG_BLK
765 *
766 * @dev: MMC device to set up
767 * @mmc: MMC struct
768 * @cfg: MMC configuration
769 * @return 0 if OK, -ve on error
770 */
771 int mmc_bind(struct udevice *dev, struct mmc *mmc,
772 const struct mmc_config *cfg);
773 void mmc_destroy(struct mmc *mmc);
774
775 /**
776 * mmc_unbind() - Unbind a MMC device's child block device
777 *
778 * @dev: MMC device
779 * @return 0 if OK, -ve on error
780 */
781 int mmc_unbind(struct udevice *dev);
782 int mmc_initialize(struct bd_info *bis);
783 int mmc_init_device(int num);
784 int mmc_init(struct mmc *mmc);
785 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
786 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data);
787
788 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
789 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
790 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
791 int mmc_deinit(struct mmc *mmc);
792 #endif
793
794 /**
795 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
796 *
797 * @dev: MMC device
798 * @cfg: MMC configuration
799 * @return 0 if OK, -ve on error
800 */
801 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
802
803 #ifdef CONFIG_MMC_PWRSEQ
804 /**
805 * mmc_pwrseq_get_power() - get a power device from device tree
806 *
807 * @dev: MMC device
808 * @cfg: MMC configuration
809 * @return 0 if OK, -ve on error
810 */
811 int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg);
812 #endif
813
814 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
815
816 /**
817 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
818 *
819 * @voltage: The mmc_voltage to convert
820 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
821 */
822 int mmc_voltage_to_mv(enum mmc_voltage voltage);
823
824 /**
825 * mmc_set_clock() - change the bus clock
826 * @mmc: MMC struct
827 * @clock: bus frequency in Hz
828 * @disable: flag indicating if the clock must on or off
829 * @return 0 if OK, -ve on error
830 */
831 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
832
833 #define MMC_CLK_ENABLE false
834 #define MMC_CLK_DISABLE true
835
836 struct mmc *find_mmc_device(int dev_num);
837 int mmc_set_dev(int dev_num);
838 void print_mmc_devices(char separator);
839
840 /**
841 * get_mmc_num() - get the total MMC device number
842 *
843 * @return 0 if there is no MMC device, else the number of devices
844 */
845 int get_mmc_num(void);
846 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
847 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
848 enum mmc_hwpart_conf_mode mode);
849
850 #if !CONFIG_IS_ENABLED(DM_MMC)
851 int mmc_getcd(struct mmc *mmc);
852 int board_mmc_getcd(struct mmc *mmc);
853 int mmc_getwp(struct mmc *mmc);
854 int board_mmc_getwp(struct mmc *mmc);
855 #endif
856
857 int mmc_set_dsr(struct mmc *mmc, u16 val);
858 /* Function to change the size of boot partition and rpmb partitions */
859 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
860 unsigned long rpmbsize);
861 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
862 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
863 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
864 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
865 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
866 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
867 /* Functions to read / write the RPMB partition */
868 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
869 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
870 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
871 unsigned short cnt, unsigned char *key);
872 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
873 unsigned short cnt, unsigned char *key);
874
875 /**
876 * mmc_rpmb_route_frames() - route RPMB data frames
877 * @mmc Pointer to a MMC device struct
878 * @req Request data frames
879 * @reqlen Length of data frames in bytes
880 * @rsp Supplied buffer for response data frames
881 * @rsplen Length of supplied buffer for response data frames
882 *
883 * The RPMB data frames are routed to/from some external entity, for
884 * example a Trusted Exectuion Environment in an arm TrustZone protected
885 * secure world. It's expected that it's the external entity who is in
886 * control of the RPMB key.
887 *
888 * Returns 0 on success, < 0 on error.
889 */
890 int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
891 void *rsp, unsigned long rsplen);
892
893 #ifdef CONFIG_CMD_BKOPS_ENABLE
894 int mmc_set_bkops_enable(struct mmc *mmc);
895 #endif
896
897 /**
898 * Start device initialization and return immediately; it does not block on
899 * polling OCR (operation condition register) status. Useful for checking
900 * the presence of SD/eMMC when no card detect logic is available.
901 *
902 * @param mmc Pointer to a MMC device struct
903 * @return 0 on success, <0 on error.
904 */
905 int mmc_get_op_cond(struct mmc *mmc);
906
907 /**
908 * Start device initialization and return immediately; it does not block on
909 * polling OCR (operation condition register) status. Then you should call
910 * mmc_init, which would block on polling OCR status and complete the device
911 * initializatin.
912 *
913 * @param mmc Pointer to a MMC device struct
914 * @return 0 on success, <0 on error.
915 */
916 int mmc_start_init(struct mmc *mmc);
917
918 /**
919 * Set preinit flag of mmc device.
920 *
921 * This will cause the device to be pre-inited during mmc_initialize(),
922 * which may save boot time if the device is not accessed until later.
923 * Some eMMC devices take 200-300ms to init, but unfortunately they
924 * must be sent a series of commands to even get them to start preparing
925 * for operation.
926 *
927 * @param mmc Pointer to a MMC device struct
928 * @param preinit preinit flag value
929 */
930 void mmc_set_preinit(struct mmc *mmc, int preinit);
931
932 #ifdef CONFIG_MMC_SPI
933 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
934 #else
935 #define mmc_host_is_spi(mmc) 0
936 #endif
937
938 #define mmc_dev(x) ((x)->dev)
939
940 void board_mmc_power_init(void);
941 int board_mmc_init(struct bd_info *bis);
942 int cpu_mmc_init(struct bd_info *bis);
943 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
944 # ifdef CONFIG_SYS_MMC_ENV_PART
945 extern uint mmc_get_env_part(struct mmc *mmc);
946 # endif
947 int mmc_get_env_dev(void);
948
949 /* Minimum partition switch timeout in units of 10-milliseconds */
950 #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
951
952 /* Set block count limit because of 16 bit register limit on some hardware*/
953 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
954 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
955 #endif
956
957 /**
958 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
959 *
960 * @mmc: MMC device
961 * @return block device if found, else NULL
962 */
963 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
964
965 /**
966 * mmc_send_ext_csd() - read the extended CSD register
967 *
968 * @mmc: MMC device
969 * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
970 * the caller, e.g. using
971 * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
972 * Return: 0 for success
973 */
974 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
975
976 /**
977 * mmc_boot_wp() - power on write protect boot partitions
978 *
979 * The boot partitions are write protected until the next power cycle.
980 *
981 * Return: 0 for success
982 */
983 int mmc_boot_wp(struct mmc *mmc);
984
mmc_get_dma_dir(struct mmc_data * data)985 static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
986 {
987 return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
988 }
989
990 #endif /* _MMC_H_ */
991