1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (C) 2018 ROHM Semiconductors */ 3 4 #ifndef BD718XX_H_ 5 #define BD718XX_H_ 6 7 #define BD718XX_REGULATOR_DRIVER "bd718x7_regulator" 8 9 enum { 10 ROHM_CHIP_TYPE_BD71837 = 0, 11 ROHM_CHIP_TYPE_BD71847, 12 ROHM_CHIP_TYPE_BD70528, 13 ROHM_CHIP_TYPE_AMOUNT 14 }; 15 16 enum { 17 BD718XX_REV = 0x00, 18 BD718XX_SWRESET = 0x01, 19 BD718XX_I2C_DEV = 0x02, 20 BD718XX_PWRCTRL0 = 0x03, 21 BD718XX_PWRCTRL1 = 0x04, 22 BD718XX_BUCK1_CTRL = 0x05, 23 BD718XX_BUCK2_CTRL = 0x06, 24 BD71837_BUCK3_CTRL = 0x07, 25 BD71837_BUCK4_CTRL = 0x08, 26 BD718XX_1ST_NODVS_BUCK_CTRL = 0x09, 27 BD718XX_2ND_NODVS_BUCK_CTRL = 0x0a, 28 BD718XX_3RD_NODVS_BUCK_CTRL = 0x0b, 29 BD718XX_4TH_NODVS_BUCK_CTRL = 0x0c, 30 BD718XX_BUCK1_VOLT_RUN = 0x0d, 31 BD718XX_BUCK1_VOLT_IDLE = 0x0e, 32 BD718XX_BUCK1_VOLT_SUSP = 0x0f, 33 BD718XX_BUCK2_VOLT_RUN = 0x10, 34 BD718XX_BUCK2_VOLT_IDLE = 0x11, 35 BD71837_BUCK3_VOLT_RUN = 0x12, 36 BD71837_BUCK4_VOLT_RUN = 0x13, 37 BD718XX_1ST_NODVS_BUCK_VOLT = 0x14, 38 BD718XX_2ND_NODVS_BUCK_VOLT = 0x15, 39 BD718XX_3RD_NODVS_BUCK_VOLT = 0x16, 40 BD718XX_4TH_NODVS_BUCK_VOLT = 0x17, 41 BD718XX_LDO1_VOLT = 0x18, 42 BD718XX_LDO2_VOLT = 0x19, 43 BD718XX_LDO3_VOLT = 0x1a, 44 BD718XX_LDO4_VOLT = 0x1b, 45 BD718XX_LDO5_VOLT = 0x1c, 46 BD718XX_LDO6_VOLT = 0x1d, 47 BD71837_LDO7_VOLT = 0x1e, 48 BD718XX_TRANS_COND0 = 0x1f, 49 BD718XX_TRANS_COND1 = 0x20, 50 BD718XX_VRFAULTEN = 0x21, 51 BD718XX_MVRFLTMASK0 = 0x22, 52 BD718XX_MVRFLTMASK1 = 0x23, 53 BD718XX_MVRFLTMASK2 = 0x24, 54 BD718XX_RCVCFG = 0x25, 55 BD718XX_RCVNUM = 0x26, 56 BD718XX_PWRONCONFIG0 = 0x27, 57 BD718XX_PWRONCONFIG1 = 0x28, 58 BD718XX_RESETSRC = 0x29, 59 BD718XX_MIRQ = 0x2a, 60 BD718XX_IRQ = 0x2b, 61 BD718XX_IN_MON = 0x2c, 62 BD718XX_POW_STATE = 0x2d, 63 BD718XX_OUT32K = 0x2e, 64 BD718XX_REGLOCK = 0x2f, 65 BD718XX_MUXSW_EN = 0x30, 66 BD718XX_REG_OTPVER = 0xff, 67 BD718XX_MAX_REGISTER = 0x100, 68 }; 69 70 #define BD718XX_REGLOCK_PWRSEQ 0x1 71 #define BD718XX_REGLOCK_VREG 0x10 72 73 #define BD718XX_BUCK_EN 0x01 74 #define BD718XX_LDO_EN 0x40 75 #define BD718XX_BUCK_SEL 0x02 76 #define BD718XX_LDO_SEL 0x80 77 78 #define DVS_BUCK_RUN_MASK 0x3f 79 #define BD718XX_1ST_NODVS_BUCK_MASK 0x07 80 #define BD718XX_3RD_NODVS_BUCK_MASK 0x07 81 #define BD718XX_4TH_NODVS_BUCK_MASK 0x3f 82 83 #define BD71847_BUCK3_MASK 0x07 84 #define BD71847_BUCK3_RANGE_MASK 0xc0 85 #define BD71847_BUCK4_MASK 0x03 86 #define BD71847_BUCK4_RANGE_MASK 0x40 87 88 #define BD71837_BUCK5_RANGE_MASK 0x80 89 #define BD71837_BUCK6_MASK 0x03 90 91 #define BD718XX_LDO1_MASK 0x03 92 #define BD718XX_LDO1_RANGE_MASK 0x20 93 #define BD718XX_LDO2_MASK 0x20 94 #define BD718XX_LDO3_MASK 0x0f 95 #define BD718XX_LDO4_MASK 0x0f 96 #define BD718XX_LDO6_MASK 0x0f 97 98 #define BD71837_LDO5_MASK 0x0f 99 #define BD71847_LDO5_MASK 0x0f 100 #define BD71847_LDO5_RANGE_MASK 0x20 101 #define BD71837_LDO7_MASK 0x0f 102 103 #endif 104