1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 *
5 */
6
7 #include <common.h>
8 #include <hang.h>
9 #include <init.h>
10 #include <asm/arch/ddr.h>
11 #include <asm/arch/imx8mq_pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch/clock.h>
14 #include <asm/mach-imx/gpio.h>
15 #include <asm/mach-imx/mxc_i2c.h>
16 #include <fsl_esdhc_imx.h>
17 #include <linux/delay.h>
18 #include <spl.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
spl_dram_init(void)22 static void spl_dram_init(void)
23 {
24 /* ddr init */
25 ddr_init(&dram_timing);
26 }
27
28 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
29 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
30 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
31
board_mmc_getcd(struct mmc * mmc)32 int board_mmc_getcd(struct mmc *mmc)
33 {
34 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
35 int ret = 0;
36
37 switch (cfg->esdhc_base) {
38 case USDHC1_BASE_ADDR:
39 ret = 1;
40 break;
41 case USDHC2_BASE_ADDR:
42 ret = gpio_get_value(USDHC2_CD_GPIO);
43 return ret;
44 }
45
46 return 1;
47 }
48
49 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
50 PAD_CTL_FSEL2)
51 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
52
53 static iomux_v3_cfg_t const usdhc1_pads[] = {
54 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
65 };
66
67 static iomux_v3_cfg_t const usdhc2_pads[] = {
68 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
75 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
76 };
77
78 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
79 {USDHC1_BASE_ADDR, 0, 8},
80 {USDHC2_BASE_ADDR, 0, 4},
81 };
82
board_mmc_init(struct bd_info * bis)83 int board_mmc_init(struct bd_info *bis)
84 {
85 int i, ret;
86 /*
87 * According to the board_mmc_init() the following map is done:
88 * (U-Boot device node) (Physical Port)
89 * mmc0 USDHC1
90 * mmc1 USDHC2
91 */
92 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
93 switch (i) {
94 case 0:
95 init_clk_usdhc(0);
96 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
97 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
98 ARRAY_SIZE(usdhc1_pads));
99 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
100 gpio_direction_output(USDHC1_PWR_GPIO, 0);
101 udelay(500);
102 gpio_direction_output(USDHC1_PWR_GPIO, 1);
103 break;
104 case 1:
105 init_clk_usdhc(1);
106 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
107 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
108 ARRAY_SIZE(usdhc2_pads));
109 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
110 gpio_direction_output(USDHC2_PWR_GPIO, 0);
111 udelay(500);
112 gpio_direction_output(USDHC2_PWR_GPIO, 1);
113 break;
114 default:
115 printf("Warning: you configured more USDHC controllers(%d)"
116 " than supported by the board\n", i + 1);
117 return -EINVAL;
118 }
119
120 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
121 if (ret)
122 return ret;
123 }
124
125 return 0;
126 }
127
spl_board_init(void)128 void spl_board_init(void)
129 {
130 puts("Normal Boot\n");
131 }
132
board_init_f(ulong dummy)133 void board_init_f(ulong dummy)
134 {
135 int ret;
136
137 /* Clear global data */
138 memset((void *)gd, 0, sizeof(gd_t));
139
140 arch_cpu_init();
141
142 init_uart_clk(0);
143
144 board_early_init_f();
145
146 timer_init();
147
148 preloader_console_init();
149
150 /* Clear the BSS. */
151 memset(__bss_start, 0, __bss_end - __bss_start);
152
153 ret = spl_init();
154 if (ret) {
155 debug("spl_init() failed: %d\n", ret);
156 hang();
157 }
158
159 enable_tzc380();
160
161 /* DDR initialization */
162 spl_dram_init();
163
164 board_init_r(NULL, 0);
165 }
166