1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
7 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 */
9
10 #include <common.h>
11 #include <init.h>
12 #include <asm/global_data.h>
13 #include <linux/sizes.h>
14 #include <asm/io.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/at91_matrix.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/gpio.h>
22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
23 #include <net.h>
24 #endif
25 #include <netdev.h>
26 #include <asm/mach-types.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 /* ------------------------------------------------------------------------- */
31 /*
32 * Miscelaneous platform dependent initialisations
33 */
34
35 #ifdef CONFIG_CMD_NAND
pm9263_nand_hw_init(void)36 static void pm9263_nand_hw_init(void)
37 {
38 unsigned long csa;
39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
41
42 /* Enable CS3 */
43 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
44 writel(csa, &matrix->csa[0]);
45
46 /* Configure SMC CS3 for NAND/SmartMedia */
47 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
48 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
49 &smc->cs[3].setup);
50
51 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
53 &smc->cs[3].pulse);
54
55 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
56 &smc->cs[3].cycle);
57
58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
59 AT91_SMC_MODE_EXNW_DISABLE |
60 #ifdef CONFIG_SYS_NAND_DBW_16
61 AT91_SMC_MODE_DBW_16 |
62 #else /* CONFIG_SYS_NAND_DBW_8 */
63 AT91_SMC_MODE_DBW_8 |
64 #endif
65 AT91_SMC_MODE_TDF_CYCLE(2),
66 &smc->cs[3].mode);
67
68 /* Configure RDY/BSY */
69 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
70
71 /* Enable NandFlash */
72 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
73 }
74 #endif
75
76 #ifdef CONFIG_MACB
pm9263_macb_hw_init(void)77 static void pm9263_macb_hw_init(void)
78 {
79 /*
80 * PB27 enables the 50MHz oscillator for Ethernet PHY
81 * 1 - enable
82 * 0 - disable
83 */
84 at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
85 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
86
87 at91_periph_clk_enable(ATMEL_ID_EMAC);
88
89 /*
90 * Disable pull-up on:
91 * RXDV (PC25) => PHY normal mode (not Test mode)
92 * ERX0 (PE25) => PHY ADDR0
93 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
94 *
95 * PHY has internal pull-down
96 */
97
98 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
99 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
100 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
101
102 /* Re-enable pull-up */
103 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
104 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
105 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
106
107 at91_macb_hw_init();
108 }
109 #endif
110
111 #ifdef CONFIG_LCD
112
113 #ifdef CONFIG_LCD_IN_PSRAM
114
115 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
116 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
117
118 /* Initialize the PSRAM memory */
pm9263_lcd_hw_psram_init(void)119 static int pm9263_lcd_hw_psram_init(void)
120 {
121 unsigned long csa;
122 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
123 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
124
125 /* Enable CS3 3.3v, no pull-ups */
126 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
127 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
128
129 writel(csa, &matrix->csa[1]);
130
131 /* Configure SMC1 CS0 for PSRAM - 16-bit */
132 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
133 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
134 &smc->cs[0].setup);
135
136 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
137 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
138 &smc->cs[0].pulse);
139
140 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
141 &smc->cs[0].cycle);
142
143 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
144 &smc->cs[0].mode);
145
146 /* setup PB29 as output */
147 at91_set_pio_output(PSRAM_CRE_PIN, 1);
148
149 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
150
151 /* PSRAM: write BCR */
152 readw(PSRAM_CTRL_REG);
153 readw(PSRAM_CTRL_REG);
154 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
155 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
156
157 /* write RCR of the PSRAM */
158 readw(PSRAM_CTRL_REG);
159 readw(PSRAM_CTRL_REG);
160 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
161 /* set RCR; 0x10-async mode,0x90-page mode */
162 writew(0x90, PSRAM_CTRL_REG);
163
164 /*
165 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
166 * MT45W2M16B - CRE must be 0
167 * MT45W2M16A - CRE must be 1
168 */
169 writew(0x1234, PHYS_PSRAM);
170 writew(0x5678, PHYS_PSRAM + 2);
171
172 /* test if the chip is MT45W2M16B */
173 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
174 /* try with CRE=1 (MT45W2M16A) */
175 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
176
177 /* write RCR of the PSRAM */
178 readw(PSRAM_CTRL_REG);
179 readw(PSRAM_CTRL_REG);
180 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
181 /* set RCR;0x10-async mode,0x90-page mode */
182 writew(0x90, PSRAM_CTRL_REG);
183
184
185 writew(0x1234, PHYS_PSRAM);
186 writew(0x5678, PHYS_PSRAM+2);
187 if ((readw(PHYS_PSRAM) != 0x1234)
188 || (readw(PHYS_PSRAM + 2) != 0x5678))
189 return 1;
190
191 }
192
193 /* Bus matrix */
194 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
195 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
196
197 return 0;
198 }
199 #endif
200
pm9263_lcd_hw_init(void)201 static void pm9263_lcd_hw_init(void)
202 {
203 /* Power Control */
204 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
205 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
206
207 #ifdef CONFIG_LCD_IN_PSRAM
208 /* initialize te PSRAM */
209 int stat = pm9263_lcd_hw_psram_init();
210
211 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
212 #else
213 gd->fb_base = ATMEL_BASE_SRAM0;
214 #endif
215
216 }
217
218 #endif /* CONFIG_LCD */
219
board_early_init_f(void)220 int board_early_init_f(void)
221 {
222 return 0;
223 }
224
board_init(void)225 int board_init(void)
226 {
227 /* arch number of AT91SAM9263EK-Board */
228 gd->bd->bi_arch_number = MACH_TYPE_PM9263;
229
230 /* adress of boot parameters */
231 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
232
233 #ifdef CONFIG_CMD_NAND
234 pm9263_nand_hw_init();
235 #endif
236 #ifdef CONFIG_MACB
237 pm9263_macb_hw_init();
238 #endif
239 #ifdef CONFIG_USB_OHCI_NEW
240 at91_uhp_hw_init();
241 #endif
242 #ifdef CONFIG_LCD
243 pm9263_lcd_hw_init();
244 #endif
245 return 0;
246 }
247
dram_init(void)248 int dram_init(void)
249 {
250 /* dram_init must store complete ramsize in gd->ram_size */
251 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
252 PHYS_SDRAM_SIZE);
253 return 0;
254 }
255
dram_init_banksize(void)256 int dram_init_banksize(void)
257 {
258 gd->bd->bi_dram[0].start = PHYS_SDRAM;
259 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
260
261 return 0;
262 }
263
264 #ifdef CONFIG_RESET_PHY_R
reset_phy(void)265 void reset_phy(void)
266 {
267 }
268 #endif
269
board_eth_init(struct bd_info * bis)270 int board_eth_init(struct bd_info *bis)
271 {
272 int rc = 0;
273 #ifdef CONFIG_MACB
274 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
275 #endif
276 return rc;
277 }
278
279 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)280 int checkboard (void)
281 {
282 char *ss;
283
284 printf ("Board : Ronetix PM9263\n");
285
286 switch (gd->fb_base) {
287 case PHYS_PSRAM:
288 ss = "(PSRAM)";
289 break;
290
291 case ATMEL_BASE_SRAM0:
292 ss = "(Internal SRAM)";
293 break;
294
295 default:
296 ss = "";
297 break;
298 }
299 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
300
301 printf ("\n");
302 return 0;
303 }
304 #endif
305