1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 *
6 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
8 */
9 #ifndef __LINUX_CLK_PROVIDER_H
10 #define __LINUX_CLK_PROVIDER_H
11
12 #include <linux/bitops.h>
13 #include <linux/err.h>
14 #include <clk-uclass.h>
15
16 struct udevice;
17
clk_dm(ulong id,struct clk * clk)18 static inline void clk_dm(ulong id, struct clk *clk)
19 {
20 if (!IS_ERR(clk))
21 clk->id = id;
22 }
23
24 /*
25 * flags used across common struct clk. these flags should only affect the
26 * top-level framework. custom flags for dealing with hardware specifics
27 * belong in struct clk_foo
28 *
29 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
30 */
31 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
32 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
33 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
34 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
35 /* unused */
36 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
37 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
38 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
39 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
40 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
41 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
42 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
43 /* parents need enable during gate/ungate, set rate and re-parent */
44 #define CLK_OPS_PARENT_ENABLE BIT(12)
45 /* duty cycle call may be forwarded to the parent clock */
46 #define CLK_DUTY_CYCLE_PARENT BIT(13)
47
48 #define CLK_MUX_INDEX_ONE BIT(0)
49 #define CLK_MUX_INDEX_BIT BIT(1)
50 #define CLK_MUX_HIWORD_MASK BIT(2)
51 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
52 #define CLK_MUX_ROUND_CLOSEST BIT(4)
53
54 struct clk_mux {
55 struct clk clk;
56 void __iomem *reg;
57 u32 *table;
58 u32 mask;
59 u8 shift;
60 u8 flags;
61
62 /*
63 * Fields from struct clk_init_data - this struct has been
64 * omitted to avoid too deep level of CCF for bootloader
65 */
66 const char * const *parent_names;
67 u8 num_parents;
68 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
69 u32 io_mux_val;
70 #endif
71
72 };
73
74 #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
75 extern const struct clk_ops clk_mux_ops;
76 u8 clk_mux_get_parent(struct clk *clk);
77
78 /**
79 * clk_mux_index_to_val() - Convert the parent index to the register value
80 *
81 * It returns the value to write in the hardware register to output the selected
82 * input clock parent.
83 *
84 * @table: array of register values corresponding to the parent index (optional)
85 * @flags: hardware-specific flags
86 * @index: parent clock index
87 * @return the register value
88 */
89 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
90
91 struct clk_gate {
92 struct clk clk;
93 void __iomem *reg;
94 u8 bit_idx;
95 u8 flags;
96 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
97 u32 io_gate_val;
98 #endif
99 };
100
101 #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
102
103 #define CLK_GATE_SET_TO_DISABLE BIT(0)
104 #define CLK_GATE_HIWORD_MASK BIT(1)
105
106 extern const struct clk_ops clk_gate_ops;
107 struct clk *clk_register_gate(struct device *dev, const char *name,
108 const char *parent_name, unsigned long flags,
109 void __iomem *reg, u8 bit_idx,
110 u8 clk_gate_flags, spinlock_t *lock);
111
112 struct clk_div_table {
113 unsigned int val;
114 unsigned int div;
115 };
116
117 struct clk_divider {
118 struct clk clk;
119 void __iomem *reg;
120 u8 shift;
121 u8 width;
122 u8 flags;
123 const struct clk_div_table *table;
124 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
125 u32 io_divider_val;
126 #endif
127 };
128
129 #define clk_div_mask(width) ((1 << (width)) - 1)
130 #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
131
132 #define CLK_DIVIDER_ONE_BASED BIT(0)
133 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
134 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
135 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
136 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
137 #define CLK_DIVIDER_READ_ONLY BIT(5)
138 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
139 extern const struct clk_ops clk_divider_ops;
140
141 /**
142 * clk_divider_get_table_div() - convert the register value to the divider
143 *
144 * @table: array of register values corresponding to valid dividers
145 * @val: value to convert
146 * @return the divider
147 */
148 unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
149 unsigned int val);
150
151 /**
152 * clk_divider_get_table_val() - convert the divider to the register value
153 *
154 * It returns the value to write in the hardware register to divide the input
155 * clock rate by @div.
156 *
157 * @table: array of register values corresponding to valid dividers
158 * @div: requested divider
159 * @return the register value
160 */
161 unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
162 unsigned int div);
163
164 /**
165 * clk_divider_is_valid_div() - check if the divider is valid
166 *
167 * @table: array of valid dividers (optional)
168 * @div: divider to check
169 * @flags: hardware-specific flags
170 * @return true if the divider is valid, false otherwise
171 */
172 bool clk_divider_is_valid_div(const struct clk_div_table *table,
173 unsigned int div, unsigned long flags);
174
175 /**
176 * clk_divider_is_valid_table_div - check if the divider is in the @table array
177 *
178 * @table: array of valid dividers
179 * @div: divider to check
180 * @return true if the divider is found in the @table array, false otherwise
181 */
182 bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
183 unsigned int div);
184 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
185 unsigned int val,
186 const struct clk_div_table *table,
187 unsigned long flags, unsigned long width);
188
189 struct clk_fixed_factor {
190 struct clk clk;
191 unsigned int mult;
192 unsigned int div;
193 };
194
195 extern const struct clk_ops clk_fixed_rate_ops;
196
197 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
198 clk)
199
200 struct clk_fixed_rate {
201 struct clk clk;
202 unsigned long fixed_rate;
203 };
204
205 #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_plat(dev))
206
207 void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
208 struct clk_fixed_rate *plat);
209
210 struct clk_composite {
211 struct clk clk;
212 struct clk_ops ops;
213
214 struct clk *mux;
215 struct clk *rate;
216 struct clk *gate;
217
218 const struct clk_ops *mux_ops;
219 const struct clk_ops *rate_ops;
220 const struct clk_ops *gate_ops;
221 };
222
223 #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
224
225 struct clk *clk_register_composite(struct device *dev, const char *name,
226 const char * const *parent_names, int num_parents,
227 struct clk *mux_clk, const struct clk_ops *mux_ops,
228 struct clk *rate_clk, const struct clk_ops *rate_ops,
229 struct clk *gate_clk, const struct clk_ops *gate_ops,
230 unsigned long flags);
231
232 int clk_register(struct clk *clk, const char *drv_name, const char *name,
233 const char *parent_name);
234
235 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
236 const char *parent_name, unsigned long flags,
237 unsigned int mult, unsigned int div);
238
239 struct clk *clk_register_divider(struct device *dev, const char *name,
240 const char *parent_name, unsigned long flags,
241 void __iomem *reg, u8 shift, u8 width,
242 u8 clk_divider_flags);
243
244 struct clk *clk_register_mux(struct device *dev, const char *name,
245 const char * const *parent_names, u8 num_parents,
246 unsigned long flags,
247 void __iomem *reg, u8 shift, u8 width,
248 u8 clk_mux_flags);
249
250 const char *clk_hw_get_name(const struct clk *hw);
251 ulong clk_generic_get_rate(struct clk *clk);
252
253 struct clk *dev_get_clk_ptr(struct udevice *dev);
254 #endif /* __LINUX_CLK_PROVIDER_H */
255