1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 */
8
9 #ifndef CONFIG_CLK_MPC83XX
10
11 #include <common.h>
12 #include <clock_legacy.h>
13 #include <mpc83xx.h>
14 #include <command.h>
15 #include <vsprintf.h>
16 #include <asm/global_data.h>
17 #include <asm/processor.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /* ----------------------------------------------------------------- */
22
23 typedef enum {
24 _unk,
25 _off,
26 _byp,
27 _x8,
28 _x4,
29 _x2,
30 _x1,
31 _1x,
32 _1_5x,
33 _2x,
34 _2_5x,
35 _3x
36 } mult_t;
37
38 typedef struct {
39 mult_t core_csb_ratio;
40 mult_t vco_divider;
41 } corecnf_t;
42
43 static corecnf_t corecnf_tab[] = {
44 {_byp, _byp}, /* 0x00 */
45 {_byp, _byp}, /* 0x01 */
46 {_byp, _byp}, /* 0x02 */
47 {_byp, _byp}, /* 0x03 */
48 {_byp, _byp}, /* 0x04 */
49 {_byp, _byp}, /* 0x05 */
50 {_byp, _byp}, /* 0x06 */
51 {_byp, _byp}, /* 0x07 */
52 {_1x, _x2}, /* 0x08 */
53 {_1x, _x4}, /* 0x09 */
54 {_1x, _x8}, /* 0x0A */
55 {_1x, _x8}, /* 0x0B */
56 {_1_5x, _x2}, /* 0x0C */
57 {_1_5x, _x4}, /* 0x0D */
58 {_1_5x, _x8}, /* 0x0E */
59 {_1_5x, _x8}, /* 0x0F */
60 {_2x, _x2}, /* 0x10 */
61 {_2x, _x4}, /* 0x11 */
62 {_2x, _x8}, /* 0x12 */
63 {_2x, _x8}, /* 0x13 */
64 {_2_5x, _x2}, /* 0x14 */
65 {_2_5x, _x4}, /* 0x15 */
66 {_2_5x, _x8}, /* 0x16 */
67 {_2_5x, _x8}, /* 0x17 */
68 {_3x, _x2}, /* 0x18 */
69 {_3x, _x4}, /* 0x19 */
70 {_3x, _x8}, /* 0x1A */
71 {_3x, _x8}, /* 0x1B */
72 };
73
74 /* ----------------------------------------------------------------- */
75
76 /*
77 *
78 */
get_clocks(void)79 int get_clocks(void)
80 {
81 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
82 u32 pci_sync_in;
83 u8 spmf;
84 u8 clkin_div;
85 u32 sccr;
86 u32 corecnf_tab_index;
87 u8 corepll;
88 u32 lcrr;
89
90 u32 csb_clk;
91 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
92 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
93 u32 tsec1_clk;
94 u32 tsec2_clk;
95 u32 usbdr_clk;
96 #elif defined(CONFIG_ARCH_MPC8309)
97 u32 usbdr_clk;
98 #endif
99 #ifdef CONFIG_ARCH_MPC834X
100 u32 usbmph_clk;
101 #endif
102 u32 core_clk;
103 u32 i2c1_clk;
104 #if !defined(CONFIG_ARCH_MPC832X)
105 u32 i2c2_clk;
106 #endif
107 #if defined(CONFIG_ARCH_MPC8315)
108 u32 tdm_clk;
109 #endif
110 #if defined(CONFIG_FSL_ESDHC)
111 u32 sdhc_clk;
112 #endif
113 #if !defined(CONFIG_ARCH_MPC8309)
114 u32 enc_clk;
115 #endif
116 u32 lbiu_clk;
117 u32 lclk_clk;
118 u32 mem_clk;
119 #if defined(CONFIG_ARCH_MPC8360)
120 u32 mem_sec_clk;
121 #endif
122 #if defined(CONFIG_QE)
123 u32 qepmf;
124 u32 qepdf;
125 u32 qe_clk;
126 u32 brg_clk;
127 #endif
128 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
129 defined(CONFIG_ARCH_MPC837X)
130 u32 pciexp1_clk;
131 u32 pciexp2_clk;
132 #endif
133 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
134 u32 sata_clk;
135 #endif
136
137 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
138 return -1;
139
140 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
141
142 if (im->reset.rcwh & HRCWH_PCI_HOST) {
143 #if defined(CONFIG_SYS_CLK_FREQ)
144 pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
145 #else
146 pci_sync_in = 0xDEADBEEF;
147 #endif
148 } else {
149 #if defined(CONFIG_83XX_PCICLK)
150 pci_sync_in = CONFIG_83XX_PCICLK;
151 #else
152 pci_sync_in = 0xDEADBEEF;
153 #endif
154 }
155
156 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
157 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
158
159 sccr = im->clk.sccr;
160
161 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
162 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
163 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
164 case 0:
165 tsec1_clk = 0;
166 break;
167 case 1:
168 tsec1_clk = csb_clk;
169 break;
170 case 2:
171 tsec1_clk = csb_clk / 2;
172 break;
173 case 3:
174 tsec1_clk = csb_clk / 3;
175 break;
176 default:
177 /* unknown SCCR_TSEC1CM value */
178 return -2;
179 }
180 #endif
181
182 #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
183 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
184 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
185 case 0:
186 usbdr_clk = 0;
187 break;
188 case 1:
189 usbdr_clk = csb_clk;
190 break;
191 case 2:
192 usbdr_clk = csb_clk / 2;
193 break;
194 case 3:
195 usbdr_clk = csb_clk / 3;
196 break;
197 default:
198 /* unknown SCCR_USBDRCM value */
199 return -3;
200 }
201 #endif
202
203 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
204 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
205 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
206 case 0:
207 tsec2_clk = 0;
208 break;
209 case 1:
210 tsec2_clk = csb_clk;
211 break;
212 case 2:
213 tsec2_clk = csb_clk / 2;
214 break;
215 case 3:
216 tsec2_clk = csb_clk / 3;
217 break;
218 default:
219 /* unknown SCCR_TSEC2CM value */
220 return -4;
221 }
222 #elif defined(CONFIG_ARCH_MPC8313)
223 tsec2_clk = tsec1_clk;
224
225 if (!(sccr & SCCR_TSEC1ON))
226 tsec1_clk = 0;
227 if (!(sccr & SCCR_TSEC2ON))
228 tsec2_clk = 0;
229 #endif
230
231 #if defined(CONFIG_ARCH_MPC834X)
232 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
233 case 0:
234 usbmph_clk = 0;
235 break;
236 case 1:
237 usbmph_clk = csb_clk;
238 break;
239 case 2:
240 usbmph_clk = csb_clk / 2;
241 break;
242 case 3:
243 usbmph_clk = csb_clk / 3;
244 break;
245 default:
246 /* unknown SCCR_USBMPHCM value */
247 return -5;
248 }
249
250 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
251 /* if USB MPH clock is not disabled and
252 * USB DR clock is not disabled then
253 * USB MPH & USB DR must have the same rate
254 */
255 return -6;
256 }
257 #endif
258 #if !defined(CONFIG_ARCH_MPC8309)
259 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
260 case 0:
261 enc_clk = 0;
262 break;
263 case 1:
264 enc_clk = csb_clk;
265 break;
266 case 2:
267 enc_clk = csb_clk / 2;
268 break;
269 case 3:
270 enc_clk = csb_clk / 3;
271 break;
272 default:
273 /* unknown SCCR_ENCCM value */
274 return -7;
275 }
276 #endif
277
278 #if defined(CONFIG_FSL_ESDHC)
279 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
280 case 0:
281 sdhc_clk = 0;
282 break;
283 case 1:
284 sdhc_clk = csb_clk;
285 break;
286 case 2:
287 sdhc_clk = csb_clk / 2;
288 break;
289 case 3:
290 sdhc_clk = csb_clk / 3;
291 break;
292 default:
293 /* unknown SCCR_SDHCCM value */
294 return -8;
295 }
296 #endif
297 #if defined(CONFIG_ARCH_MPC8315)
298 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
299 case 0:
300 tdm_clk = 0;
301 break;
302 case 1:
303 tdm_clk = csb_clk;
304 break;
305 case 2:
306 tdm_clk = csb_clk / 2;
307 break;
308 case 3:
309 tdm_clk = csb_clk / 3;
310 break;
311 default:
312 /* unknown SCCR_TDMCM value */
313 return -8;
314 }
315 #endif
316
317 #if defined(CONFIG_ARCH_MPC834X)
318 i2c1_clk = tsec2_clk;
319 #elif defined(CONFIG_ARCH_MPC8360)
320 i2c1_clk = csb_clk;
321 #elif defined(CONFIG_ARCH_MPC832X)
322 i2c1_clk = enc_clk;
323 #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
324 i2c1_clk = enc_clk;
325 #elif defined(CONFIG_FSL_ESDHC)
326 i2c1_clk = sdhc_clk;
327 #elif defined(CONFIG_ARCH_MPC837X)
328 i2c1_clk = enc_clk;
329 #elif defined(CONFIG_ARCH_MPC8309)
330 i2c1_clk = csb_clk;
331 #endif
332 #if !defined(CONFIG_ARCH_MPC832X)
333 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
334 #endif
335
336 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
337 defined(CONFIG_ARCH_MPC837X)
338 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
339 case 0:
340 pciexp1_clk = 0;
341 break;
342 case 1:
343 pciexp1_clk = csb_clk;
344 break;
345 case 2:
346 pciexp1_clk = csb_clk / 2;
347 break;
348 case 3:
349 pciexp1_clk = csb_clk / 3;
350 break;
351 default:
352 /* unknown SCCR_PCIEXP1CM value */
353 return -9;
354 }
355
356 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
357 case 0:
358 pciexp2_clk = 0;
359 break;
360 case 1:
361 pciexp2_clk = csb_clk;
362 break;
363 case 2:
364 pciexp2_clk = csb_clk / 2;
365 break;
366 case 3:
367 pciexp2_clk = csb_clk / 3;
368 break;
369 default:
370 /* unknown SCCR_PCIEXP2CM value */
371 return -10;
372 }
373 #endif
374
375 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
376 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
377 case 0:
378 sata_clk = 0;
379 break;
380 case 1:
381 sata_clk = csb_clk;
382 break;
383 case 2:
384 sata_clk = csb_clk / 2;
385 break;
386 case 3:
387 sata_clk = csb_clk / 3;
388 break;
389 default:
390 /* unknown SCCR_SATA1CM value */
391 return -11;
392 }
393 #endif
394
395 lbiu_clk = csb_clk *
396 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
397 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
398 switch (lcrr) {
399 case 2:
400 case 4:
401 case 8:
402 lclk_clk = lbiu_clk / lcrr;
403 break;
404 default:
405 /* unknown lcrr */
406 return -12;
407 }
408
409 mem_clk = csb_clk *
410 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
411 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
412
413 #if defined(CONFIG_ARCH_MPC8360)
414 mem_sec_clk = csb_clk * (1 +
415 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
416 #endif
417
418 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
419 if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
420 /* corecnf_tab_index is too high, possibly wrong value */
421 return -11;
422 }
423 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
424 case _byp:
425 case _x1:
426 case _1x:
427 core_clk = csb_clk;
428 break;
429 case _1_5x:
430 core_clk = (3 * csb_clk) / 2;
431 break;
432 case _2x:
433 core_clk = 2 * csb_clk;
434 break;
435 case _2_5x:
436 core_clk = (5 * csb_clk) / 2;
437 break;
438 case _3x:
439 core_clk = 3 * csb_clk;
440 break;
441 default:
442 /* unknown core to csb ratio */
443 return -13;
444 }
445
446 #if defined(CONFIG_QE)
447 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
448 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
449 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
450 brg_clk = qe_clk / 2;
451 #endif
452
453 gd->arch.csb_clk = csb_clk;
454 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
455 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
456 gd->arch.tsec1_clk = tsec1_clk;
457 gd->arch.tsec2_clk = tsec2_clk;
458 gd->arch.usbdr_clk = usbdr_clk;
459 #elif defined(CONFIG_ARCH_MPC8309)
460 gd->arch.usbdr_clk = usbdr_clk;
461 #endif
462 #if defined(CONFIG_ARCH_MPC834X)
463 gd->arch.usbmph_clk = usbmph_clk;
464 #endif
465 #if defined(CONFIG_ARCH_MPC8315)
466 gd->arch.tdm_clk = tdm_clk;
467 #endif
468 #if defined(CONFIG_FSL_ESDHC)
469 gd->arch.sdhc_clk = sdhc_clk;
470 #endif
471 gd->arch.core_clk = core_clk;
472 gd->arch.i2c1_clk = i2c1_clk;
473 #if !defined(CONFIG_ARCH_MPC832X)
474 gd->arch.i2c2_clk = i2c2_clk;
475 #endif
476 #if !defined(CONFIG_ARCH_MPC8309)
477 gd->arch.enc_clk = enc_clk;
478 #endif
479 gd->arch.lbiu_clk = lbiu_clk;
480 gd->arch.lclk_clk = lclk_clk;
481 gd->mem_clk = mem_clk;
482 #if defined(CONFIG_ARCH_MPC8360)
483 gd->arch.mem_sec_clk = mem_sec_clk;
484 #endif
485 #if defined(CONFIG_QE)
486 gd->arch.qe_clk = qe_clk;
487 gd->arch.brg_clk = brg_clk;
488 #endif
489 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
490 defined(CONFIG_ARCH_MPC837X)
491 gd->arch.pciexp1_clk = pciexp1_clk;
492 gd->arch.pciexp2_clk = pciexp2_clk;
493 #endif
494 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
495 gd->arch.sata_clk = sata_clk;
496 #endif
497 gd->pci_clk = pci_sync_in;
498 gd->cpu_clk = gd->arch.core_clk;
499 gd->bus_clk = gd->arch.csb_clk;
500 return 0;
501
502 }
503
504 /********************************************
505 * get_bus_freq
506 * return system bus freq in Hz
507 *********************************************/
get_bus_freq(ulong dummy)508 ulong get_bus_freq(ulong dummy)
509 {
510 return gd->arch.csb_clk;
511 }
512
513 /********************************************
514 * get_ddr_freq
515 * return ddr bus freq in Hz
516 *********************************************/
get_ddr_freq(ulong dummy)517 ulong get_ddr_freq(ulong dummy)
518 {
519 return gd->mem_clk;
520 }
521
get_serial_clock(void)522 int get_serial_clock(void)
523 {
524 return get_bus_freq(0);
525 }
526
do_clocks(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])527 static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
528 char *const argv[])
529 {
530 char buf[32];
531
532 printf("Clock configuration:\n");
533 printf(" Core: %-4s MHz\n",
534 strmhz(buf, gd->arch.core_clk));
535 printf(" Coherent System Bus: %-4s MHz\n",
536 strmhz(buf, gd->arch.csb_clk));
537 #if defined(CONFIG_QE)
538 printf(" QE: %-4s MHz\n",
539 strmhz(buf, gd->arch.qe_clk));
540 printf(" BRG: %-4s MHz\n",
541 strmhz(buf, gd->arch.brg_clk));
542 #endif
543 printf(" Local Bus Controller:%-4s MHz\n",
544 strmhz(buf, gd->arch.lbiu_clk));
545 printf(" Local Bus: %-4s MHz\n",
546 strmhz(buf, gd->arch.lclk_clk));
547 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
548 #if defined(CONFIG_ARCH_MPC8360)
549 printf(" DDR Secondary: %-4s MHz\n",
550 strmhz(buf, gd->arch.mem_sec_clk));
551 #endif
552 #if !defined(CONFIG_ARCH_MPC8309)
553 printf(" SEC: %-4s MHz\n",
554 strmhz(buf, gd->arch.enc_clk));
555 #endif
556 printf(" I2C1: %-4s MHz\n",
557 strmhz(buf, gd->arch.i2c1_clk));
558 #if !defined(CONFIG_ARCH_MPC832X)
559 printf(" I2C2: %-4s MHz\n",
560 strmhz(buf, gd->arch.i2c2_clk));
561 #endif
562 #if defined(CONFIG_ARCH_MPC8315)
563 printf(" TDM: %-4s MHz\n",
564 strmhz(buf, gd->arch.tdm_clk));
565 #endif
566 #if defined(CONFIG_FSL_ESDHC)
567 printf(" SDHC: %-4s MHz\n",
568 strmhz(buf, gd->arch.sdhc_clk));
569 #endif
570 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
571 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
572 printf(" TSEC1: %-4s MHz\n",
573 strmhz(buf, gd->arch.tsec1_clk));
574 printf(" TSEC2: %-4s MHz\n",
575 strmhz(buf, gd->arch.tsec2_clk));
576 printf(" USB DR: %-4s MHz\n",
577 strmhz(buf, gd->arch.usbdr_clk));
578 #elif defined(CONFIG_ARCH_MPC8309)
579 printf(" USB DR: %-4s MHz\n",
580 strmhz(buf, gd->arch.usbdr_clk));
581 #endif
582 #if defined(CONFIG_ARCH_MPC834X)
583 printf(" USB MPH: %-4s MHz\n",
584 strmhz(buf, gd->arch.usbmph_clk));
585 #endif
586 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
587 defined(CONFIG_ARCH_MPC837X)
588 printf(" PCIEXP1: %-4s MHz\n",
589 strmhz(buf, gd->arch.pciexp1_clk));
590 printf(" PCIEXP2: %-4s MHz\n",
591 strmhz(buf, gd->arch.pciexp2_clk));
592 #endif
593 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
594 printf(" SATA: %-4s MHz\n",
595 strmhz(buf, gd->arch.sata_clk));
596 #endif
597 return 0;
598 }
599
600 U_BOOT_CMD(clocks, 1, 0, do_clocks,
601 "print clock configuration",
602 " clocks"
603 );
604
605 #endif
606