1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2003 Motorola Inc.
6 * Modified by Xianghua Xiao, X.Xiao@motorola.com
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 */
11
12 #include <common.h>
13 #include <env.h>
14 #include <init.h>
15 #include <net.h>
16 #include <watchdog.h>
17 #include <asm/processor.h>
18 #include <ioports.h>
19 #include <sata.h>
20 #include <fm_eth.h>
21 #include <asm/io.h>
22 #include <asm/cache.h>
23 #include <asm/mmu.h>
24 #include <fsl_errata.h>
25 #include <asm/fsl_law.h>
26 #include <asm/fsl_serdes.h>
27 #include <asm/fsl_srio.h>
28 #ifdef CONFIG_FSL_CORENET
29 #include <asm/fsl_portals.h>
30 #include <asm/fsl_liodn.h>
31 #include <fsl_qbman.h>
32 #endif
33 #include <fsl_usb.h>
34 #include <hwconfig.h>
35 #include <linux/compiler.h>
36 #include <linux/delay.h>
37 #include "mp.h"
38 #ifdef CONFIG_CHAIN_OF_TRUST
39 #include <fsl_validate.h>
40 #endif
41 #ifdef CONFIG_FSL_CAAM
42 #include <fsl_sec.h>
43 #endif
44 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
45 #include <asm/fsl_pamu.h>
46 #include <fsl_secboot_err.h>
47 #endif
48 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
49 #include <nand.h>
50 #include <errno.h>
51 #endif
52 #ifndef CONFIG_ARCH_QEMU_E500
53 #include <fsl_ddr.h>
54 #endif
55 #include "../../../../drivers/ata/fsl_sata.h"
56 #ifdef CONFIG_U_QE
57 #include <fsl_qe.h>
58 #endif
59
60 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
61 /*
62 * For deriving usb clock from 100MHz sysclk, reference divisor is set
63 * to a value of 5, which gives an intermediate value 20(100/5). The
64 * multiplication factor integer is set to 24, which when multiplied to
65 * above intermediate value provides clock for usb ip.
66 */
usb_single_source_clk_configure(struct ccsr_usb_phy * usb_phy)67 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
68 {
69 sys_info_t sysinfo;
70
71 get_sys_info(&sysinfo);
72 if (sysinfo.diff_sysclk == 1) {
73 clrbits_be32(&usb_phy->pllprg[1],
74 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
75 setbits_be32(&usb_phy->pllprg[1],
76 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
77 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
78 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
79 }
80 }
81 #endif
82
83 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem * usb_phy)84 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
85 {
86 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
87 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
88
89 /* Increase Disconnect Threshold by 50mV */
90 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
91 INC_DCNT_THRESHOLD_50MV;
92 /* Enable programming of USB High speed Disconnect threshold */
93 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
94 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
95
96 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
97 /* Increase Disconnect Threshold by 50mV */
98 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
99 INC_DCNT_THRESHOLD_50MV;
100 /* Enable programming of USB High speed Disconnect threshold */
101 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
102 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
103 #else
104
105 u32 temp = 0;
106 u32 status = in_be32(&usb_phy->status1);
107
108 u32 squelch_prog_rd_0_2 =
109 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
110 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
111
112 u32 squelch_prog_rd_3_5 =
113 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
114 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
115
116 setbits_be32(&usb_phy->config1,
117 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
118 setbits_be32(&usb_phy->config2,
119 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
120
121 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
122 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
123
124 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
125 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
126 #endif
127 }
128 #endif
129
130
131 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
132 extern qe_iop_conf_t qe_iop_conf_tab[];
133 extern void qe_config_iopin(u8 port, u8 pin, int dir,
134 int open_drain, int assign);
135 extern void qe_init(uint qe_base);
136 extern void qe_reset(void);
137
config_qe_ioports(void)138 static void config_qe_ioports(void)
139 {
140 u8 port, pin;
141 int dir, open_drain, assign;
142 int i;
143
144 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
145 port = qe_iop_conf_tab[i].port;
146 pin = qe_iop_conf_tab[i].pin;
147 dir = qe_iop_conf_tab[i].dir;
148 open_drain = qe_iop_conf_tab[i].open_drain;
149 assign = qe_iop_conf_tab[i].assign;
150 qe_config_iopin(port, pin, dir, open_drain, assign);
151 }
152 }
153 #endif
154
155 #ifdef CONFIG_CPM2
config_8560_ioports(volatile ccsr_cpm_t * cpm)156 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
157 {
158 int portnum;
159
160 for (portnum = 0; portnum < 4; portnum++) {
161 uint pmsk = 0,
162 ppar = 0,
163 psor = 0,
164 pdir = 0,
165 podr = 0,
166 pdat = 0;
167 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
168 iop_conf_t *eiopc = iopc + 32;
169 uint msk = 1;
170
171 /*
172 * NOTE:
173 * index 0 refers to pin 31,
174 * index 31 refers to pin 0
175 */
176 while (iopc < eiopc) {
177 if (iopc->conf) {
178 pmsk |= msk;
179 if (iopc->ppar)
180 ppar |= msk;
181 if (iopc->psor)
182 psor |= msk;
183 if (iopc->pdir)
184 pdir |= msk;
185 if (iopc->podr)
186 podr |= msk;
187 if (iopc->pdat)
188 pdat |= msk;
189 }
190
191 msk <<= 1;
192 iopc++;
193 }
194
195 if (pmsk != 0) {
196 volatile ioport_t *iop = ioport_addr (cpm, portnum);
197 uint tpmsk = ~pmsk;
198
199 /*
200 * the (somewhat confused) paragraph at the
201 * bottom of page 35-5 warns that there might
202 * be "unknown behaviour" when programming
203 * PSORx and PDIRx, if PPARx = 1, so I
204 * decided this meant I had to disable the
205 * dedicated function first, and enable it
206 * last.
207 */
208 iop->ppar &= tpmsk;
209 iop->psor = (iop->psor & tpmsk) | psor;
210 iop->podr = (iop->podr & tpmsk) | podr;
211 iop->pdat = (iop->pdat & tpmsk) | pdat;
212 iop->pdir = (iop->pdir & tpmsk) | pdir;
213 iop->ppar |= ppar;
214 }
215 }
216 }
217 #endif
218
219 #ifdef CONFIG_SYS_FSL_CPC
220 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram(void)221 void disable_cpc_sram(void)
222 {
223 int i;
224
225 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
226
227 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
228 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
229 /* find and disable LAW of SRAM */
230 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
231
232 if (law.index == -1) {
233 printf("\nFatal error happened\n");
234 return;
235 }
236 disable_law(law.index);
237
238 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
239 out_be32(&cpc->cpccsr0, 0);
240 out_be32(&cpc->cpcsrcr0, 0);
241 }
242 }
243 }
244 #endif
245
246 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
247 #ifdef CONFIG_POST
248 #error POST memory test cannot be enabled with TDM
249 #endif
enable_tdm_law(void)250 static void enable_tdm_law(void)
251 {
252 int ret;
253 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
254 int tdm_hwconfig_enabled = 0;
255
256 /*
257 * Extract hwconfig from environment since environment
258 * is not setup properly yet. Search for tdm entry in
259 * hwconfig.
260 */
261 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
262 if (ret > 0) {
263 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
264 /* If tdm is defined in hwconfig, set law for tdm workaround */
265 if (tdm_hwconfig_enabled)
266 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
267 LAW_TRGT_IF_CCSR);
268 }
269 }
270 #endif
271
enable_cpc(void)272 void enable_cpc(void)
273 {
274 int i;
275 int ret;
276 u32 size = 0;
277 u32 cpccfg0;
278 char buffer[HWCONFIG_BUFFER_SIZE];
279 char cpc_subarg[16];
280 bool have_hwconfig = false;
281 int cpc_args = 0;
282 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
283
284 /* Extract hwconfig from environment */
285 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
286 if (ret > 0) {
287 /*
288 * If "en_cpc" is not defined in hwconfig then by default all
289 * cpcs are enable. If this config is defined then individual
290 * cpcs which have to be enabled should also be defined.
291 * e.g en_cpc:cpc1,cpc2;
292 */
293 if (hwconfig_f("en_cpc", buffer))
294 have_hwconfig = true;
295 }
296
297 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
298 if (have_hwconfig) {
299 sprintf(cpc_subarg, "cpc%u", i + 1);
300 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
301 if (cpc_args == 0)
302 continue;
303 }
304 cpccfg0 = in_be32(&cpc->cpccfg0);
305 size += CPC_CFG0_SZ_K(cpccfg0);
306
307 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
308 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
309 #endif
310 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
311 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
312 #endif
313 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
314 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
315 #endif
316 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
317 if (has_erratum_a006379()) {
318 setbits_be32(&cpc->cpchdbcr0,
319 CPC_HDBCR0_SPLRU_LEVEL_EN);
320 }
321 #endif
322
323 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
324 /* Read back to sync write */
325 in_be32(&cpc->cpccsr0);
326
327 }
328
329 puts("Corenet Platform Cache: ");
330 print_size(size * 1024, " enabled\n");
331 }
332
invalidate_cpc(void)333 static void invalidate_cpc(void)
334 {
335 int i;
336 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
337
338 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
339 /* skip CPC when it used as all SRAM */
340 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
341 continue;
342 /* Flash invalidate the CPC and clear all the locks */
343 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
344 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
345 ;
346 }
347 }
348 #else
349 #define enable_cpc()
350 #define invalidate_cpc()
351 #define disable_cpc_sram()
352 #endif /* CONFIG_SYS_FSL_CPC */
353
354 /*
355 * Breathe some life into the CPU...
356 *
357 * Set up the memory map
358 * initialize a bunch of registers
359 */
360
361 #ifdef CONFIG_FSL_CORENET
corenet_tb_init(void)362 static void corenet_tb_init(void)
363 {
364 volatile ccsr_rcpm_t *rcpm =
365 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
366 volatile ccsr_pic_t *pic =
367 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
368 u32 whoami = in_be32(&pic->whoami);
369
370 /* Enable the timebase register for this core */
371 out_be32(&rcpm->ctbenrl, (1 << whoami));
372 }
373 #endif
374
375 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround(void)376 void fsl_erratum_a007212_workaround(void)
377 {
378 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
379 u32 ddr_pll_ratio;
380 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
381 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
382 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
383 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
384 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
385 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
386 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
387 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
388 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
389 #endif
390 #endif
391 /*
392 * Even this workaround applies to selected version of SoCs, it is
393 * safe to apply to all versions, with the limitation of odd ratios.
394 * If RCW has disabled DDR PLL, we have to apply this workaround,
395 * otherwise DDR will not work.
396 */
397 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
398 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
399 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
400 /* check if RCW sets ratio to 0, required by this workaround */
401 if (ddr_pll_ratio != 0)
402 return;
403 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
404 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
405 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
406 /* check if reserved bits have the desired ratio */
407 if (ddr_pll_ratio == 0) {
408 printf("Error: Unknown DDR PLL ratio!\n");
409 return;
410 }
411 ddr_pll_ratio >>= 1;
412
413 setbits_be32(plldadcr1, 0x02000001);
414 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
415 setbits_be32(plldadcr2, 0x02000001);
416 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
417 setbits_be32(plldadcr3, 0x02000001);
418 #endif
419 #endif
420 setbits_be32(dpdovrcr4, 0xe0000000);
421 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
422 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
423 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
424 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
425 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
426 #endif
427 #endif
428 udelay(100);
429 clrbits_be32(plldadcr1, 0x02000001);
430 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
431 clrbits_be32(plldadcr2, 0x02000001);
432 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
433 clrbits_be32(plldadcr3, 0x02000001);
434 #endif
435 #endif
436 clrbits_be32(dpdovrcr4, 0xe0000000);
437 }
438 #endif
439
cpu_init_f(void)440 ulong cpu_init_f(void)
441 {
442 extern void m8560_cpm_reset (void);
443 #ifdef CONFIG_SYS_DCSRBAR_PHYS
444 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
445 #endif
446 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
447 struct law_entry law;
448 #endif
449 #ifdef CONFIG_ARCH_MPC8548
450 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
451 uint svr = get_svr();
452
453 /*
454 * CPU2 errata workaround: A core hang possible while executing
455 * a msync instruction and a snoopable transaction from an I/O
456 * master tagged to make quick forward progress is present.
457 * Fixed in silicon rev 2.1.
458 */
459 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
460 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
461 #endif
462
463 disable_tlb(14);
464 disable_tlb(15);
465
466 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
467 /* Disable the LAW created for NOR flash by the PBI commands */
468 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
469 if (law.index != -1)
470 disable_law(law.index);
471
472 #if defined(CONFIG_SYS_CPC_REINIT_F)
473 disable_cpc_sram();
474 #endif
475 #endif
476
477 #ifdef CONFIG_CPM2
478 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
479 #endif
480
481 init_early_memctl_regs();
482
483 #if defined(CONFIG_CPM2)
484 m8560_cpm_reset();
485 #endif
486
487 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
488 /* Config QE ioports */
489 config_qe_ioports();
490 #endif
491
492 #if defined(CONFIG_FSL_DMA)
493 dma_init();
494 #endif
495 #ifdef CONFIG_FSL_CORENET
496 corenet_tb_init();
497 #endif
498 init_used_tlb_cams();
499
500 /* Invalidate the CPC before DDR gets enabled */
501 invalidate_cpc();
502
503 #ifdef CONFIG_SYS_DCSRBAR_PHYS
504 /* set DCSRCR so that DCSR space is 1G */
505 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
506 in_be32(&gur->dcsrcr);
507 #endif
508
509 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
510 fsl_erratum_a007212_workaround();
511 #endif
512
513 return 0;
514 }
515
516 /* Implement a dummy function for those platforms w/o SERDES */
__fsl_serdes__init(void)517 static void __fsl_serdes__init(void)
518 {
519 return ;
520 }
521 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
522
523 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
enable_cluster_l2(void)524 int enable_cluster_l2(void)
525 {
526 int i = 0;
527 u32 cluster, svr = get_svr();
528 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
529 struct ccsr_cluster_l2 __iomem *l2cache;
530
531 /* only the L2 of first cluster should be enabled as expected on T4080,
532 * but there is no EOC in the first cluster as HW sake, so return here
533 * to skip enabling L2 cache of the 2nd cluster.
534 */
535 if (SVR_SOC_VER(svr) == SVR_T4080)
536 return 0;
537
538 cluster = in_be32(&gur->tp_cluster[i].lower);
539 if (cluster & TP_CLUSTER_EOC)
540 return 0;
541
542 /* The first cache has already been set up, so skip it */
543 i++;
544
545 /* Look through the remaining clusters, and set up their caches */
546 do {
547 int j, cluster_valid = 0;
548
549 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
550
551 cluster = in_be32(&gur->tp_cluster[i].lower);
552
553 /* check that at least one core/accel is enabled in cluster */
554 for (j = 0; j < 4; j++) {
555 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
556 u32 type = in_be32(&gur->tp_ityp[idx]);
557
558 if ((type & TP_ITYP_AV) &&
559 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
560 cluster_valid = 1;
561 }
562
563 if (cluster_valid) {
564 /* set stash ID to (cluster) * 2 + 32 + 1 */
565 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
566
567 printf("enable l2 for cluster %d %p\n", i, l2cache);
568
569 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
570 while ((in_be32(&l2cache->l2csr0)
571 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
572 ;
573 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
574 }
575 i++;
576 } while (!(cluster & TP_CLUSTER_EOC));
577
578 return 0;
579 }
580 #endif
581
582 /*
583 * Initialize L2 as cache.
584 */
l2cache_init(void)585 int l2cache_init(void)
586 {
587 __maybe_unused u32 svr = get_svr();
588 #ifdef CONFIG_L2_CACHE
589 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
590 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
591 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
592 #endif
593
594 puts ("L2: ");
595
596 #if defined(CONFIG_L2_CACHE)
597 volatile uint cache_ctl;
598 uint ver;
599 u32 l2siz_field;
600
601 ver = SVR_SOC_VER(svr);
602
603 asm("msync;isync");
604 cache_ctl = l2cache->l2ctl;
605
606 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
607 if (cache_ctl & MPC85xx_L2CTL_L2E) {
608 /* Clear L2 SRAM memory-mapped base address */
609 out_be32(&l2cache->l2srbar0, 0x0);
610 out_be32(&l2cache->l2srbar1, 0x0);
611
612 /* set MBECCDIS=0, SBECCDIS=0 */
613 clrbits_be32(&l2cache->l2errdis,
614 (MPC85xx_L2ERRDIS_MBECC |
615 MPC85xx_L2ERRDIS_SBECC));
616
617 /* set L2E=0, L2SRAM=0 */
618 clrbits_be32(&l2cache->l2ctl,
619 (MPC85xx_L2CTL_L2E |
620 MPC85xx_L2CTL_L2SRAM_ENTIRE));
621 }
622 #endif
623
624 l2siz_field = (cache_ctl >> 28) & 0x3;
625
626 switch (l2siz_field) {
627 case 0x0:
628 printf(" unknown size (0x%08x)\n", cache_ctl);
629 return -1;
630 break;
631 case 0x1:
632 if (ver == SVR_8540 || ver == SVR_8560 ||
633 ver == SVR_8541 || ver == SVR_8555) {
634 puts("128 KiB ");
635 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
636 cache_ctl = 0xc4000000;
637 } else {
638 puts("256 KiB ");
639 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
640 }
641 break;
642 case 0x2:
643 if (ver == SVR_8540 || ver == SVR_8560 ||
644 ver == SVR_8541 || ver == SVR_8555) {
645 puts("256 KiB ");
646 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
647 cache_ctl = 0xc8000000;
648 } else {
649 puts("512 KiB ");
650 /* set L2E=1, L2I=1, & L2SRAM=0 */
651 cache_ctl = 0xc0000000;
652 }
653 break;
654 case 0x3:
655 puts("1024 KiB ");
656 /* set L2E=1, L2I=1, & L2SRAM=0 */
657 cache_ctl = 0xc0000000;
658 break;
659 }
660
661 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
662 puts("already enabled");
663 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
664 u32 l2srbar = l2cache->l2srbar0;
665 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
666 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
667 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
668 l2cache->l2srbar0 = l2srbar;
669 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
670 }
671 #endif /* CONFIG_SYS_INIT_L2_ADDR */
672 puts("\n");
673 } else {
674 asm("msync;isync");
675 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
676 asm("msync;isync");
677 puts("enabled\n");
678 }
679 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
680 if (SVR_SOC_VER(svr) == SVR_P2040) {
681 puts("N/A\n");
682 goto skip_l2;
683 }
684
685 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
686
687 /* invalidate the L2 cache */
688 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
689 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
690 ;
691
692 #ifdef CONFIG_SYS_CACHE_STASHING
693 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
694 mtspr(SPRN_L2CSR1, (32 + 1));
695 #endif
696
697 /* enable the cache */
698 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
699
700 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
701 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
702 ;
703 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
704 }
705
706 skip_l2:
707 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
708 if (l2cache->l2csr0 & L2CSR0_L2E)
709 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
710 " enabled\n");
711
712 enable_cluster_l2();
713 #else
714 puts("disabled\n");
715 #endif
716
717 return 0;
718 }
719
720 /*
721 *
722 * The newer 8548, etc, parts have twice as much cache, but
723 * use the same bit-encoding as the older 8555, etc, parts.
724 *
725 */
cpu_init_r(void)726 int cpu_init_r(void)
727 {
728 __maybe_unused u32 svr = get_svr();
729 #ifdef CONFIG_SYS_LBC_LCRR
730 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
731 #endif
732 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
733 extern int spin_table_compat;
734 const char *spin;
735 #endif
736 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
737 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
738 #endif
739 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
740 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
741 /*
742 * CPU22 and NMG_CPU_A011 share the same workaround.
743 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
744 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
745 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
746 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
747 * be disabled by hwconfig with syntax:
748 *
749 * fsl_cpu_a011:disable
750 */
751 extern int enable_cpu_a011_workaround;
752 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
753 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
754 #else
755 char buffer[HWCONFIG_BUFFER_SIZE];
756 char *buf = NULL;
757 int n, res;
758
759 n = env_get_f("hwconfig", buffer, sizeof(buffer));
760 if (n > 0)
761 buf = buffer;
762
763 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
764 if (res > 0) {
765 enable_cpu_a011_workaround = 0;
766 } else {
767 if (n >= HWCONFIG_BUFFER_SIZE) {
768 printf("fsl_cpu_a011 was not found. hwconfig variable "
769 "may be too long\n");
770 }
771 enable_cpu_a011_workaround =
772 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
773 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
774 }
775 #endif
776 if (enable_cpu_a011_workaround) {
777 flush_dcache();
778 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
779 sync();
780 }
781 #endif
782
783 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
784 flush_dcache();
785 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
786 sync();
787 #endif
788
789 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
790 /*
791 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
792 * in write shadow mode. Checking DCWS before setting SPR 976.
793 */
794 if (mfspr(L1CSR2) & L1CSR2_DCWS)
795 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
796 #endif
797
798 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
799 spin = env_get("spin_table_compat");
800 if (spin && (*spin == 'n'))
801 spin_table_compat = 0;
802 else
803 spin_table_compat = 1;
804 #endif
805
806 #ifdef CONFIG_FSL_CORENET
807 set_liodns();
808 #ifdef CONFIG_SYS_DPAA_QBMAN
809 setup_qbman_portals();
810 #endif
811 #endif
812
813 l2cache_init();
814 #if defined(CONFIG_RAMBOOT_PBL)
815 disable_cpc_sram();
816 #endif
817 enable_cpc();
818 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
819 enable_tdm_law();
820 #endif
821
822 #ifndef CONFIG_SYS_FSL_NO_SERDES
823 /* needs to be in ram since code uses global static vars */
824 fsl_serdes_init();
825 #endif
826
827 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
828 #define MCFGR_AXIPIPE 0x000000f0
829 if (IS_SVR_REV(svr, 1, 0))
830 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
831 #endif
832
833 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
834 if (IS_SVR_REV(svr, 1, 0)) {
835 int i;
836 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
837
838 for (i = 0; i < 12; i++) {
839 p += i + (i > 5 ? 11 : 0);
840 out_be32(p, 0x2);
841 }
842 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
843 out_be32(p, 0x34);
844 }
845 #endif
846
847 #ifdef CONFIG_SYS_SRIO
848 srio_init();
849 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
850 char *s = env_get("bootmaster");
851 if (s) {
852 if (!strcmp(s, "SRIO1")) {
853 srio_boot_master(1);
854 srio_boot_master_release_slave(1);
855 }
856 if (!strcmp(s, "SRIO2")) {
857 srio_boot_master(2);
858 srio_boot_master_release_slave(2);
859 }
860 }
861 #endif
862 #endif
863
864 #if defined(CONFIG_MP)
865 setup_mp();
866 #endif
867
868 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
869 {
870 if (SVR_MAJ(svr) < 3) {
871 void *p;
872 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
873 setbits_be32(p, 1 << (31 - 14));
874 }
875 }
876 #endif
877
878 #ifdef CONFIG_SYS_LBC_LCRR
879 /*
880 * Modify the CLKDIV field of LCRR register to improve the writing
881 * speed for NOR flash.
882 */
883 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
884 __raw_readl(&lbc->lcrr);
885 isync();
886 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
887 udelay(100);
888 #endif
889 #endif
890
891 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
892 {
893 struct ccsr_usb_phy __iomem *usb_phy1 =
894 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
895 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
896 if (has_erratum_a006261())
897 fsl_erratum_a006261_workaround(usb_phy1);
898 #endif
899 out_be32(&usb_phy1->usb_enable_override,
900 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
901 }
902 #endif
903 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
904 {
905 struct ccsr_usb_phy __iomem *usb_phy2 =
906 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
907 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
908 if (has_erratum_a006261())
909 fsl_erratum_a006261_workaround(usb_phy2);
910 #endif
911 out_be32(&usb_phy2->usb_enable_override,
912 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
913 }
914 #endif
915
916 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
917 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
918 * multi-bit ECC errors which has impact on performance, so software
919 * should disable all ECC reporting from USB1 and USB2.
920 */
921 if (IS_SVR_REV(get_svr(), 1, 0)) {
922 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
923 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
924 setbits_be32(&dcfg->ecccr1,
925 (DCSR_DCFG_ECC_DISABLE_USB1 |
926 DCSR_DCFG_ECC_DISABLE_USB2));
927 }
928 #endif
929
930 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
931 struct ccsr_usb_phy __iomem *usb_phy =
932 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
933 setbits_be32(&usb_phy->pllprg[1],
934 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
935 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
936 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
937 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
938 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
939 usb_single_source_clk_configure(usb_phy);
940 #endif
941 setbits_be32(&usb_phy->port1.ctrl,
942 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
943 setbits_be32(&usb_phy->port1.drvvbuscfg,
944 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
945 setbits_be32(&usb_phy->port1.pwrfltcfg,
946 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
947 setbits_be32(&usb_phy->port2.ctrl,
948 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
949 setbits_be32(&usb_phy->port2.drvvbuscfg,
950 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
951 setbits_be32(&usb_phy->port2.pwrfltcfg,
952 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
953
954 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
955 if (has_erratum_a006261())
956 fsl_erratum_a006261_workaround(usb_phy);
957 #endif
958
959 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
960
961 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
962 erratum_a009942_check_cpo();
963 #endif
964
965 #ifdef CONFIG_FMAN_ENET
966 #ifndef CONFIG_DM_ETH
967 fman_enet_init();
968 #endif
969 #endif
970
971 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
972 if (pamu_init() < 0)
973 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
974 #endif
975
976 #ifdef CONFIG_FSL_CAAM
977 sec_init();
978
979 #if defined(CONFIG_ARCH_C29X)
980 if ((SVR_SOC_VER(svr) == SVR_C292) ||
981 (SVR_SOC_VER(svr) == SVR_C293))
982 sec_init_idx(1);
983
984 if (SVR_SOC_VER(svr) == SVR_C293)
985 sec_init_idx(2);
986 #endif
987 #endif
988
989 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
990 /*
991 * For P1022/1013 Rev1.0 silicon, after power on SATA host
992 * controller is configured in legacy mode instead of the
993 * expected enterprise mode. Software needs to clear bit[28]
994 * of HControl register to change to enterprise mode from
995 * legacy mode. We assume that the controller is offline.
996 */
997 if (IS_SVR_REV(svr, 1, 0) &&
998 ((SVR_SOC_VER(svr) == SVR_P1022) ||
999 (SVR_SOC_VER(svr) == SVR_P1013))) {
1000 fsl_sata_reg_t *reg;
1001
1002 /* first SATA controller */
1003 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
1004 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
1005
1006 /* second SATA controller */
1007 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
1008 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
1009 }
1010 #endif
1011
1012 init_used_tlb_cams();
1013
1014 return 0;
1015 }
1016
arch_preboot_os(void)1017 void arch_preboot_os(void)
1018 {
1019 u32 msr;
1020
1021 /*
1022 * We are changing interrupt offsets and are about to boot the OS so
1023 * we need to make sure we disable all async interrupts. EE is already
1024 * disabled by the time we get called.
1025 */
1026 msr = mfmsr();
1027 msr &= ~(MSR_ME|MSR_CE);
1028 mtmsr(msr);
1029 }
1030
cpu_secondary_init_r(void)1031 int cpu_secondary_init_r(void)
1032 {
1033 #ifdef CONFIG_QE
1034 #ifdef CONFIG_U_QE
1035 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1036 #else
1037 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
1038 #endif
1039
1040 qe_init(qe_base);
1041 qe_reset();
1042 #endif
1043
1044 return 0;
1045 }
1046
1047 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)1048 int board_late_init(void)
1049 {
1050 #ifdef CONFIG_CHAIN_OF_TRUST
1051 fsl_setenv_chain_of_trust();
1052 #endif
1053
1054 return 0;
1055 }
1056 #endif
1057