1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale MX28EVK board
4 *
5 * (C) Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * Author: Fabio Estevam <fabio.estevam@freescale.com>
8 *
9 * Based on m28evk.c:
10 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
11 * on behalf of DENX Software Engineering GmbH
12 */
13
14 #include <common.h>
15 #include <init.h>
16 #include <net.h>
17 #include <asm/global_data.h>
18 #include <asm/gpio.h>
19 #include <asm/io.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/iomux-mx28.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/sys_proto.h>
24 #include <linux/delay.h>
25 #include <linux/mii.h>
26 #include <miiphy.h>
27 #include <netdev.h>
28 #include <errno.h>
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 /*
33 * Functions
34 */
board_early_init_f(void)35 int board_early_init_f(void)
36 {
37 /* IO0 clock at 480MHz */
38 mxs_set_ioclk(MXC_IOCLK0, 480000);
39 /* IO1 clock at 480MHz */
40 mxs_set_ioclk(MXC_IOCLK1, 480000);
41
42 /* SSP0 clock at 96MHz */
43 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
44 /* SSP2 clock at 160MHz */
45 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
46
47 #ifdef CONFIG_CMD_USB
48 mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
49 mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
50 MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
51 gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
52 #endif
53
54 /* Power on LCD */
55 gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
56
57 /* Set contrast to maximum */
58 gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
59
60 return 0;
61 }
62
dram_init(void)63 int dram_init(void)
64 {
65 return mxs_dram_init();
66 }
67
board_init(void)68 int board_init(void)
69 {
70 /* Adress of boot parameters */
71 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
72
73 return 0;
74 }
75
76 #ifdef CONFIG_CMD_MMC
mx28evk_mmc_wp(int id)77 static int mx28evk_mmc_wp(int id)
78 {
79 if (id != 0) {
80 printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
81 return 1;
82 }
83
84 return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
85 }
86
board_mmc_init(struct bd_info * bis)87 int board_mmc_init(struct bd_info *bis)
88 {
89 /* Configure WP as input */
90 gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
91
92 /* Configure MMC0 Power Enable */
93 gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
94
95 return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
96 }
97 #endif
98
99 #ifdef CONFIG_CMD_NET
100
board_eth_init(struct bd_info * bis)101 int board_eth_init(struct bd_info *bis)
102 {
103 struct mxs_clkctrl_regs *clkctrl_regs =
104 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
105 struct eth_device *dev;
106 int ret;
107
108 ret = cpu_eth_init(bis);
109 if (ret)
110 return ret;
111
112 /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
113 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
114 &clkctrl_regs->hw_clkctrl_enet);
115
116 /* Power-on FECs */
117 gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
118
119 /* Reset FEC PHYs */
120 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
121 udelay(200);
122 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
123
124 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
125 if (ret) {
126 puts("FEC MXS: Unable to init FEC0\n");
127 return ret;
128 }
129
130 ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
131 if (ret) {
132 puts("FEC MXS: Unable to init FEC1\n");
133 return ret;
134 }
135
136 dev = eth_get_dev_by_name("FEC0");
137 if (!dev) {
138 puts("FEC MXS: Unable to get FEC0 device entry\n");
139 return -EINVAL;
140 }
141
142 dev = eth_get_dev_by_name("FEC1");
143 if (!dev) {
144 puts("FEC MXS: Unable to get FEC1 device entry\n");
145 return -EINVAL;
146 }
147
148 return ret;
149 }
150
151 #endif
152