1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell Armada 37xx SoC Time Base Generator clocks
4 *
5 * Marek Behun <marek.behun@nic.cz>
6 *
7 * Based on Linux driver by:
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 */
10
11 #include <common.h>
12 #include <clk-uclass.h>
13 #include <clk.h>
14 #include <dm.h>
15 #include <asm/io.h>
16 #include <asm/arch/cpu.h>
17 #include <dm/device_compat.h>
18
19 #define NUM_TBG 4
20
21 #define TBG_CTRL0 0x4
22 #define TBG_CTRL1 0x8
23 #define TBG_CTRL7 0x20
24 #define TBG_CTRL8 0x30
25
26 #define TBG_DIV_MASK 0x1FF
27
28 #define TBG_A_REFDIV 0
29 #define TBG_B_REFDIV 16
30
31 #define TBG_A_FBDIV 2
32 #define TBG_B_FBDIV 18
33
34 #define TBG_A_VCODIV_SE 0
35 #define TBG_B_VCODIV_SE 16
36
37 #define TBG_A_VCODIV_DIFF 1
38 #define TBG_B_VCODIV_DIFF 17
39
40 struct tbg_def {
41 const char *name;
42 u32 refdiv_offset;
43 u32 fbdiv_offset;
44 u32 vcodiv_reg;
45 u32 vcodiv_offset;
46 };
47
48 static const struct tbg_def tbg[NUM_TBG] = {
49 {"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF},
50 {"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF},
51 {"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE},
52 {"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE},
53 };
54
55 struct a37xx_tbgclk {
56 ulong rates[NUM_TBG];
57 unsigned int mult[NUM_TBG];
58 unsigned int div[NUM_TBG];
59 };
60
tbg_get_mult(void __iomem * reg,const struct tbg_def * ptbg)61 static unsigned int tbg_get_mult(void __iomem *reg, const struct tbg_def *ptbg)
62 {
63 u32 val;
64
65 val = readl(reg + TBG_CTRL0);
66
67 return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2;
68 }
69
tbg_get_div(void __iomem * reg,const struct tbg_def * ptbg)70 static unsigned int tbg_get_div(void __iomem *reg, const struct tbg_def *ptbg)
71 {
72 u32 val;
73 unsigned int div;
74
75 val = readl(reg + TBG_CTRL7);
76
77 div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK;
78 if (div == 0)
79 div = 1;
80 val = readl(reg + ptbg->vcodiv_reg);
81
82 div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK);
83
84 return div;
85 }
86
armada_37xx_tbg_clk_get_rate(struct clk * clk)87 static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk)
88 {
89 struct a37xx_tbgclk *priv = dev_get_priv(clk->dev);
90
91 if (clk->id >= NUM_TBG)
92 return -ENODEV;
93
94 return priv->rates[clk->id];
95 }
96
97 #if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720)
armada_37xx_tbg_clk_dump(struct udevice * dev)98 int armada_37xx_tbg_clk_dump(struct udevice *dev)
99 {
100 struct a37xx_tbgclk *priv = dev_get_priv(dev);
101 int i;
102
103 for (i = 0; i < NUM_TBG; ++i)
104 printf(" %s at %lu Hz\n", tbg[i].name,
105 priv->rates[i]);
106 printf("\n");
107
108 return 0;
109 }
110 #endif
111
armada_37xx_tbg_clk_probe(struct udevice * dev)112 static int armada_37xx_tbg_clk_probe(struct udevice *dev)
113 {
114 struct a37xx_tbgclk *priv = dev_get_priv(dev);
115 void __iomem *reg;
116 ulong xtal;
117 int i;
118
119 reg = dev_read_addr_ptr(dev);
120 if (!reg) {
121 dev_err(dev, "no io address\n");
122 return -ENODEV;
123 }
124
125 xtal = (ulong)get_ref_clk() * 1000000;
126
127 for (i = 0; i < NUM_TBG; ++i) {
128 unsigned int mult, div;
129
130 mult = tbg_get_mult(reg, &tbg[i]);
131 div = tbg_get_div(reg, &tbg[i]);
132
133 priv->rates[i] = (xtal * mult) / div;
134 }
135
136 return 0;
137 }
138
139 static const struct clk_ops armada_37xx_tbg_clk_ops = {
140 .get_rate = armada_37xx_tbg_clk_get_rate,
141 };
142
143 static const struct udevice_id armada_37xx_tbg_clk_ids[] = {
144 { .compatible = "marvell,armada-3700-tbg-clock" },
145 {}
146 };
147
148 U_BOOT_DRIVER(armada_37xx_tbg_clk) = {
149 .name = "armada_37xx_tbg_clk",
150 .id = UCLASS_CLK,
151 .of_match = armada_37xx_tbg_clk_ids,
152 .ops = &armada_37xx_tbg_clk_ops,
153 .priv_auto = sizeof(struct a37xx_tbgclk),
154 .probe = armada_37xx_tbg_clk_probe,
155 };
156