1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
5 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
6 * (C) Copyright 2006 DENX Software Engineering
7 */
8
9 #include <common.h>
10 #include <log.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <memalign.h>
14 #include <nand.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/funcmux.h>
17 #include <asm/arch-tegra/clk_rst.h>
18 #include <dm/device_compat.h>
19 #include <linux/bug.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <asm/gpio.h>
23 #include <fdtdec.h>
24 #include <bouncebuf.h>
25 #include <dm.h>
26 #include "tegra_nand.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define NAND_CMD_TIMEOUT_MS 10
31
32 #define SKIPPED_SPARE_BYTES 4
33
34 /* ECC bytes to be generated for tag data */
35 #define TAG_ECC_BYTES 4
36
37 static const struct udevice_id tegra_nand_dt_ids[] = {
38 {
39 .compatible = "nvidia,tegra20-nand",
40 },
41 { /* sentinel */ }
42 };
43
44 /* 64 byte oob block info for large page (== 2KB) device
45 *
46 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
47 * Skipped bytes(4)
48 * Main area Ecc(36)
49 * Tag data(20)
50 * Tag data Ecc(4)
51 *
52 * Yaffs2 will use 16 tag bytes.
53 */
54 static struct nand_ecclayout eccoob = {
55 .eccbytes = 36,
56 .eccpos = {
57 4, 5, 6, 7, 8, 9, 10, 11, 12,
58 13, 14, 15, 16, 17, 18, 19, 20, 21,
59 22, 23, 24, 25, 26, 27, 28, 29, 30,
60 31, 32, 33, 34, 35, 36, 37, 38, 39,
61 },
62 .oobavail = 20,
63 .oobfree = {
64 {
65 .offset = 40,
66 .length = 20,
67 },
68 }
69 };
70
71 enum {
72 ECC_OK,
73 ECC_TAG_ERROR = 1 << 0,
74 ECC_DATA_ERROR = 1 << 1
75 };
76
77 /* Timing parameters */
78 enum {
79 FDT_NAND_MAX_TRP_TREA,
80 FDT_NAND_TWB,
81 FDT_NAND_MAX_TCR_TAR_TRR,
82 FDT_NAND_TWHR,
83 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
84 FDT_NAND_TWH,
85 FDT_NAND_TWP,
86 FDT_NAND_TRH,
87 FDT_NAND_TADL,
88
89 FDT_NAND_TIMING_COUNT
90 };
91
92 /* Information about an attached NAND chip */
93 struct fdt_nand {
94 struct nand_ctlr *reg;
95 int enabled; /* 1 to enable, 0 to disable */
96 struct gpio_desc wp_gpio; /* write-protect GPIO */
97 s32 width; /* bit width, normally 8 */
98 u32 timing[FDT_NAND_TIMING_COUNT];
99 };
100
101 struct nand_drv {
102 struct nand_ctlr *reg;
103 struct fdt_nand config;
104 };
105
106 struct tegra_nand_info {
107 struct udevice *dev;
108 struct nand_drv nand_ctrl;
109 struct nand_chip nand_chip;
110 };
111
112 /**
113 * Wait for command completion
114 *
115 * @param reg nand_ctlr structure
116 * @return
117 * 1 - Command completed
118 * 0 - Timeout
119 */
nand_waitfor_cmd_completion(struct nand_ctlr * reg)120 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
121 {
122 u32 reg_val;
123 int running;
124 int i;
125
126 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
127 if ((readl(®->command) & CMD_GO) ||
128 !(readl(®->status) & STATUS_RBSY0) ||
129 !(readl(®->isr) & ISR_IS_CMD_DONE)) {
130 udelay(1);
131 continue;
132 }
133 reg_val = readl(®->dma_mst_ctrl);
134 /*
135 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
136 * is set, that means DMA engine is running.
137 *
138 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
139 * is cleared, indicating DMA transfer completion.
140 */
141 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
142 DMA_MST_CTRL_EN_B_ENABLE);
143 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
144 return 1;
145 udelay(1);
146 }
147 return 0;
148 }
149
150 /**
151 * Read one byte from the chip
152 *
153 * @param mtd MTD device structure
154 * @return data byte
155 *
156 * Read function for 8bit bus-width
157 */
read_byte(struct mtd_info * mtd)158 static uint8_t read_byte(struct mtd_info *mtd)
159 {
160 struct nand_chip *chip = mtd_to_nand(mtd);
161 struct nand_drv *info;
162
163 info = (struct nand_drv *)nand_get_controller_data(chip);
164
165 writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
166 &info->reg->command);
167 if (!nand_waitfor_cmd_completion(info->reg))
168 printf("Command timeout\n");
169
170 return (uint8_t)readl(&info->reg->resp);
171 }
172
173 /**
174 * Read len bytes from the chip into a buffer
175 *
176 * @param mtd MTD device structure
177 * @param buf buffer to store data to
178 * @param len number of bytes to read
179 *
180 * Read function for 8bit bus-width
181 */
read_buf(struct mtd_info * mtd,uint8_t * buf,int len)182 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
183 {
184 int i, s;
185 unsigned int reg;
186 struct nand_chip *chip = mtd_to_nand(mtd);
187 struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
188
189 for (i = 0; i < len; i += 4) {
190 s = (len - i) > 4 ? 4 : len - i;
191 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
192 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
193 &info->reg->command);
194 if (!nand_waitfor_cmd_completion(info->reg))
195 puts("Command timeout during read_buf\n");
196 reg = readl(&info->reg->resp);
197 memcpy(buf + i, ®, s);
198 }
199 }
200
201 /**
202 * Check NAND status to see if it is ready or not
203 *
204 * @param mtd MTD device structure
205 * @return
206 * 1 - ready
207 * 0 - not ready
208 */
nand_dev_ready(struct mtd_info * mtd)209 static int nand_dev_ready(struct mtd_info *mtd)
210 {
211 struct nand_chip *chip = mtd_to_nand(mtd);
212 int reg_val;
213 struct nand_drv *info;
214
215 info = (struct nand_drv *)nand_get_controller_data(chip);
216
217 reg_val = readl(&info->reg->status);
218 if (reg_val & STATUS_RBSY0)
219 return 1;
220 else
221 return 0;
222 }
223
224 /* Dummy implementation: we don't support multiple chips */
nand_select_chip(struct mtd_info * mtd,int chipnr)225 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
226 {
227 switch (chipnr) {
228 case -1:
229 case 0:
230 break;
231
232 default:
233 BUG();
234 }
235 }
236
237 /**
238 * Clear all interrupt status bits
239 *
240 * @param reg nand_ctlr structure
241 */
nand_clear_interrupt_status(struct nand_ctlr * reg)242 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
243 {
244 u32 reg_val;
245
246 /* Clear interrupt status */
247 reg_val = readl(®->isr);
248 writel(reg_val, ®->isr);
249 }
250
251 /**
252 * Send command to NAND device
253 *
254 * @param mtd MTD device structure
255 * @param command the command to be sent
256 * @param column the column address for this command, -1 if none
257 * @param page_addr the page address for this command, -1 if none
258 */
nand_command(struct mtd_info * mtd,unsigned int command,int column,int page_addr)259 static void nand_command(struct mtd_info *mtd, unsigned int command,
260 int column, int page_addr)
261 {
262 struct nand_chip *chip = mtd_to_nand(mtd);
263 struct nand_drv *info;
264
265 info = (struct nand_drv *)nand_get_controller_data(chip);
266
267 /*
268 * Write out the command to the device.
269 *
270 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
271 * here before mtd->writesize is initialized.
272 */
273
274 /* Emulate NAND_CMD_READOOB */
275 if (command == NAND_CMD_READOOB) {
276 assert(mtd->writesize != 0);
277 column += mtd->writesize;
278 command = NAND_CMD_READ0;
279 }
280
281 /* Adjust columns for 16 bit bus-width */
282 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
283 column >>= 1;
284
285 nand_clear_interrupt_status(info->reg);
286
287 /* Stop DMA engine, clear DMA completion status */
288 writel(DMA_MST_CTRL_EN_A_DISABLE
289 | DMA_MST_CTRL_EN_B_DISABLE
290 | DMA_MST_CTRL_IS_DMA_DONE,
291 &info->reg->dma_mst_ctrl);
292
293 /*
294 * Program and erase have their own busy handlers
295 * status and sequential in needs no delay
296 */
297 switch (command) {
298 case NAND_CMD_READID:
299 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
300 writel(column & 0xFF, &info->reg->addr_reg1);
301 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
302 &info->reg->command);
303 break;
304 case NAND_CMD_PARAM:
305 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
306 writel(column & 0xFF, &info->reg->addr_reg1);
307 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
308 &info->reg->command);
309 break;
310 case NAND_CMD_READ0:
311 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
312 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
313 writel((page_addr << 16) | (column & 0xFFFF),
314 &info->reg->addr_reg1);
315 writel(page_addr >> 16, &info->reg->addr_reg2);
316 return;
317 case NAND_CMD_SEQIN:
318 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
319 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
320 writel((page_addr << 16) | (column & 0xFFFF),
321 &info->reg->addr_reg1);
322 writel(page_addr >> 16,
323 &info->reg->addr_reg2);
324 return;
325 case NAND_CMD_PAGEPROG:
326 return;
327 case NAND_CMD_ERASE1:
328 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
329 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
330 writel(page_addr, &info->reg->addr_reg1);
331 writel(CMD_GO | CMD_CLE | CMD_ALE |
332 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
333 &info->reg->command);
334 break;
335 case NAND_CMD_ERASE2:
336 return;
337 case NAND_CMD_STATUS:
338 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
339 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
340 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
341 | CMD_CE0,
342 &info->reg->command);
343 break;
344 case NAND_CMD_RESET:
345 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
346 writel(CMD_GO | CMD_CLE | CMD_CE0,
347 &info->reg->command);
348 break;
349 case NAND_CMD_RNDOUT:
350 default:
351 printf("%s: Unsupported command %d\n", __func__, command);
352 return;
353 }
354 if (!nand_waitfor_cmd_completion(info->reg))
355 printf("Command 0x%02X timeout\n", command);
356 }
357
358 /**
359 * Check whether the pointed buffer are all 0xff (blank).
360 *
361 * @param buf data buffer for blank check
362 * @param len length of the buffer in byte
363 * @return
364 * 1 - blank
365 * 0 - non-blank
366 */
blank_check(u8 * buf,int len)367 static int blank_check(u8 *buf, int len)
368 {
369 int i;
370
371 for (i = 0; i < len; i++)
372 if (buf[i] != 0xFF)
373 return 0;
374 return 1;
375 }
376
377 /**
378 * After a DMA transfer for read, we call this function to see whether there
379 * is any uncorrectable error on the pointed data buffer or oob buffer.
380 *
381 * @param reg nand_ctlr structure
382 * @param databuf data buffer
383 * @param a_len data buffer length
384 * @param oobbuf oob buffer
385 * @param b_len oob buffer length
386 * @return
387 * ECC_OK - no ECC error or correctable ECC error
388 * ECC_TAG_ERROR - uncorrectable tag ECC error
389 * ECC_DATA_ERROR - uncorrectable data ECC error
390 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
391 */
check_ecc_error(struct nand_ctlr * reg,u8 * databuf,int a_len,u8 * oobbuf,int b_len)392 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
393 int a_len, u8 *oobbuf, int b_len)
394 {
395 int return_val = ECC_OK;
396 u32 reg_val;
397
398 if (!(readl(®->isr) & ISR_IS_ECC_ERR))
399 return ECC_OK;
400
401 /*
402 * Area A is used for the data block (databuf). Area B is used for
403 * the spare block (oobbuf)
404 */
405 reg_val = readl(®->dec_status);
406 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
407 reg_val = readl(®->bch_dec_status_buf);
408 /*
409 * If uncorrectable error occurs on data area, then see whether
410 * they are all FF. If all are FF, it's a blank page.
411 * Not error.
412 */
413 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
414 !blank_check(databuf, a_len))
415 return_val |= ECC_DATA_ERROR;
416 }
417
418 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
419 reg_val = readl(®->bch_dec_status_buf);
420 /*
421 * If uncorrectable error occurs on tag area, then see whether
422 * they are all FF. If all are FF, it's a blank page.
423 * Not error.
424 */
425 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
426 !blank_check(oobbuf, b_len))
427 return_val |= ECC_TAG_ERROR;
428 }
429
430 return return_val;
431 }
432
433 /**
434 * Set GO bit to send command to device
435 *
436 * @param reg nand_ctlr structure
437 */
start_command(struct nand_ctlr * reg)438 static void start_command(struct nand_ctlr *reg)
439 {
440 u32 reg_val;
441
442 reg_val = readl(®->command);
443 reg_val |= CMD_GO;
444 writel(reg_val, ®->command);
445 }
446
447 /**
448 * Clear command GO bit, DMA GO bit, and DMA completion status
449 *
450 * @param reg nand_ctlr structure
451 */
stop_command(struct nand_ctlr * reg)452 static void stop_command(struct nand_ctlr *reg)
453 {
454 /* Stop command */
455 writel(0, ®->command);
456
457 /* Stop DMA engine and clear DMA completion status */
458 writel(DMA_MST_CTRL_GO_DISABLE
459 | DMA_MST_CTRL_IS_DMA_DONE,
460 ®->dma_mst_ctrl);
461 }
462
463 /**
464 * Set up NAND bus width and page size
465 *
466 * @param info nand_info structure
467 * @param *reg_val address of reg_val
468 * @return 0 if ok, -1 on error
469 */
set_bus_width_page_size(struct mtd_info * our_mtd,struct fdt_nand * config,u32 * reg_val)470 static int set_bus_width_page_size(struct mtd_info *our_mtd,
471 struct fdt_nand *config, u32 *reg_val)
472 {
473 if (config->width == 8)
474 *reg_val = CFG_BUS_WIDTH_8BIT;
475 else if (config->width == 16)
476 *reg_val = CFG_BUS_WIDTH_16BIT;
477 else {
478 debug("%s: Unsupported bus width %d\n", __func__,
479 config->width);
480 return -1;
481 }
482
483 if (our_mtd->writesize == 512)
484 *reg_val |= CFG_PAGE_SIZE_512;
485 else if (our_mtd->writesize == 2048)
486 *reg_val |= CFG_PAGE_SIZE_2048;
487 else if (our_mtd->writesize == 4096)
488 *reg_val |= CFG_PAGE_SIZE_4096;
489 else {
490 debug("%s: Unsupported page size %d\n", __func__,
491 our_mtd->writesize);
492 return -1;
493 }
494
495 return 0;
496 }
497
498 /**
499 * Page read/write function
500 *
501 * @param mtd mtd info structure
502 * @param chip nand chip info structure
503 * @param buf data buffer
504 * @param page page number
505 * @param with_ecc 1 to enable ECC, 0 to disable ECC
506 * @param is_writing 0 for read, 1 for write
507 * @return 0 when successfully completed
508 * -EIO when command timeout
509 */
nand_rw_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int page,int with_ecc,int is_writing)510 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
511 uint8_t *buf, int page, int with_ecc, int is_writing)
512 {
513 u32 reg_val;
514 int tag_size;
515 struct nand_oobfree *free = chip->ecc.layout->oobfree;
516 /* 4*128=512 (byte) is the value that our HW can support. */
517 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
518 char *tag_ptr;
519 struct nand_drv *info;
520 struct fdt_nand *config;
521 unsigned int bbflags;
522 struct bounce_buffer bbstate, bbstate_oob;
523
524 if ((uintptr_t)buf & 0x03) {
525 printf("buf %p has to be 4-byte aligned\n", buf);
526 return -EINVAL;
527 }
528
529 info = (struct nand_drv *)nand_get_controller_data(chip);
530 config = &info->config;
531 if (set_bus_width_page_size(mtd, config, ®_val))
532 return -EINVAL;
533
534 /* Need to be 4-byte aligned */
535 tag_ptr = (char *)tag_buf;
536
537 stop_command(info->reg);
538
539 if (is_writing)
540 bbflags = GEN_BB_READ;
541 else
542 bbflags = GEN_BB_WRITE;
543
544 bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
545 bbflags);
546 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
547 writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
548
549 /* Set ECC selection, configure ECC settings */
550 if (with_ecc) {
551 if (is_writing)
552 memcpy(tag_ptr, chip->oob_poi + free->offset,
553 chip->ecc.layout->oobavail + TAG_ECC_BYTES);
554 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
555 reg_val |= (CFG_SKIP_SPARE_SEL_4
556 | CFG_SKIP_SPARE_ENABLE
557 | CFG_HW_ECC_CORRECTION_ENABLE
558 | CFG_ECC_EN_TAG_DISABLE
559 | CFG_HW_ECC_SEL_RS
560 | CFG_HW_ECC_ENABLE
561 | CFG_TVAL4
562 | (tag_size - 1));
563
564 if (!is_writing)
565 tag_size += SKIPPED_SPARE_BYTES;
566 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
567 bbflags);
568 } else {
569 tag_size = mtd->oobsize;
570 reg_val |= (CFG_SKIP_SPARE_DISABLE
571 | CFG_HW_ECC_CORRECTION_DISABLE
572 | CFG_ECC_EN_TAG_DISABLE
573 | CFG_HW_ECC_DISABLE
574 | (tag_size - 1));
575 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
576 tag_size, bbflags);
577 }
578 writel(reg_val, &info->reg->config);
579 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
580 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
581 writel(tag_size - 1, &info->reg->dma_cfg_b);
582
583 nand_clear_interrupt_status(info->reg);
584
585 reg_val = CMD_CLE | CMD_ALE
586 | CMD_SEC_CMD
587 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
588 | CMD_A_VALID
589 | CMD_B_VALID
590 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
591 | CMD_CE0;
592 if (!is_writing)
593 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
594 else
595 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
596 writel(reg_val, &info->reg->command);
597
598 /* Setup DMA engine */
599 reg_val = DMA_MST_CTRL_GO_ENABLE
600 | DMA_MST_CTRL_BURST_8WORDS
601 | DMA_MST_CTRL_EN_A_ENABLE
602 | DMA_MST_CTRL_EN_B_ENABLE;
603
604 if (!is_writing)
605 reg_val |= DMA_MST_CTRL_DIR_READ;
606 else
607 reg_val |= DMA_MST_CTRL_DIR_WRITE;
608
609 writel(reg_val, &info->reg->dma_mst_ctrl);
610
611 start_command(info->reg);
612
613 if (!nand_waitfor_cmd_completion(info->reg)) {
614 if (!is_writing)
615 printf("Read Page 0x%X timeout ", page);
616 else
617 printf("Write Page 0x%X timeout ", page);
618 if (with_ecc)
619 printf("with ECC");
620 else
621 printf("without ECC");
622 printf("\n");
623 return -EIO;
624 }
625
626 bounce_buffer_stop(&bbstate_oob);
627 bounce_buffer_stop(&bbstate);
628
629 if (with_ecc && !is_writing) {
630 memcpy(chip->oob_poi, tag_ptr,
631 SKIPPED_SPARE_BYTES);
632 memcpy(chip->oob_poi + free->offset,
633 tag_ptr + SKIPPED_SPARE_BYTES,
634 chip->ecc.layout->oobavail);
635 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
636 1 << chip->page_shift,
637 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
638 chip->ecc.layout->oobavail);
639 if (reg_val & ECC_TAG_ERROR)
640 printf("Read Page 0x%X tag ECC error\n", page);
641 if (reg_val & ECC_DATA_ERROR)
642 printf("Read Page 0x%X data ECC error\n",
643 page);
644 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
645 return -EIO;
646 }
647 return 0;
648 }
649
650 /**
651 * Hardware ecc based page read function
652 *
653 * @param mtd mtd info structure
654 * @param chip nand chip info structure
655 * @param buf buffer to store read data
656 * @param page page number to read
657 * @return 0 when successfully completed
658 * -EIO when command timeout
659 */
nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)660 static int nand_read_page_hwecc(struct mtd_info *mtd,
661 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
662 {
663 return nand_rw_page(mtd, chip, buf, page, 1, 0);
664 }
665
666 /**
667 * Hardware ecc based page write function
668 *
669 * @param mtd mtd info structure
670 * @param chip nand chip info structure
671 * @param buf data buffer
672 */
nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)673 static int nand_write_page_hwecc(struct mtd_info *mtd,
674 struct nand_chip *chip, const uint8_t *buf, int oob_required,
675 int page)
676 {
677 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
678 return 0;
679 }
680
681
682 /**
683 * Read raw page data without ecc
684 *
685 * @param mtd mtd info structure
686 * @param chip nand chip info structure
687 * @param buf buffer to store read data
688 * @param page page number to read
689 * @return 0 when successfully completed
690 * -EINVAL when chip->oob_poi is not double-word aligned
691 * -EIO when command timeout
692 */
nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)693 static int nand_read_page_raw(struct mtd_info *mtd,
694 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
695 {
696 return nand_rw_page(mtd, chip, buf, page, 0, 0);
697 }
698
699 /**
700 * Raw page write function
701 *
702 * @param mtd mtd info structure
703 * @param chip nand chip info structure
704 * @param buf data buffer
705 */
nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)706 static int nand_write_page_raw(struct mtd_info *mtd,
707 struct nand_chip *chip, const uint8_t *buf,
708 int oob_required, int page)
709 {
710 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
711 return 0;
712 }
713
714 /**
715 * OOB data read/write function
716 *
717 * @param mtd mtd info structure
718 * @param chip nand chip info structure
719 * @param page page number to read
720 * @param with_ecc 1 to enable ECC, 0 to disable ECC
721 * @param is_writing 0 for read, 1 for write
722 * @return 0 when successfully completed
723 * -EINVAL when chip->oob_poi is not double-word aligned
724 * -EIO when command timeout
725 */
nand_rw_oob(struct mtd_info * mtd,struct nand_chip * chip,int page,int with_ecc,int is_writing)726 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
727 int page, int with_ecc, int is_writing)
728 {
729 u32 reg_val;
730 int tag_size;
731 struct nand_oobfree *free = chip->ecc.layout->oobfree;
732 struct nand_drv *info;
733 unsigned int bbflags;
734 struct bounce_buffer bbstate_oob;
735
736 if (((int)chip->oob_poi) & 0x03)
737 return -EINVAL;
738 info = (struct nand_drv *)nand_get_controller_data(chip);
739 if (set_bus_width_page_size(mtd, &info->config, ®_val))
740 return -EINVAL;
741
742 stop_command(info->reg);
743
744 /* Set ECC selection */
745 tag_size = mtd->oobsize;
746 if (with_ecc)
747 reg_val |= CFG_ECC_EN_TAG_ENABLE;
748 else
749 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
750
751 reg_val |= ((tag_size - 1) |
752 CFG_SKIP_SPARE_DISABLE |
753 CFG_HW_ECC_CORRECTION_DISABLE |
754 CFG_HW_ECC_DISABLE);
755 writel(reg_val, &info->reg->config);
756
757 if (is_writing && with_ecc)
758 tag_size -= TAG_ECC_BYTES;
759
760 if (is_writing)
761 bbflags = GEN_BB_READ;
762 else
763 bbflags = GEN_BB_WRITE;
764
765 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
766 bbflags);
767 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
768
769 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
770
771 writel(tag_size - 1, &info->reg->dma_cfg_b);
772
773 nand_clear_interrupt_status(info->reg);
774
775 reg_val = CMD_CLE | CMD_ALE
776 | CMD_SEC_CMD
777 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
778 | CMD_B_VALID
779 | CMD_CE0;
780 if (!is_writing)
781 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
782 else
783 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
784 writel(reg_val, &info->reg->command);
785
786 /* Setup DMA engine */
787 reg_val = DMA_MST_CTRL_GO_ENABLE
788 | DMA_MST_CTRL_BURST_8WORDS
789 | DMA_MST_CTRL_EN_B_ENABLE;
790 if (!is_writing)
791 reg_val |= DMA_MST_CTRL_DIR_READ;
792 else
793 reg_val |= DMA_MST_CTRL_DIR_WRITE;
794
795 writel(reg_val, &info->reg->dma_mst_ctrl);
796
797 start_command(info->reg);
798
799 if (!nand_waitfor_cmd_completion(info->reg)) {
800 if (!is_writing)
801 printf("Read OOB of Page 0x%X timeout\n", page);
802 else
803 printf("Write OOB of Page 0x%X timeout\n", page);
804 return -EIO;
805 }
806
807 bounce_buffer_stop(&bbstate_oob);
808
809 if (with_ecc && !is_writing) {
810 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
811 (u8 *)(chip->oob_poi + free->offset),
812 chip->ecc.layout->oobavail);
813 if (reg_val & ECC_TAG_ERROR)
814 printf("Read OOB of Page 0x%X tag ECC error\n", page);
815 }
816 return 0;
817 }
818
819 /**
820 * OOB data read function
821 *
822 * @param mtd mtd info structure
823 * @param chip nand chip info structure
824 * @param page page number to read
825 */
nand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)826 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
827 int page)
828 {
829 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
830 nand_rw_oob(mtd, chip, page, 0, 0);
831 return 0;
832 }
833
834 /**
835 * OOB data write function
836 *
837 * @param mtd mtd info structure
838 * @param chip nand chip info structure
839 * @param page page number to write
840 * @return 0 when successfully completed
841 * -EINVAL when chip->oob_poi is not double-word aligned
842 * -EIO when command timeout
843 */
nand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)844 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
845 int page)
846 {
847 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
848
849 return nand_rw_oob(mtd, chip, page, 0, 1);
850 }
851
852 /**
853 * Set up NAND memory timings according to the provided parameters
854 *
855 * @param timing Timing parameters
856 * @param reg NAND controller register address
857 */
setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],struct nand_ctlr * reg)858 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
859 struct nand_ctlr *reg)
860 {
861 u32 reg_val, clk_rate, clk_period, time_val;
862
863 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
864 CLOCK_ID_PERIPH) / 1000000;
865 clk_period = 1000 / clk_rate;
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
867 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
869 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
871 if (time_val > 2)
872 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
873 TIMING_TCR_TAR_TRR_CNT_MASK;
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
875 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
876 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
877 if (time_val > 1)
878 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
879 TIMING_TCS_CNT_MASK;
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
881 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
883 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
885 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
887 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
888 writel(reg_val, ®->timing);
889
890 reg_val = 0;
891 time_val = timing[FDT_NAND_TADL] / clk_period;
892 if (time_val > 2)
893 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
894 writel(reg_val, ®->timing2);
895 }
896
897 /**
898 * Decode NAND parameters from the device tree
899 *
900 * @param dev Driver model device
901 * @param config Device tree NAND configuration
902 * @return 0 if ok, -ve on error (FDT_ERR_...)
903 */
fdt_decode_nand(struct udevice * dev,struct fdt_nand * config)904 static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
905 {
906 int err;
907
908 config->reg = (struct nand_ctlr *)dev_read_addr(dev);
909 config->enabled = dev_read_enabled(dev);
910 config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
911 err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
912 GPIOD_IS_OUT);
913 if (err)
914 return err;
915 err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
916 FDT_NAND_TIMING_COUNT);
917 if (err < 0)
918 return err;
919
920 return 0;
921 }
922
tegra_probe(struct udevice * dev)923 static int tegra_probe(struct udevice *dev)
924 {
925 struct tegra_nand_info *tegra = dev_get_priv(dev);
926 struct nand_chip *nand = &tegra->nand_chip;
927 struct nand_drv *info = &tegra->nand_ctrl;
928 struct fdt_nand *config = &info->config;
929 struct mtd_info *our_mtd;
930 int ret;
931
932 if (fdt_decode_nand(dev, config)) {
933 printf("Could not decode nand-flash in device tree\n");
934 return -1;
935 }
936 if (!config->enabled)
937 return -1;
938 info->reg = config->reg;
939 nand->ecc.mode = NAND_ECC_HW;
940 nand->ecc.layout = &eccoob;
941
942 nand->options = LP_OPTIONS;
943 nand->cmdfunc = nand_command;
944 nand->read_byte = read_byte;
945 nand->read_buf = read_buf;
946 nand->ecc.read_page = nand_read_page_hwecc;
947 nand->ecc.write_page = nand_write_page_hwecc;
948 nand->ecc.read_page_raw = nand_read_page_raw;
949 nand->ecc.write_page_raw = nand_write_page_raw;
950 nand->ecc.read_oob = nand_read_oob;
951 nand->ecc.write_oob = nand_write_oob;
952 nand->ecc.strength = 1;
953 nand->select_chip = nand_select_chip;
954 nand->dev_ready = nand_dev_ready;
955 nand_set_controller_data(nand, &tegra->nand_ctrl);
956
957 /* Disable subpage writes as we do not provide ecc->hwctl */
958 nand->options |= NAND_NO_SUBPAGE_WRITE;
959
960 /* Adjust controller clock rate */
961 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
962
963 /* Adjust timing for NAND device */
964 setup_timing(config->timing, info->reg);
965
966 dm_gpio_set_value(&config->wp_gpio, 1);
967
968 our_mtd = nand_to_mtd(nand);
969 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
970 if (ret)
971 return ret;
972
973 nand->ecc.size = our_mtd->writesize;
974 nand->ecc.bytes = our_mtd->oobsize;
975
976 ret = nand_scan_tail(our_mtd);
977 if (ret)
978 return ret;
979
980 ret = nand_register(0, our_mtd);
981 if (ret) {
982 dev_err(dev, "Failed to register MTD: %d\n", ret);
983 return ret;
984 }
985
986 return 0;
987 }
988
989 U_BOOT_DRIVER(tegra_nand) = {
990 .name = "tegra-nand",
991 .id = UCLASS_MTD,
992 .of_match = tegra_nand_dt_ids,
993 .probe = tegra_probe,
994 .priv_auto = sizeof(struct tegra_nand_info),
995 };
996
board_nand_init(void)997 void board_nand_init(void)
998 {
999 struct udevice *dev;
1000 int ret;
1001
1002 ret = uclass_get_device_by_driver(UCLASS_MTD,
1003 DM_DRIVER_GET(tegra_nand), &dev);
1004 if (ret && ret != -ENODEV)
1005 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
1006 ret);
1007 }
1008