1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 380 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 */
11
12#include "armada-38x.dtsi"
13
14/ {
15	model = "Marvell Armada 380 family SoC";
16	compatible = "marvell,armada380";
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21		enable-method = "marvell,armada-380-smp";
22
23		cpu@0 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a9";
26			reg = <0>;
27		};
28	};
29
30	soc {
31		internal-regs {
32			pinctrl@18000 {
33				compatible = "marvell,mv88f6810-pinctrl";
34			};
35		};
36
37		pcie {
38			compatible = "marvell,armada-370-pcie";
39			status = "disabled";
40			device_type = "pci";
41
42			#address-cells = <3>;
43			#size-cells = <2>;
44
45			msi-parent = <&mpic>;
46			bus-range = <0x00 0xff>;
47
48			ranges =
49			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
50				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
52				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
53				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
55				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
57				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;
59
60			/* x1 port */
61			pcie@1,0 {
62				device_type = "pci";
63				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
64				reg = <0x0800 0 0 0 0>;
65				#address-cells = <3>;
66				#size-cells = <2>;
67				#interrupt-cells = <1>;
68				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
69					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
70				bus-range = <0x00 0xff>;
71				interrupt-map-mask = <0 0 0 0>;
72				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
73				marvell,pcie-port = <0>;
74				marvell,pcie-lane = <0>;
75				clocks = <&gateclk 8>;
76				status = "disabled";
77			};
78
79			/* x1 port */
80			pcie@2,0 {
81				device_type = "pci";
82				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83				reg = <0x1000 0 0 0 0>;
84				#address-cells = <3>;
85				#size-cells = <2>;
86				#interrupt-cells = <1>;
87				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
88					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
89				bus-range = <0x00 0xff>;
90				interrupt-map-mask = <0 0 0 0>;
91				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
92				marvell,pcie-port = <1>;
93				marvell,pcie-lane = <0>;
94				clocks = <&gateclk 5>;
95				status = "disabled";
96			};
97
98			/* x1 port */
99			pcie@3,0 {
100				device_type = "pci";
101				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
102				reg = <0x1800 0 0 0 0>;
103				#address-cells = <3>;
104				#size-cells = <2>;
105				#interrupt-cells = <1>;
106				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
107					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
108				bus-range = <0x00 0xff>;
109				interrupt-map-mask = <0 0 0 0>;
110				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
111				marvell,pcie-port = <2>;
112				marvell,pcie-lane = <0>;
113				clocks = <&gateclk 6>;
114				status = "disabled";
115			};
116		};
117	};
118};
119