1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for SolidRun Armada 38x Microsom
4 *
5 *  Copyright (C) 2015 Russell King
6 *
7 * This board is in development; the contents of this file work with
8 * the A1 rev 2.0 of the board, which does not represent final
9 * production board.  Things will change, don't expect this file to
10 * remain compatible info the future.
11 */
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16	memory {
17		device_type = "memory";
18		reg = <0x00000000 0x10000000>; /* 256 MB */
19	};
20
21	soc {
22		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
23			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
24			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
25			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
26			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
27
28		internal-regs {
29			rtc@a3800 {
30				/*
31				 * If the rtc doesn't work, run "date reset"
32				 * twice in u-boot.
33				 */
34				status = "okay";
35			};
36		};
37	};
38};
39
40&eth0 {
41	/* ethernet@70000 */
42	pinctrl-0 = <&ge0_rgmii_pins>;
43	pinctrl-names = "default";
44	phy = <&phy_dedicated>;
45	phy-mode = "rgmii-id";
46	status = "okay";
47};
48
49&mdio {
50	/*
51	 * Add the phy clock here, so the phy can be accessed to read its
52	 * IDs prior to binding with the driver.
53	 */
54	pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
55	pinctrl-names = "default";
56
57	phy_dedicated: ethernet-phy@0 {
58		/*
59		 * Annoyingly, the marvell phy driver configures the LED
60		 * register, rather than preserving reset-loaded setting.
61		 * We undo that rubbish here.
62		 */
63		marvell,reg-init = <3 16 0 0x101e>;
64		reg = <0>;
65	};
66};
67
68&pinctrl {
69	microsom_phy_clk_pins: microsom-phy-clk-pins {
70		marvell,pins = "mpp45";
71		marvell,function = "ref";
72	};
73	/* Optional eMMC */
74	microsom_sdhci_pins: microsom-sdhci-pins {
75		marvell,pins = "mpp21", "mpp28", "mpp37",
76			       "mpp38", "mpp39", "mpp40";
77		marvell,function = "sd0";
78	};
79};
80
81&spi1 {
82	/* The microsom has an optional W25Q32 on board, connected to CS0 */
83	pinctrl-0 = <&spi1_pins>;
84
85	w25q32: spi-flash@0 {
86		#address-cells = <1>;
87		#size-cells = <1>;
88		compatible = "w25q32", "jedec,spi-nor";
89		reg = <0>; /* Chip select 0 */
90		spi-max-frequency = <3000000>;
91		status = "disabled";
92	};
93};
94
95&uart0 {
96	pinctrl-0 = <&uart0_pins>;
97	pinctrl-names = "default";
98	status = "okay";
99	u-boot,dm-pre-reloc;
100};
101
102&i2c0 {
103	eeprom@53 {
104		compatible = "atmel,24c02";
105		reg = <0x53>;
106		pagesize = <16>;
107	};
108};
109